CN101055516A - Hardware configuration method implementing binary system polynomial arithmetic and hardware system - Google Patents
Hardware configuration method implementing binary system polynomial arithmetic and hardware system Download PDFInfo
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- CN101055516A CN101055516A CN 200710099807 CN200710099807A CN101055516A CN 101055516 A CN101055516 A CN 101055516A CN 200710099807 CN200710099807 CN 200710099807 CN 200710099807 A CN200710099807 A CN 200710099807A CN 101055516 A CN101055516 A CN 101055516A
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Abstract
The invention provides a hardware configuration method and hardware system for carrying out binary multinomial operation. The method includes: for n linear feedback shift register inputed with a serial data, each register respectively representing one item of x1 to xn of binary multinomial based on input output order; setting a coefficient of item of binary multinomial corresponding to the former register of the register by setting a conbination logic unit for carrying out a choice function at each input port of registers. The invention is able to agilely set a inear feedback shift logic of shift register on the hardware, and may accomplish binary multinomial operation having different prejects, including the project of different length, accordingly the effect for carrying out the hardware and the agility of system are improved greatly.
Description
Technical field
The present invention relates to communicate by letter and the data processing technique of microelectronic, particularly relate to a kind of hardware configuration method and hardware system of realizing the scale-of-two multinomial operation.
Background technology
The scale-of-two multinomial operation is the citation form that the data processing used always is calculated, and its typical application example comprises the cyclic redundancy check (CRC) (Cyclic Redundancy Check, abbreviation CRC) that is widely used in the communication system solution.In data handling procedure, adopt the data of binary representation, can be counted as a polynomial coefficient of scale-of-two, polynomial expression multiplication and division calculating process is identical with the multiplication and division of common algebraic polynomial, and polynomial signed magnitude arithmetic(al) is mould with 2, and is consistent with the logical difference exclusive disjunction.
With CRC is example, and when adopting CRC check, transmit leg and take over party use same generator polynomial g (x), and the first place of g (x) and last coefficient are necessary for 1.The disposal route of CRC is: transmit leg is removed data t (x) with g (x), obtains remainder as the CRC check sign indicating number; During verification, whether reciever is 0 to be certificate with the correction result that calculates, judges whether receive data makes mistakes.All be the scale-of-two multinomial operation in steps in the computation process.
The polynomial computation process of this scale-of-two is the Modulo-two operation of ring shift on hardware, the linear feedback shift register that the corresponding hardware of this computing is realized when data are the serial input, its linear feedback shift logic determines by computing formula, shows as the every corresponding one by one of shift register and generator polynomial g (x) in CRC.For example, if evaluator g (x)=x
3+ x+1 just must design the hardware circuit with three shift registers, respectively corresponding x
3, x
1, x
0, as can be seen, all to design hardware circuit respectively if calculate the polynomial expression of different length and different item, bother very much, efficient is very low.
Therefore, how to overcome in the prior art hardware realize can only corresponding a kind of numerical procedure defective, how to provide a kind of general hardware to realize, make the linear feedback shift logic reach configurableization, to support the scale-of-two multinomial operation of multiple scheme and even multiple length, be that problem to be solved is arranged.
Summary of the invention
The purpose of this invention is to provide a kind of hardware configuration method and hardware system of realizing the scale-of-two multinomial operation, a hardware that solves prior art is realized can only corresponding a kind of interpretative version, can not finish the technical matters of the scale-of-two multinomial operation of different schemes.
To achieve these goals, the invention provides a kind of hardware configuration method of realizing the scale-of-two multinomial operation, wherein, comprise the steps:
Above-mentioned method, wherein, also comprise: step 3, the value of each register is input to most significant digit selection logical block, and select the output of logical block to be connected to the XOR logical block of the input port of described combinatorial logic unit the described most significant digit, select logical block that polynomial of described scale-of-two is set by described most significant digit and allow the most significant digit that has.
Above-mentioned method wherein, in described step 2, is represented x
1The combinatorial logic unit of input port of shift register, be used for controlling the polynomial x of scale-of-two
0Coefficient.
Above-mentioned method wherein, is provided with parameters C and parameter K, and described parameters C comprises the combinatorial logic unit of the input port of the described n of the corresponding respectively input of a n binary number register, is used for selecting then x
0To x
N-1Coefficient, described parameter K is imported described most significant digit and is selected logical block, realizes that described most significant digit selects the n of logical block to select a function, obtains polynomial of described scale-of-two and allows the most significant digit that has.
Above-mentioned method wherein, by the setting to parameters C and parameter K, realizes setting and the change of the polynomial every coefficient of scale-of-two with the most significant digit that is allowed.
In order to realize purpose of the present invention, the present invention also provides a kind of hardware system of realizing the scale-of-two multinomial operation, wherein, comprising: adopt n linear feedback shift register of serial data input, each register is represented the polynomial x of scale-of-two respectively by input/output sequence
1To x
nIn one; Be arranged on the combinatorial logic unit of realization selection function of the input port of each register, be used for being provided with the coefficient of polynomial of the pairing scale-of-two of previous register of this register.
Above-mentioned hardware system wherein, comprises that also most significant digit selects logical block, is used for being provided with polynomial of described scale-of-two and allows the most significant digit that has; The value of each register is input to described most significant digit and selects logical block, and described most significant digit selects the output of logical block to be connected to the XOR logical block of the input port of described combinatorial logic unit.
Above-mentioned hardware system wherein, is represented x
1The combinatorial logic unit of input port of shift register, be used for controlling the polynomial x of scale-of-two
0Coefficient.
Above-mentioned hardware system, wherein, n binary number of the corresponding respectively input of the combinatorial logic unit of the input port of a described n register is used for selecting then x
0To x
N-1Coefficient; Described most significant digit is selected logical block input parameter K, is used for realizing that the n of described most significant digit selection logical block selects a function; Described n binary number composition parameter C.
Technique effect of the present invention is:
The present invention proposes a hardware and realizes design, can be on hardware the linear feedback shift logic of flexible configuration shift register, can finish the scale-of-two multinomial operation of different schemes, comprise the scheme of different length, thus the dirigibility that has greatly improved hard-wired efficient and system.
Description of drawings
Fig. 1 is the flow chart of steps of the inventive method;
Fig. 2 is that the hardware of the inventive method is realized synoptic diagram;
Fig. 3 a, 3b are the inventive method equivalent hardware synoptic diagram under predetermined embodiment parameter.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, describe the present invention below in conjunction with the accompanying drawings and the specific embodiments.
Fig. 1 is the flow chart of steps of the inventive method, and as figure, the inventive method comprises:
In the methods of the invention, parameters C and parameter K are set also,, realize of the setting and the change of the polynomial every coefficient of scale-of-two with the most significant digit that is allowed by setting to parameters C and parameter K.Described parameters C comprises the combinatorial logic unit of the input port of the described n of the corresponding respectively input of a n binary number register, is used for selecting then x
0To x
N-1Coefficient, described parameter K is imported described most significant digit and is selected logical block, realizes that described most significant digit selects the n of logical block to select a function, obtains polynomial of described scale-of-two and allows the most significant digit that has.
Fig. 2 is that the hardware of the inventive method is realized synoptic diagram, and as figure, n the shift register 201 that comprises the input of employing serial data in the shown logical circuit is to 20n; Its linear feedback logic is made up of two parts: the combinational logic of the realization selection function between the adjunct register (an XOR logic that comprises this combinational logic input port), select logic 210 (feedback that realizes selection function is selected logic, and it is input as each register value) with most significant digit.This two-part selection signal is respectively by parameters C and parameter K control.
With CRC is example, when this cover counting circuit is used for CRC calculating, suppose that design maximum CRC figure place is made as n, parameters C [n-1:0] is the n bit, every coefficient of the corresponding CRC generator polynomial g of numerical value (x), each of parameters C is controlled the selection signal of a combinatorial logic unit respectively.Parameter K is used for controlling n and selects 1 logic, select needed register output as the most significant digit feedback, thereby realization is no more than the CRC algorithm of any digit of n position.
Use sort circuit, can select to realize multiple scale-of-two polynomial computation scheme, comprise the configuration of different coefficients and different length according to pre-designed parameter (parameters C and parameter K).In needs support that the system of multiple CRC realizes, the setting of every kind of corresponding one group of parameters C of CRC scheme and K.
Fig. 3 a, 3b are by the inventive method equivalent hardware synoptic diagram under predetermined embodiment parameter, as figure, if calculate scale-of-two polynomial expression g (x)=x
3+ x+1 can select most significant digit earlier, because the item of the most significant digit of g (x) is x
3So, select parameter K=3, equivalent electrical circuit just shown in Fig. 3 a, has just been determined polynomial length like this.Determine every coefficient then, by g (x)=x
3+ x+1 as can be known, C[0]=1, C[1]=1, C[2]=0, therefore, shown in Fig. 3 b, like this,, just realized that any polynomial hardware realizes by setting to parameters C and K by the selected equivalent electrical circuit of this parameter.
As from the foregoing, compared with former technology, the invention has the advantages that: can in hardware circuit implementation, select the linear feedback logic of configuration, can support the scheme of multiple scale-of-two multinomial operation, the scheme that comprises different length, thereby the dirigibility that has greatly improved hard-wired efficient and system.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (9)
1. a hardware configuration method of realizing the scale-of-two multinomial operation is characterized in that, comprises the steps:
Step 1, for n the linear feedback shift register that adopts the serial data input, each register is represented the polynomial x of scale-of-two respectively by input/output sequence
1To x
nIn one;
Step 2 is provided with the combinatorial logic unit that realizes selection function by the input port at each register, and the coefficient of the polynomial item of the pairing scale-of-two of previous register of this register is set.
2. method according to claim 1 is characterized in that, also comprises:
Step 3, the value of each register is input to most significant digit selection logical block, and select the output of logical block to be connected to the XOR logical block of the input port of described combinatorial logic unit the described most significant digit, select logical block that polynomial of described scale-of-two is set by described most significant digit and allow the most significant digit that has.
3. method according to claim 1 and 2 is characterized in that, in described step 2, represents x
1The combinatorial logic unit of input port of shift register, be used for controlling the polynomial x of scale-of-two
0Coefficient.
4. method according to claim 3 is characterized in that, parameters C and parameter K are set, and described parameters C comprises the combinatorial logic unit of the input port of the described n of the corresponding respectively input of a n binary number register, is used for selecting then x
0To x
N-1Coefficient, described parameter K is imported described most significant digit and is selected logical block, realizes that described most significant digit selects the n of logical block to select a function, obtains polynomial of described scale-of-two and allows the most significant digit that has.
5. method according to claim 4 is characterized in that, by the setting to parameters C and parameter K, realizes setting and the change of the polynomial every coefficient of scale-of-two with the most significant digit that is allowed.
6. a hardware system of realizing the scale-of-two multinomial operation is characterized in that, comprising:
Adopt n linear feedback shift register of serial data input, each register is represented the polynomial x of scale-of-two respectively by input/output sequence
1To x
nIn one;
Be arranged on the combinatorial logic unit of realization selection function of the input port of each register, be used for being provided with the coefficient of polynomial of the pairing scale-of-two of previous register of this register.
7. hardware system according to claim 6 is characterized in that, comprises that also most significant digit selects logical block, is used for being provided with polynomial of described scale-of-two and allows the most significant digit that has; The value of each register is input to described most significant digit and selects logical block, and described most significant digit selects the output of logical block to be connected to the XOR logical block of the input port of described combinatorial logic unit.
8. according to claim 6 or 7 described hardware systems, it is characterized in that, represent x
1The combinatorial logic unit of input port of shift register, be used for controlling the polynomial x of scale-of-two
0Coefficient.
9. hardware system according to claim 8 is characterized in that, n binary number of the corresponding respectively input of the combinatorial logic unit of the input port of a described n register is used for selecting then x
0To x
N-1Coefficient; Described most significant digit is selected logical block input parameter K, is used for realizing that the n of described most significant digit selection logical block selects a function; Described n binary number composition parameter C.
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| CN100517214C CN100517214C (en) | 2009-07-22 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101354640B (en) * | 2008-09-02 | 2011-11-16 | 北京九方中实电子科技有限责任公司 | Operator for performing multinomial operation to data sequence in order mobile window |
| CN111400232A (en) * | 2020-04-10 | 2020-07-10 | 芯启源电子科技有限公司 | Scramble and desramble hardware implementation method based on data bit width expansion |
| US20210105124A1 (en) * | 2017-06-29 | 2021-04-08 | Qualcomm Incorporated | Providing protection for information delivered in demodulation reference signals (dmrs) |
| CN114443347A (en) * | 2021-12-23 | 2022-05-06 | 湖南毂梁微电子有限公司 | Configurable CRC code calculation method |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3607116B2 (en) * | 1999-04-28 | 2005-01-05 | 松下電器産業株式会社 | Arithmetic processing unit |
| AU5871201A (en) * | 2000-05-15 | 2001-11-26 | M-Systems Flash Disk Pioneers Ltd. | Extending the range of computational fields of integers |
| DE10107376A1 (en) * | 2001-02-16 | 2002-08-29 | Infineon Technologies Ag | Method and device for modular multiplication and arithmetic unit for modular multiplication |
| US7711763B2 (en) * | 2001-02-21 | 2010-05-04 | Mips Technologies, Inc. | Microprocessor instructions for performing polynomial arithmetic operations |
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2007
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101354640B (en) * | 2008-09-02 | 2011-11-16 | 北京九方中实电子科技有限责任公司 | Operator for performing multinomial operation to data sequence in order mobile window |
| US20210105124A1 (en) * | 2017-06-29 | 2021-04-08 | Qualcomm Incorporated | Providing protection for information delivered in demodulation reference signals (dmrs) |
| US11671222B2 (en) * | 2017-06-29 | 2023-06-06 | Qualcomm Incorporated | Providing protection for information delivered in demodulation reference signals (DMRS) |
| CN111400232A (en) * | 2020-04-10 | 2020-07-10 | 芯启源电子科技有限公司 | Scramble and desramble hardware implementation method based on data bit width expansion |
| CN114443347A (en) * | 2021-12-23 | 2022-05-06 | 湖南毂梁微电子有限公司 | Configurable CRC code calculation method |
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| CN100517214C (en) | 2009-07-22 |
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