CN114442438B - Core particle arrangement optimizing algorithm for variable grids - Google Patents
Core particle arrangement optimizing algorithm for variable grids Download PDFInfo
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Abstract
The invention provides a core particle arrangement optimizing algorithm of a variable grid, which comprises the following steps: s1, establishing a rectangular coordinate system, wherein a X, Y axis of the rectangular coordinate system is tangent to the edge of the wafer; s2: the coordinate origin of the rectangular coordinate system is used as a starting point, an optimal combination of the offset of the Dies in the X direction and the Y direction of the Dies is found by adopting a dichotomy method, so that the number of the Dies divided on the wafer is the largest, and the Dies are arranged in an array; s3, setting the offset of the X direction and the Y direction of a single exposure unit Shot according to the Die arrangement obtained in the S2, so that the number of shots required for covering the wafer is minimum, and obtaining Shot arrangement; the variable-grid core particle arrangement optimizing algorithm provided by the invention has the advantages that the calculated amount is far smaller than that of the existing fixed-grid optimizing algorithm, the calculating time is greatly shortened, the result judgment is added, and the accuracy of the result is ensured. The method effectively overcomes the defects of large optimizing calculation amount, long time consumption, inaccurate result and the like in the prior art, and has higher practical value in the field of semiconductor manufacturing.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a core particle arrangement optimizing algorithm for a variable grid.
Background
In semiconductor manufacturing, it is generally involved in designing a Die array for the entire wafer, and the wafer is expensive to manufacture, so we need to divide as many Die as possible on a wafer of a fixed size. In the process of dividing the wafer, a photolithography process is necessarily used, and the complete photolithography process comprises the procedures of cleaning, gluing, soft baking, exposure, development, etching, detection and the like, wherein the exposure is a key step for determining the number of final Die. The exposure process is to transfer the pattern on the mask plate to the wafer, so that the placement of the mask plate directly determines the final Die array arrangement, and the placement position of the mask plate is obtained through the prior Die array arrangement design. Since the wafer is generally circular and Die is generally regular rectangular, this results in incomplete Die at the wafer edge must occur during exposure. Therefore, simulation calculation is required before exposure, and the maximum number of complete Die on the wafer is ensured by continuously changing the relative positions of Die and wafer, so that the optimal Die arrangement is obtained. In practical array arrangement design, wafers often have unusable areas such as defects, zone bits, laser etching codes and the like, and the factors need to be considered in the array arrangement design. In addition, since the size of the area of one exposure of the exposure system is limited, it is necessary to divide one wafer into a plurality of exposure units (shots) for exposure imaging at the time of exposure, and it is also a goal of technicians to reduce the number of shots as much as possible. Finally, the maximum Die and the minimum Shot are obtained through the design and arrangement of the Die.
The conventional array arrangement algorithm generally adopts a fixed grid optimizing algorithm, and the offset is changed substantially by linearly changing the offset, so that the relative position relation between the Die and the wafer is changed, the number of the Die under various position relations is calculated, the corresponding position relation when the maximum Die is selected from the number of the Die, the problem of searching the optimal Die arrangement is converted into the problem of searching the optimal offset, and the method comprises the following specific steps of: as shown in fig. 1, a rectangular coordinate system is established, the X, Y axis of the rectangular coordinate system is tangent to the edge of the wafer, the length and width of each Die are determined to be X 0、Y0, X 0、Y0 is divided into a plurality of parts, and the length of each part is X 0/100、Y0/100 assuming that the parts are divided into 100 parts. The offset amounts X and Y offset are set, the offset amounts X and Y offset are set to X 0/100、2X0/100、……、X0 in order, and the offset amount Y offset is set to Y 0/100、2Y0/100、……、Y0 in order, so that the total set of the X and Y offsets is 100×100=10000. And (3) through traversing the combined setting of the 10000X-offset and Y-offset, calculating the number of complete Die which can be arranged on the wafer under 10000 conditions, and selecting the X-offset and Y-offset corresponding to the maximum number of complete Die, thereby determining the placement position of the mask plate and obtaining the optimal Die array arrangement.
The fixed grid optimizing algorithm has some problems, and the advantages and disadvantages of the results are directly determined by the number of equal parts of X 0、Y0, because the more the number of equal parts of X 0、Y0 is, the more the arrangement and combination are, the more the traversing is, the more the probability of the obtained optimal Die array arrangement is, but the more the number of equal parts is, the double increase of the calculated amount is required, and the time consumption is increased. Taking an 8-inch wafer as an example, when Die with the array arrangement of 2.06mm and 1.64mm is arranged, dividing the length and width X 0、Y0 of the Die into 160 parts equally, obtaining the optimal Die array arrangement at the moment takes 90 minutes, calculating 25600 times, and has large calculated amount and longer use time. In addition, this method does not ensure that the result is optimal, and in theory, the result is optimal when the number of X 0、Y0 equal parts is unlimited, but in view of the time-consuming effect, it is not ensured that the result is optimal when only Die length and width X 0、Y0 is equal to 100 parts. In addition, the array arrangement result obtained by the method is more doubtful due to the influence of unavailable areas such as defects, zone bits, laser etching codes and the like.
Therefore, a new Die array arrangement method needs to be proposed to solve the above problems.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention aims to provide a variable grid core arrangement optimizing algorithm, which is used for solving the problems of large calculation amount, inaccurate result, long time consumption and the like of the existing fixed grid optimizing algorithm. The method for calculating Die array arrangement on the wafer comprises the following steps:
S1, establishing a rectangular coordinate system, wherein the X, Y axis of the rectangular coordinate system is tangent to the edge of the wafer.
S2: and (3) taking the origin of coordinates as a starting point, and finding the optimal combination of the X-direction offset (X-offset) and the Y-direction offset (Y-offset) of the Die arrangement by adopting a dichotomy method, so that the number of complete Die (Die Count) divided on the wafer is the largest, and the Die array arrangement is obtained.
S3, setting an X-direction offset (XRet) and a Y-direction offset (YRet) of a single exposure unit Shot according to the Die array arrangement obtained in the S2, so that the number of shots required for covering the wafer is minimum, and obtaining the Shot arrangement.
Specifically, the step S2 specifically includes the following steps:
S2-1: the length and width of a single Die are determined to be X 0、Y0 respectively, and X 0、Y0 is divided into a plurality of parts of p and q respectively, wherein p and q are positive integers.
S2-2: setting the offset X-offset and Y-offset as X 0/p,2X0/p,……,X0 in sequence, setting the offset Y-offset as Y 0/q,2Y0/q,……,Y0 in sequence, traversing the combination setting of p.q X-offset and Y-offset, calculating the Die Count which can be arranged on the wafer under the p.q conditions, selecting the combination setting of all the X-offset and Y-offset corresponding to the Die Count being greater than a certain threshold value, setting the combination of the selected X-offset and Y-offset as I-level suspected points, and setting the threshold value as I-level point threshold value.
S2-3: and (3) on the basis of the I-level suspected points selected in the step (S2-2), locating II-level points around each I-level suspected point in a shape of a Chinese character 'tian', wherein the II-level points are mutually connected in the X and Y directions, and the length and the width of the formed grid are X 0/2p、Y0/2 q respectively. And calculating a Die Count corresponding to the class II point, selecting a combination setting of all corresponding X-offset and Y-offset when the Die Count is larger than a certain threshold value, setting the combination of the selected X-offset and Y-offset as a class II suspected point, and setting the threshold value as a class II point threshold value.
S2-4: and sequentially finding out a III-level suspected point, an IV-level suspected point, a V-level suspected point, … … and a k-level suspected point through an iteration method. And after the obtained k-level suspected points are connected with each other in the X and Y directions, the length and width of the formed grid are X 0/2(k-1)p、Y0/2(k-1) q respectively. And taking the combination of the X offset and the Y offset corresponding to the k-level suspected points with the maximum Die Count as the final optimal solution, wherein k is a positive integer.
Specifically, the step S3 specifically includes the following steps:
The number of Die contained in a single Shot is determined to be m x n, and the step length of the Shot for offset is the length and width of the single Die. Then there are m cases of shift of Shot along the X axis, there are n cases of Shot along the Y axis, and all cases of two directions are combined together in a permutation and combination to have m×n cases. Calculating the required Shot number of the covered wafer under the condition of m x n, wherein the corresponding offset is the optimal Shot arrangement when the Shot number is minimum, and m and n are positive integers.
Optionally, the step S2 further includes the steps of:
S2-5, finding k-level suspected points through judging conditions in the step S2-4, and terminating the algorithm after the judging conditions are met, wherein the obtained k-level suspected points are the true optimal points, the judging conditions of the terminating algorithm are that the maximum Die Count obtained by the calculation of the new level is the same as that of the previous level, and meanwhile, the class of the suspected point corresponding to the maximum Die Count is the same as that of the calculation of the previous level. Specifically, the method for determining the class of the suspected points comprises the following steps:
After the suspicious points of each level are found in the step S2, cluster analysis is performed on the suspicious points of each level, the space distance between the suspicious points is calculated, a threshold is set, the suspicious points with the space distance smaller than the threshold and the same number of corresponding Die are classified into a class, and the class threshold is determined according to the number of the suspicious points.
Optionally, before executing S2, the method includes the steps of: the unusable areas are accurately positioned on the wafer, the areas are classified as invalid areas when array arrangement calculation is carried out, and the invalid areas are excluded when Die Count is calculated.
Optionally, the level I point threshold setting rule in step S2-2 is: and ordering the corresponding Die Count in descending order under the p-q cases, and setting a threshold value so that the points ordered at the first 3/4 enter the range of I-level suspected points.
Optionally, in step S2-4, the k-level point threshold setting rule is: and ordering the number of Die corresponding to the k-level points in a descending order, and setting a threshold value to enable the number of Die to be ordered within the range that the point with the first name of i enters the k-level suspected point. Where i is a positive integer, the value of i may be set to 5.
Optionally, in step S2-2, the length and width X 0、Y0 of Die are all equally divided into 10 parts, i.e. p and q are both 10.
Specifically, by using the above-mentioned optimization algorithm for core particle arrangement with variable grids, core particles with the length and width X 0、Y0 of 2.06mm and 1.64mm respectively are arranged on a wafer with the diameter of 8 inches, and when the optimal Die arrangement is obtained, the algorithm calculates 1016 times in total, and takes 3 minutes and 30 seconds, so that the maximum Die Count is 8515.
In summary, the Die arrangement optimizing algorithm of the variable grid provided by the invention has the following beneficial effects: when the optimal offset combination is found, the suspected point is found first, then the area near the suspected point is analyzed, and the optimal point is found through iteration. The calculated amount of the method is far smaller than that of a fixed grid optimizing algorithm, so that the calculation time is greatly shortened, and meanwhile, the result judgment is added, so that the accuracy of the result is ensured. Therefore, the invention effectively overcomes the defects of large optimizing calculation amount, long time consumption, inaccurate result and the like in the prior art, and has higher practical value in the field of semiconductor manufacturing.
Drawings
The features and advantages of the present invention will be more clearly understood by reference to the accompanying drawings, which are illustrative and should not be construed as limiting the invention in any way, in which:
FIG. 1 is a schematic diagram showing the rule of setting the offset in Die arrangement
FIG. 2 is a schematic diagram showing the results of the first level points located in the first embodiment
FIG. 3 is a schematic diagram of a grid formed by two-level points connected to each other
FIG. 4 is a schematic view showing a secondary suspected point selected from the secondary points shown in FIG. three
FIG. 5 is a schematic diagram showing the best results obtained in the first embodiment
FIG. 6 is a schematic diagram showing classification in dimer analysis according to an embodiment
FIG. 7 is a schematic diagram showing the best point and its category according to the second embodiment
FIG. 8 shows the coordinates of the optimal points obtained for the second embodiment
FIG. 9 is a schematic view of a wafer processing with non-usable areas in accordance with a third embodiment
Fig. 10 is a schematic diagram showing an offset setting rule in the Shot arrangement in the fourth embodiment
FIG. 11 shows a Shot count result obtained by setting different offsets in the Shot arrangement in the fourth embodiment
FIG. 12 shows a schematic diagram of a minimum Shot arrangement obtained in example four
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Example 1
The embodiment provides a Die arrangement optimizing algorithm of a variable grid, which comprises the following steps:
S1, establishing a rectangular coordinate system, wherein the X, Y axis of the rectangular coordinate system is tangent to the edge of the wafer.
S2: and (3) taking the origin of coordinates as a starting point, and finding the optimal combination of the offset X offset and the Y offset by adopting a dichotomy method to maximize the Die Count divided on the wafer, thereby obtaining the Die array arrangement.
The step S2 specifically includes the following steps:
S2-1, equally dividing the length and width X 0、Y0 of Die into 10 parts, wherein the length and width of each part are respectively X 0/10、Y0/10;
S2-2, sequentially setting X offset of the X direction of Die arrangement as X 0/10,2X0/10,……,X0; the Y-direction offset amount Y offset of Die arrangement is set to Y 0/10,2Y0/10,……,Y 0 in order. A total of 10×10=100 combinations of offset X-offset and Y-offset are obtained, die counts obtained under these 100 conditions are sequentially calculated, the obtained Die counts are sorted in descending order, the points with the number of Die counts being more than 75% above are selected, i.e. the combination of the preferred X-offset and Y-offset values is selected, as shown in fig. 2, the abscissa represents the X-offset value, the ordinate represents the Y-offset value, the solid points marked in the figure represent the preferred combination selected, and the abscissa of these points also represents the corresponding X-offset and Y-offset values. Meanwhile, the points obtained in the step are classified as I-level suspected points, and the I-level suspected points are named as P1, P2, P3, P4 and … … for descriptive convenience;
S2-3, on the basis of the I-level suspected points selected in the S2-2, eight adjacent I-level points P1, P2, P3, P4 and … … are positioned according to the rule of the shape of the Chinese character 'tian', the II-level points are named as P11, … …, P18, P21, … …, P28, P31, … …, P38 and … … for convenience of description, as shown in figure 3, after the II-level points are mutually connected in the X and Y directions, the formed grid length and width are X 0/20、Y0/20 respectively, which is equivalent to dividing the grid length and width into two parts again on the basis that each part of original length and width are X 0/10、Y0/10 respectively, and at the moment, the length and width of each part are X 0/20、Y0/20 respectively. And (3) calculating the II-level points obtained in the step to obtain the Die Count corresponding to each point, sorting the obtained Die Count in a descending order, selecting the five points with the top Die Count number ranking, namely selecting the combination of the better X offset and Y offset values in the II-level points, wherein the marked points in the figure represent the selected preferred combination, and classifying the selected points as II-level suspected points as the selected preferred combination.
On the basis of the II-level suspected points, eight adjacent points of each II-level suspected point are positioned in a shape rule of a 'field' shape by adopting the same method, and III-level points are obtained, wherein after the III-level points are connected with each other in the X and Y directions, the formed grid has the length and width of X 0/40、Y0/40 respectively, which is equivalent to dividing the grid into two parts again on the basis of each part of length and width of X 0/20、Y0/20 respectively. And calculating newly added points to obtain Die Count corresponding to each class III point, sorting the obtained Die Count in a descending order, selecting the five points with the top Die Count number ranking, and classifying the selected points as class III suspected points.
And S2-4, sequentially finding IV-level suspected points and V-level suspected points according to the steps, and taking the combination of X offset and Y offset corresponding to the maximum Die Count in the V-level suspected points as the final optimal solution.
Example two
The embodiment also provides a method for calculating Die array arrangement on a wafer, which is the same as that of the first embodiment, and the differences are that:
After the suspected points of each level are found in the first embodiment, the suspected points of each level are respectively subjected to cluster analysis, as shown in fig. 6, the suspected points are classified, and each closed curve in the figure represents a class. The method for classifying the suspected points by adopting the cluster analysis comprises the following steps: calculating the space distance between each suspected point, setting a class threshold, and classifying the suspected points with the space distance smaller than the threshold and the same corresponding Die Count value into a class. The class threshold is determined according to the number of suspected points, for example, the class I suspected points are far away from each other, and the class threshold is larger at this time; for the V-level suspected points, the distance between the V-level suspected points is relatively close, and the class threshold is relatively small. In this embodiment, the threshold value in classification is 2 times the length and width of the grid corresponding to the suspected point level, for example, when classifying the suspected point of level I, the threshold value in classification is X 0/5、Y0/5; the length-width threshold value when classifying the III-level suspected points is X 0/20、Y0/20.
In order to obtain a more accurate optimal solution, after calculating the V-level suspected points in step S2-4, the algorithm is not stopped, and the algorithm continues to calculate downwards to obtain VI-level suspected points, VII-level suspected points and … …, but the algorithm cannot calculate downwards all the time, and a judgment termination algorithm needs to be added. The condition of the termination algorithm is that the maximum Die Count obtained by the new step is the same as that of the previous step, and the class of the suspected point corresponding to the maximum Die Count is the same as that of the previous step. The judgment has the significance that the Die Count at the moment is determined to be the maximum, and the suspected point corresponding to the Die Count is in the range of the class determined in the last step, so that the suspected point is ensured not to appear outside the range of the class, otherwise, the analysis and calculation of the suspected point outside the range of the class are continued without stopping.
As shown in fig. 7, for the optimal points obtained by the calculation and judgment of the algorithm, die with a diameter of 2.06mm by 1.64mm are arranged on a wafer with a diameter of 8 inches, and 5 optimal points are divided into three types. Each small circle represents a class. As shown in fig. 8, the coordinates of the 5 points are specific information, and the final Die Count of the 5 points is 8515, and cluster represents the class to which the 5 points belong. The optimal Die arrangement is obtained by using the variable grid algorithm, and 1016 times are calculated, and the time is 3 times and 30 seconds. Compared with a fixed grid optimizing algorithm, the method has the advantages that the calculated amount is greatly reduced, and the time consumption is shortened. Meanwhile, the obtained optimal point is a true optimal point through calculation and judgment of the algorithm.
Example III
The embodiment provides a method for calculating Die array arrangement on a wafer, which is mainly used for Die array arrangement on a wafer with unusable areas such as defects, marker bits, laser etching codes and the like. The same points as those of the second embodiment are not described in detail, and the difference is that:
Before S2 is executed, the unusable areas of the wafer are further divided, as shown in fig. 9, the unusable areas are accurately positioned on the wafer, when the array arrangement calculation is performed, the unusable areas are classified as invalid areas, and when the Die Count is calculated, the invalid areas are excluded, so that the obtained optimal point is the true optimal point, and is the optimal point according with the practical situation.
Example IV
The embodiment provides a method for calculating Shot arrangement on a wafer, which is mainly used for carrying out arrangement design on shots after array arrangement of Die is completed, so that the number of shots is minimum. The method is similar to the method for determining the optimal Die arrangement, and the method for gradually changing the offset is also adopted, so that the number of shots under various offsets is compared, and the optimal Shot arrangement is obtained. On the basis of the third embodiment, the embodiment further includes the following steps:
S3, setting an X-direction offset (XRet) and a Y-direction offset (YRet) of a single exposure unit Shot according to the Die array arrangement obtained in the S2, so that the number of the shots covering the wafer is minimum, and obtaining the Shot arrangement
The step S3 specifically comprises the following steps:
as shown in fig. 10, after the Die array arrangement is determined, the default Shot is shown by a dotted rectangle in the figure, that is, the right angle of the Shot coincides with the right angle of the outermost peripheral Die. Assuming that m×n Die are included in the Shot, the step length of Shot offset is the length and width of a single Die, then there are m cases of Shot offset along the X axis, n cases of Shot offset along the Y axis, and all cases of two directions are arranged and combined together to share m×n cases. As shown in fig. 10, the solid rectangular frame is the shifted Shot position, the shift amounts of the Shot in the X and Y directions are defined as XRet and YRet, respectively, and at this time, the Shot is shifted by 1 Die length in the X and Y directions with respect to the default position, i.e., XRet and YRet are both 1.
As shown in fig. 11, in this embodiment, when XRet is fixed to 1, YRet is sequentially increased from 1 to 20, and the corresponding number of shots (Shot Count) has different results. The number of shots is at least 44 and at most 50. As shown in fig. 12, which is a schematic diagram of the arrangement corresponding to the number of shots 44, it can be seen that the number of shots covering all Die on the wafer is 44.
In summary, the variable-grid core particle arrangement optimizing algorithm provided by the invention has the following beneficial effects: when the optimal offset combination is found, the suspected point is found first, then the area near the suspected point is analyzed, and the optimal point is found through iteration. The calculated amount of the method is far smaller than that of a fixed grid optimizing algorithm, so that the calculation time is greatly shortened, and meanwhile, the result judgment is added, so that the accuracy of the result is ensured. Therefore, the invention effectively overcomes the defects of large optimizing calculation amount, long time consumption, inaccurate result and the like in the prior art, and has higher practical value in the field of semiconductor manufacturing.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (9)
1. The core particle arrangement optimizing algorithm for the variable grid is characterized by comprising the following steps of:
S1, establishing a rectangular coordinate system, wherein a X, Y axis of the rectangular coordinate system is tangent to the edge of the wafer;
S2: taking the origin of coordinates of the rectangular coordinate system as a starting point, and finding out the optimal combination of the X-direction offset and the Y-direction offset of the Die arrangement by adopting a dichotomy method, so that the number of Die divided on the wafer is the largest, and the Die arrangement is obtained; comprising the following steps:
S2-1: determining the length and width of each Die to be X 0、Y0, and equally dividing X 0、Y0 into a plurality of parts of p and q;
S2-2: sequentially setting the X-direction offset of the Die arrangement as X 0/p,2X0/p,……,X0, sequentially setting the Y-direction offset of the Die arrangement as Y 0/q,2Y0/q,……,Y0, traversing the p X q combinations of the X-direction offset and the Y-direction offset, calculating the number of the Die which can be arranged on the wafer under the p X q conditions, selecting the combination of the X-direction offset and the Y-direction offset corresponding to the Die arrangement when the number of the Die is larger than a certain threshold value, setting the selected combination as an I-level suspected point, and setting the threshold value of the step as an I-level point threshold value, wherein p and q are positive integers;
S2-3: on the basis of the I-level suspected points selected in the step S2-2, locating II-level points around each I-level suspected point in a shape of a Chinese character 'tian', wherein the II-level points are mutually connected in the X and Y directions, the length and the width of a formed grid are X 0/2p、Y0/2 q respectively, the number of Dies corresponding to the II-level points is calculated, when the number of Dies is greater than a certain threshold value, the combination of the X-direction offset and the Y-direction offset corresponding to the Dies is selected, the selected combination is set as the II-level suspected point, and the threshold value in the step is set as the II-level point threshold value;
S2-4: and sequentially finding a III-level suspected point, an IV-level suspected point, a V-level suspected point, … … and a k-level suspected point through an iteration method, analyzing the area near the suspected point, and finding the optimal point through iteration.
2. The variable grid core arrangement optimization algorithm of claim 1, further comprising the steps of:
S3, setting the X-direction offset and the Y-direction offset of a single exposure unit Shot according to the Die arrangement obtained in the S2, so that the number of shots required for covering the wafer is minimum, and obtaining the Shot arrangement.
3. The variable grid core arrangement optimizing algorithm according to claim 1, wherein the step S2-4 further comprises: sequentially finding a III-level suspected point, an IV-level suspected point, a V-level suspected point, … … and a k-level suspected point through an iteration method, connecting the obtained k-level suspected points in the X and Y directions, forming grids with the length and the width of X 0/2(k-1)p、Y0/2(k-1) q respectively, and taking the combination of the X-direction offset and the Y-direction offset of the k-level suspected points with the largest number of Die corresponding to Die arrangement as a final optimal solution, wherein k is a positive integer.
4. The variable grid core arrangement optimizing algorithm according to claim 2, wherein the step S3 specifically comprises the steps of:
Determining that the number of Die contained in a single Shot is m X n, and the step length of Shot offset is the length and width of the single Die, wherein m cases exist in the X-direction offset of the Shot, n cases exist in the Y-direction offset of the Shot, and all cases of the X-direction offset and the Y-direction offset of the Shot are arranged and combined together to share m X n cases; calculating the required Shot number of the covered wafer under the condition of m x n, wherein the corresponding offset is the optimal Shot arrangement when the Shot number is minimum, and m and n are positive integers.
5. The variable grid core arrangement optimizing algorithm according to claim 3, wherein the step S2 further comprises the steps of:
s2-5, finding k-level suspected points through judging conditions in the step S2-4, and terminating the algorithm after the judging conditions are met, wherein the k-level suspected points are true optimal points, the judging conditions of the terminating algorithm are that the maximum number of Die calculated at the new stage is the same as that of the previous stage, and the class of suspected points corresponding to the maximum number of Die is the same as that of the previous stage.
6. The variable grid core particle placement optimization algorithm according to claim 5, wherein the method for determining the class of the suspected points is as follows:
After the suspicious points of each level are found in the step S2, cluster analysis is performed on the suspicious points of each level, the space distance between the suspicious points is calculated, a threshold is set, the suspicious points with the space distance smaller than the threshold and the same number of corresponding Die are classified into a class, and the class threshold is determined according to the number of the suspicious points.
7. The variable grid core particle placement optimization algorithm as set forth in claim 1, wherein the dividing the unusable area with defects, flags, laser etching codes in the wafer prior to executing S2-1 comprises the following specific steps: the unusable areas are accurately positioned on the wafer, the areas are classified as invalid areas when the Die arrangement calculation is carried out, and the invalid areas are excluded when the Die number is calculated.
8. The variable grid core particle placement optimization algorithm as set forth in claim 3, wherein the k-level point threshold setting rule is: and ordering the number of Die corresponding to the k-level points in a descending order, and setting a threshold value to enable the points with the number of Die ordered in the previous i-number to enter a range of k-level suspected points, wherein i is a positive integer.
9. The variable grid core arrangement optimization algorithm of claim 8, wherein the value of i is 5.
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