CN110780533A - Novel OPC model correction method - Google Patents
Novel OPC model correction method Download PDFInfo
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- CN110780533A CN110780533A CN201911084357.1A CN201911084357A CN110780533A CN 110780533 A CN110780533 A CN 110780533A CN 201911084357 A CN201911084357 A CN 201911084357A CN 110780533 A CN110780533 A CN 110780533A
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000012937 correction Methods 0.000 title claims abstract description 28
- 238000012360 testing method Methods 0.000 claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 claims abstract description 22
- 238000004458 analytical method Methods 0.000 claims abstract description 16
- 238000013461 design Methods 0.000 claims abstract description 9
- 238000010835 comparative analysis Methods 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 4
- 239000007787 solid Substances 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 238000005259 measurement Methods 0.000 description 6
- 238000001459 lithography Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000004364 calculation method Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000011532 electronic conductor Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003909 pattern recognition Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
- G03F7/70441—Optical proximity correction [OPC]
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Abstract
The invention provides a novel OPC model correction method, which comprises the following steps: designing an OPC test pattern; manufacturing an OPC mask plate aiming at the OPC test pattern; establishing an OPC model; carrying out OPC wafer production; identifying and extracting a pattern structure on the produced wafer; comparing and analyzing the graph structure extracted from the wafer with the designed test graph to obtain the part of the graph structure on the wafer which is not matched or wrong relative to the test graph; correcting the OPC model aiming at the part which is obtained by the graph comparison analysis and is not matched with the test graph; and repeating iteration until the graph structure on the wafer is completely matched with the test graph or the design precision requirement is met in the graph comparison analysis, and finishing the OPC model correction. The invention avoids the potential risk brought by replacing the photoresist, more accurately acquires and feeds back the information of the complex graph, and greatly reduces the iteration times among the model design-correction-model determination processes.
Description
Technical Field
The invention relates to the field of semiconductor design and manufacture, in particular to a novel OPC model correction method.
Background
The key to model-based optical proximity correction is to build an accurate photolithography process model. The reliable OPC model can completely describe the whole photoetching process including an optical system, a mask, photoresist and an etching process. Although the strict lithography model has high precision, the requirement on computing power is high, and the traditional computing power cannot complete the lithography process simulation of a chip level within the time required by the market. OPC uses a semi-empirical simplified lithography model that replaces the complex processes in the original model with some simplified empirical formulas. The empirical formula contains many parameters, which can be calibrated by experimental data fitting, and finally the calculation structure of the simplified lithography model is matched with the experimental result. The calibration period of the OPC model can be summarized as the following steps: experiments were Designed (DOE), performed, data collected, model calibrated and verified. The current OPC model is corrected by collecting the critical dimension of a chip on a mask or a wafer by using CD-SEM test, feeding back related measurement data to the OPC model and performing comprehensive operation by combining modeling information. However, due to the fact that the measured data volume is large, time consumption is high, a graph under the Non-Manhattans design rule is not easy to describe, and it is difficult to represent and describe an actual graph through measured data of a plurality of points, and in the traditional process, a photoresist shrinks under bombardment of electron beams during measurement, and the measured data has deviation from an actual value.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a novel OPC model correction method, aiming at reducing the iteration times of OPC model correction, accelerating the wafer production process conforming to the design layout and reducing the production cost.
In order to achieve the purpose, the invention adopts the following technical scheme:
a novel OPC model correction method comprises the following steps:
A. designing an OPC test pattern;
B. manufacturing an OPC mask;
C. establishing an OPC model;
D. carrying out OPC wafer production to manufacture a physical structure corresponding to the test pattern on the wafer;
E. identifying and extracting the graph structure on the wafer produced in the step D;
F. comparing and analyzing the graph structure extracted from the wafer in the step E with the test graph designed in the step A to obtain a part of the graph structure on the wafer, which is not matched or wrong relative to the test graph;
G. correcting the OPC model aiming at the part which is obtained by the graph comparison analysis in the step F and is not matched with the test graph;
H. repeating the step D to the step G until the graph structure on the wafer is completely matched with the test graph or the design precision requirement is met in the graph comparison analysis, and finishing the OPC model correction;
in step E, the graph contrast analysis comprises any one of the following modes:
(1) inputting part or all of the OPC test patterns into photoetching simulation software so as to perform comparative analysis on pattern data with the extracted pattern structure in the process of step E;
(2) converting the file format of the extracted graph structure into the file format same as that of the test graph so as to perform comparative analysis on graph data on an OPC software platform;
(3) and transferring the extracted graph structure file and the test graph file into third-party image contrast analysis software to perform graph or graph data contrast analysis.
Further, in step E, the graph structure includes an outer edge profile graph or graph data corresponding to the solid structure.
The invention introduces the graph comparison of the graph structure extracted from the actual wafer and the test graph into the correction application of the OPC model, avoids the deviation and limitation of measuring data of a plurality of CD sizes to the description of irregular actual graphs, directly compares the graph of the extracted entity structure graph and the test graph with the graph, optimizes the aspects of measuring errors, graph description errors and the like, reduces the iteration times of establishing and correcting the OPC model, and can quickly obtain a more accurate OPC model, thereby greatly improving the process efficiency of semiconductor design-manufacturing, and greatly improving the speed of chip yield ramp and the yield peak value. The cost is considerable, and the performance and yield of the chip are greatly improved.
Drawings
FIG. 1 is a flow chart of the method of the present invention.
Detailed Description
The technical solution of the present invention is further explained with reference to the drawings and the embodiments.
As shown in fig. 1, a method for correcting a novel OPC model includes the following steps:
a novel OPC model correction method comprises the following steps:
A. designing an OPC test pattern;
B. manufacturing an OPC mask;
C. establishing an OPC model;
D. carrying out OPC wafer production to manufacture a physical structure corresponding to the test pattern on the wafer; the physical structure may comprise an electronic or semiconductor device, a connection line, a logo, etc.
E. Identifying and extracting the graph structure on the wafer produced in the step D;
F. comparing and analyzing the graph structure extracted from the wafer in the step E with the test graph designed in the step A to obtain a part of the graph structure on the wafer, which is not matched or wrong relative to the test graph; in this embodiment, the test graph is a GDS file or a GDSII file, and after the file with the graph structure is extracted and converted into a file with the same format, graph data comparison analysis operation is performed on an OPC software platform;
G. correcting the OPC model aiming at the part which is obtained by the graph comparison analysis in the step F and is not matched with the test graph;
H. and D, repeating the step D to the step G until the graph structure on the wafer is completely matched with the test graph or the design precision requirement is met in the graph comparison analysis, and finishing the OPC model correction. In this embodiment, if the average Edge Placement Error (EPE) between the graph structure and the test graph reaches a minimum value, the OPC model correction is completed, and the specific evaluation function is the prior art and is not described herein again.
In the embodiment, the file format of the extracted graph structure is converted into the file format which is the same as that of the test graph, so that the comparison analysis of graph data is carried out on an OPC software platform, the calculation capability of the existing hardware platform and software is fully utilized, and the production process is effectively optimized on the basis of not increasing the resource input; besides, in actual production, the following two other modes can be adopted:
(1) inputting part or all of the OPC test patterns into photoetching simulation software so as to perform comparative analysis on pattern data with the extracted pattern structure in the process of step E; therefore, the correction target can be synchronously found in the image extraction process, so that correction information can be fed back more timely, and the efficiency of the manufacturing process is higher.
(2) And transferring the extracted graph structure file and the test graph file into third-party image contrast analysis software to perform graph or graph data contrast analysis. With the advance of the technology, the algorithms of the image contrast and the corresponding software are diversified, the same purpose can be achieved by correcting the image contrast analysis software of a third party, meanwhile, the occupation of production resources is avoided, and the arrangement and the coordination of a production plan are more convenient.
In the embodiment, the step E is to identify and extract the outer edge outline graph of the entity structure on the wafer through a high-resolution scanning electron microscope, and directly compare the graph with the graph after extraction, without measuring the critical dimension, so that the shrinkage of the photoresist and the measurement error in the measurement process are avoided; the measurement influence among different graphs in the traditional measurement process is avoided, the graph structure of the entity structure is obtained, the problem that complex graphs cannot be described by simple CD data is solved, the data accuracy is higher, more information is extracted, and the basis for providing feedback correction is more reliable. In actual production, any manner capable of extracting the outline graph of the solid structure can be used.
In the step G, the correction of the OPC model comprises the layout correction of the OPC mask, and the part with larger area coverage difference can be quickly locked through the graph comparison on one hand, so that the mask layout is corrected quickly in a targeted manner, and the method is more targeted and accurate compared with the previous correction mode and higher in the iteration efficiency of feedback-correction.
And the graph structure extracted from the wafer is correspondingly matched with the test graph through one or more of codes, serial numbers, coordinate information or graph scanning path nodes. For example, diode D1 of the design drawing feature is still associated with part code "D1" or corresponding part serial number after pattern recognition and pattern structure acquisition, and the associated test pattern is compared pattern to pattern. The graph tolerance or the unmatched part of the pattern feature based on the design feature can be used as the correction reference of the OPC model.
In the embodiment, the graph structure extracted from the actual wafer is compared with the graph of the test graph, the correction application of the OPC model is introduced, the deviation and the limitation of measuring data of several CD sizes to the description of the irregular actual graph are avoided, the graph and the graph of the extracted entity structure graph and the test graph are directly compared, the aspects of measuring errors, graph description errors and the like are optimized, the iteration times of establishing and correcting the OPC model are reduced, the more accurate OPC model can be quickly obtained, the process efficiency of designing and manufacturing the semiconductor is greatly improved, and the saved cost is considerable.
Finally, the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all of them should be covered in the claims of the present invention.
Claims (5)
1. A novel OPC model correction method is characterized in that: comprises the following steps:
A. designing an OPC test pattern;
B. manufacturing an OPC mask;
C. establishing an OPC model;
D. carrying out OPC wafer production to manufacture a physical structure corresponding to the test pattern on the wafer;
E. identifying and extracting the graph structure on the wafer produced in the step D;
F. comparing and analyzing the graph structure extracted from the wafer in the step E with the test graph designed in the step A to obtain a part of the graph structure on the wafer, which is not matched or wrong relative to the test graph;
G. correcting the OPC model aiming at the part which is obtained by the graph comparison analysis in the step F and is not matched with the test graph;
H. repeating the step D to the step G until the graph structure on the wafer is completely matched with the test graph or the design precision requirement is met in the graph comparison analysis, and finishing the OPC model correction;
in step E, the graph contrast analysis comprises any one of the following modes:
(1) inputting part or all of the OPC test patterns into photoetching simulation software so as to perform comparative analysis on pattern data with the extracted pattern structure in the process of step E;
(2) converting the file format of the extracted graph structure into the file format same as that of the test graph so as to perform comparative analysis on graph data on an OPC software platform;
(3) and transferring the extracted graph structure file and the test graph file into third-party image contrast analysis software to perform graph or graph data contrast analysis.
2. The method for correcting the novel OPC model according to claim 1, wherein: in step E, the graph structure contains the outer edge profile graph or graph data corresponding to the solid structure.
3. The novel OPC model correction method of claim 1, wherein: the test graph is a GDS file or a GDSII file, and after the file with the graph structure is extracted and converted into a file with the same format, graph data comparison analysis operation is carried out on an OPC software platform.
4. The method for correcting a novel OPC model according to claim 1, wherein: in step G, the correction of the OPC model includes a layout correction of the OPC mask.
5. The method for correcting a novel OPC model according to claim 1, wherein: and the graph structure extracted from the wafer is correspondingly matched with the test graph through one or more of codes, serial numbers, coordinate information or graph scanning path nodes.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111158210A (en) * | 2020-03-10 | 2020-05-15 | 长江存储科技有限责任公司 | Optical proximity correction method for photomask, photomask and semiconductor manufacturing method |
| CN111427240A (en) * | 2020-03-25 | 2020-07-17 | 合肥晶合集成电路有限公司 | Method for establishing optical data correction model |
| CN112230507A (en) * | 2020-10-22 | 2021-01-15 | 泉芯集成电路制造(济南)有限公司 | Optical proximity correction model construction method and device and computer equipment |
| CN112415847A (en) * | 2020-11-20 | 2021-02-26 | 长江存储科技有限责任公司 | Optical proximity correction method |
| CN113990770A (en) * | 2021-12-28 | 2022-01-28 | 晶芯成(北京)科技有限公司 | Wafer detection method and detection device |
| CN116071319A (en) * | 2023-01-28 | 2023-05-05 | 合肥新晶集成电路有限公司 | Model building method, device, computer equipment and storage medium |
| CN112433442B (en) * | 2020-12-01 | 2024-06-21 | 泉芯集成电路制造(济南)有限公司 | Mask pattern correction method, device, computer equipment and readable storage medium |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111158210A (en) * | 2020-03-10 | 2020-05-15 | 长江存储科技有限责任公司 | Optical proximity correction method for photomask, photomask and semiconductor manufacturing method |
| CN111427240A (en) * | 2020-03-25 | 2020-07-17 | 合肥晶合集成电路有限公司 | Method for establishing optical data correction model |
| CN112230507A (en) * | 2020-10-22 | 2021-01-15 | 泉芯集成电路制造(济南)有限公司 | Optical proximity correction model construction method and device and computer equipment |
| CN112415847A (en) * | 2020-11-20 | 2021-02-26 | 长江存储科技有限责任公司 | Optical proximity correction method |
| CN112433442B (en) * | 2020-12-01 | 2024-06-21 | 泉芯集成电路制造(济南)有限公司 | Mask pattern correction method, device, computer equipment and readable storage medium |
| CN113990770A (en) * | 2021-12-28 | 2022-01-28 | 晶芯成(北京)科技有限公司 | Wafer detection method and detection device |
| CN113990770B (en) * | 2021-12-28 | 2022-03-22 | 晶芯成(北京)科技有限公司 | Wafer detection method and detection device |
| CN116071319A (en) * | 2023-01-28 | 2023-05-05 | 合肥新晶集成电路有限公司 | Model building method, device, computer equipment and storage medium |
| CN116071319B (en) * | 2023-01-28 | 2023-06-27 | 合肥新晶集成电路有限公司 | Model building method, device, computer equipment and storage medium |
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