CN114442438A - Core grain arrangement optimization algorithm for variable grids - Google Patents
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Abstract
The invention provides a core grain arrangement optimization algorithm of a variable grid, which comprises the following steps: s1, establishing a rectangular coordinate system, wherein the X, Y axis of the rectangular coordinate system is tangent to the edge of the wafer; s2: taking the origin of coordinates of the rectangular coordinate system as a starting point, finding the optimal combination of the offsets of the Die in the X direction and the Y direction by adopting a bisection method, so that the number of the Die divided on the wafer is the largest, and obtaining the array arrangement of the Die; s3, setting the X-direction and Y-direction offset of the Shot of a single exposure unit according to the Die arrangement obtained in S2 to minimize the number of shots required for covering the wafer and obtain the Shot arrangement; the variable-grid core particle arrangement optimization algorithm provided by the invention has the advantages that the calculated amount is far smaller than that of the conventional fixed grid optimization algorithm, the calculation time is greatly shortened, and meanwhile, the result judgment is added, so that the accuracy of the result is ensured. The invention effectively overcomes the defects of large optimization calculation amount, long time consumption, inaccurate result and the like in the prior art, and has higher practical value in the field of semiconductor manufacturing.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a variable-grid core grain arrangement optimization algorithm.
Background
In a semiconductor process, a Die array design is usually performed on an entire wafer, and the manufacturing cost of the wafer is expensive, so that it is necessary to divide as many dice as possible on a wafer with a fixed size. In the process of dividing the wafer, a photoetching process is used certainly, the complete photoetching process comprises the working procedures of cleaning, gluing, soft baking, exposure, developing, etching, detection and the like, and the exposure is a key step for determining the number of the final Dies. The exposure process is to transfer the pattern on the mask plate to the wafer, so that the placement of the mask plate directly determines the final Die array arrangement, and the placement position of the mask plate is obtained through the prior Die array arrangement design. Since the wafer is generally circular and Die is generally regular rectangular, incomplete Die must occur at the edge of the wafer during exposure. Therefore, simulation calculation is needed before exposure, and the complete Die on the wafer is ensured to be the most by continuously changing the relative positions of the Die and the wafer, so that the optimal Die arrangement is obtained. In an actual array layout design, a wafer often has unusable areas such as defects, flag bits, laser codes and the like, and these factors need to be taken into consideration during the array layout design. In addition, since the exposure system has a limited area for one exposure, one wafer needs to be divided into a plurality of exposure units (shots) for exposure imaging, and it is also an objective pursued by the technicians to reduce the number of shots as much as possible. And finally obtaining the largest Die and the smallest Shot through the design arrangement of the Die.
The current commonly used algorithm for array arrangement usually adopts a fixed grid optimization algorithm, which substantially changes the offset linearly so as to change the relative position relationship between Die and wafer, calculates the number of Die under various position relationships, and selects the corresponding position relationship when the most Die is selected from the Die, and converts the problem of finding the optimal Die arrangement into the problem of finding the optimal offset, and the specific steps are as follows: as shown in FIG. 1, a rectangular coordinate system is established, wherein the X, Y axis of the rectangular coordinate system is tangent to the edge of the wafer, and the length and width of each single Die are determined to be X0、Y0Is mixing X0、Y0Are respectively divided into a plurality of equal parts, and the length of each part is X assuming that the parts are divided into 100 equal parts0/100、Y0/100. Offset amounts X offset and Y offset are set, and the offset amounts X offset are set to X in order0/100、2X0/100、……、X0Sequentially setting the offset Y offset to Y0/100、2Y0/100、……、Y0In this way, the total of 100 × 100 sets of X offset and Y offset is 10000. Through traversing the 10000 combination settings of the X offset and the Y offset, the number of complete Dies which can be arranged on the wafer under the 10000 conditions is calculated, and the X offset and the Y offset which correspond to the maximum number of the complete Dies are selected, so that the placement position of the mask is determined, and the optimal Die array arrangement is obtained.
Using the above-mentioned fixed grid optimization algorithm memoryIn some cases, the quality of the result is directly determined by X0、Y0Number of aliquots determined because of X0、Y0The more equal parts, the more the permutation and combination, the more the traversal, the greater the probability of the optimal Die array arrangement, but the more equal parts will increase the calculation amount by times and increase the time consumption. Taking 8 inch wafer as an example, when Die with 2.06mm X1.64 mm is arrayed, the length and width X of Die is measured0、Y0All are equally divided into 160 parts, and at the moment, the time for obtaining the optimal Die array arrangement is 90 minutes, and the calculation is 25600 times, so that the calculation amount is large and the time is long. Furthermore, this method does not ensure that the results are optimal, in theory, X0、Y0When the number of the divided parts is infinite, the obtained result is optimal, but only the length and the width X of the Die are generally determined in consideration of time-consuming influence0、Y0Equal division into 100 parts does not guarantee that the results obtained are optimal. In addition, the influence of unavailable areas such as defects, mark bits, laser etching codes and the like is added, and the obtained array arrangement result is more doubtful.
Therefore, a new Die array arrangement method needs to be proposed to solve the above problems.
Disclosure of Invention
In view of the above disadvantages of the prior art, an object of the present invention is to provide a variable-grid kernel arrangement optimization algorithm, which is used to solve the problems of large calculation amount, inaccurate result, long time consumption, etc. of the conventional fixed grid optimization algorithm. The method for calculating the Die array arrangement on the wafer comprises the following steps:
and S1, establishing a rectangular coordinate system, wherein the X, Y axis of the rectangular coordinate system is tangent to the edge of the wafer.
S2: and with the origin of coordinates as a starting point, finding the optimal combination of the X-direction offset (X offset) and the Y-direction offset (Y offset) of the Die arrangement by adopting a bisection method, so that the number (Die Count) of the complete Die divided on the wafer is the largest, and obtaining the array arrangement of the Die.
And S3, setting the X-direction offset (XRet) and the Y-direction offset (Yret) of the Shot of the single exposure unit according to the Die array arrangement obtained in the S2, and minimizing the number of shots required for covering the wafer to obtain the Shot arrangement.
Specifically, the step S2 specifically includes the following steps:
s2-1: determining the length and width of a single Die to be X respectively0、Y0Is mixing X0、Y0Are respectively divided into a plurality of parts p and q in equal parts, wherein p and q are positive integers.
S2-2: the offset amounts X offset and Y offset are set to X in sequence0/p，2X0/p，……，X0Sequentially setting the offset Y offset to Y0/q，2Y0/q，……，Y0Traversing the p × q combinations of X offsets and Y offsets, calculating Die counts that can be arranged on the wafer in p × q cases, selecting all combinations of X offsets and Y offsets from the Die counts that correspond to when the Die Count is greater than a certain threshold, setting the selected combinations of X offsets and Y offsets as I-level pseudo points, and setting the threshold as I-level point threshold.
S2-3: on the basis of the class I suspected points selected in S2-2, class II points are regularly positioned around each class I suspected point in a shape of a Chinese character 'tian', and after the class II points are connected with each other in the X and Y directions, the length and the width of a formed grid are respectively X0/2p、Y0And/2 q. And calculating the Die Count corresponding to the II-level point, selecting all the corresponding combination settings of X offset and Y offset when the Die Count is larger than a certain threshold value, setting the selected combination of X offset and Y offset as the II-level suspected point, and setting the threshold value at the moment as the II-level point threshold value.
S2-4: and sequentially finding the class III suspected point, the class IV suspected point, the class V suspected point, … … and the class k suspected point by an iteration method. After the obtained k-level suspected points are connected with each other in the X and Y directions, the length and the width of a formed grid are respectively X0/2(k-1)p、Y0/2(k-1)q is calculated. And taking the combination of X offset and Y offset corresponding to the k-level suspected point with the largest Die Count as the final optimal solution, wherein k is a positive integer.
Specifically, the step S3 specifically includes the following steps:
and determining the number of Dies contained in a single Shot as m x n, wherein the length and the width of the single Die are the step length for shifting the Shot. There are m cases of Shot offset along the X axis and n cases of Shot along the Y axis, all cases of the two directions are grouped together for m X n cases. And calculating the number of the shots needed for covering the wafer under m × n conditions, wherein the offset corresponding to the minimum number of shots is the optimal Shot arrangement, and m and n are positive integers.
Optionally, the step S2 further includes the following steps:
s2-5, finding k-level suspected points through judgment conditions in the step S2-4, terminating the algorithm after the judgment conditions are met, wherein the obtained k-level suspected points are real optimal points, the judgment conditions of the terminating algorithm are that the maximum Die Count obtained by the new-level calculation is the same as the previous-level calculation, and meanwhile, the class of the suspected points corresponding to the maximum Die Count is the same as the class of the previous-level calculation. Specifically, the method for determining the suspected point class includes:
after the suspected points of each level are found in step S2, clustering analysis is performed on the suspected points of each level, a spatial distance between the suspected points is calculated, a threshold is set, the suspected points whose spatial distance is smaller than the threshold and whose corresponding Die number is the same are classified into a class, and the class threshold is determined according to the number of the suspected points.
Optionally, before performing S2, the unusable areas with defects, flags, and laser codes in the wafer are divided, and the specific steps are as follows: the unusable areas are accurately positioned on the wafer, the areas are classified as invalid areas during array layout calculation, and the invalid areas are excluded during Die Count calculation.
Optionally, the level I point threshold setting rule in step S2-2 is: the corresponding Die counts in the case of p × q are sorted in descending order, and the threshold value is set so that the point sorted at the top 3/4 comes within the range of the I-level suspect point.
Optionally, in step S2-4, the k-point threshold setting rule is: and sorting the Die numbers corresponding to the k-level points in a descending order, and setting a threshold value to enable the point with the Die number sorted in the top i names to enter a k-level suspected point range. Where i is a positive integer, the value of i may be set to 5.
Optionally, the length and width X of the Die are adjusted in the step S2-20、Y0Are all equally divided into 10 parts, i.e. p and q are both 10.
Specifically, using the above optimization algorithm for varying the core grain arrangement of the grid, length and width X are arranged on a wafer having a diameter of 8 inches0、Y0When the optimal Die arrangement is obtained by the core particles of 2.06mm and 1.64mm respectively, the algorithm calculates 1016 times totally, takes 3 minutes and 30 seconds, and obtains the maximum Die Count of 8515.
In summary, the Die arrangement optimization algorithm for the variable grids provided by the invention has the following beneficial effects: when the optimal offset combination is searched, a suspected point is searched first, then analysis is carried out on the area near the suspected point, and the iteration is carried out to find the optimal point. The calculation amount is far less than that of a fixed grid optimization algorithm when the method is used, the calculation time is greatly shortened, and meanwhile, result judgment is added, so that the accuracy of the result is ensured. Therefore, the method effectively overcomes the defects of large optimization calculation amount, long time consumption, inaccurate result and the like in the prior art, and has higher practical value in the field of semiconductor manufacturing.
Drawings
The features and advantages of the invention will be more clearly understood by reference to the accompanying drawings, which are illustrative and should not be understood as limiting the invention in any way, in which:
FIG. 1 is a schematic diagram showing the offset setting rule in Die arrangement
FIG. 2 is a diagram illustrating the first-level point results obtained by the first embodiment
FIG. 3 is a schematic diagram of a grid formed by two-level point interconnection
FIG. 4 is a schematic diagram of secondary suspect points selected from the secondary suspect points shown in FIG. three
FIG. 5 is a diagram showing the optimal point results obtained in the first embodiment
FIG. 6 is a schematic diagram showing classification in an example of a two-class analysis
FIG. 7 is a schematic diagram showing the optimal points obtained in the second embodiment and the categories thereof
FIG. 8 shows the optimal point coordinates obtained in example two
FIG. 9 is a schematic view of wafer processing with unusable areas according to the third embodiment
FIG. 10 is a diagram showing the rule of setting the offset when the shots are arranged in the fourth embodiment
FIG. 11 is a diagram showing the Shot count results obtained by setting different offsets when shots are arranged in the fourth embodiment
FIG. 12 is a schematic view showing the arrangement of the minimum Shot obtained in the fourth example
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example one
The embodiment provides a Die arrangement optimization algorithm for a variable grid, which specifically includes the following steps:
and S1, establishing a rectangular coordinate system, wherein the X, Y axis of the rectangular coordinate system is tangent to the edge of the wafer.
S2: and finding the optimal combination of the offsets X offset and Y offset by using a dichotomy with the origin of coordinates as a starting point to maximize the Die Count divided on the wafer, thereby obtaining the array arrangement of the dice.
The step S2 specifically includes the following steps:
s2-1, dividing the length and width X of Die0、Y0Are all equally divided into 10 parts, and the length and the width of each part are respectively X0/10、Y0/10；
S2-2, sequentially setting the X-direction offset X offset of Die arrangement as X0/10，2X0/10，……，X0(ii) a Sequentially setting the Y-direction offset Y offset of the Die arrangement as Y0/10，2Y0/10，……，Y 0. A total of 10 × 10 to 100 offset amounts X offset and Y offset are set in combination, Die Count obtained in these 100 cases is sequentially calculated, and then the Die Count obtained is obtainedIn the descending order of Die counts, the points with the number of Die counts above the first 75% are selected, i.e. the combination of the superior X offset and Y offset values is selected, as shown in fig. 2, the abscissa represents the X offset value, the ordinate represents the Y offset value, the solid points marked in the figure represent the selected superior combination, and the abscissa of these points also represents the corresponding X offset and Y offset values. Meanwhile, points obtained in the step are classified as I-grade suspected points which are named as P1, P2, P3, P4 and … … for convenience of description;
s2-3, on the basis of the I-grade suspected points selected in S2-2, eight points adjacent to each I-grade point P1, P2, P3, P4 and … … are positioned in a shape rule of a Chinese character 'tian', the II-grade points are named as P11, … …, P18, P21, … …, P28, P31, … …, P38 and … … for convenience of description, and as shown in FIG. 3, after the II-grade points are connected with each other in the X and Y directions, the length and width of the formed grids are X respectively0/20、Y0/20, corresponding to X in each original length and width0/10、Y0On the basis of/10, the mixture is divided into two parts again, wherein the length and the width of each part are respectively X0/20、Y0/20. And (3) calculating the II-level points obtained in the step to obtain the Die counts corresponding to the points, sorting the obtained Die counts in a descending order, selecting the points with the number of the Die counts ranked five, namely selecting the combination of the superior X offset and Y offset values in the II-level points, wherein the marked points in the figure represent the selected superior combination as shown in figure 4, and classifying the selected points as the II-level suspected points.
On the basis of the II-level suspected points, the same method is adopted to position eight adjacent points of each II-level suspected point in a shape rule of a Chinese character 'tian' shape to obtain III-level points, and after the III-level points are connected in the X and Y directions, the length and the width of a formed grid are respectively X0/40、Y040, corresponding to X in each length and width0/20、Y0On a/20 basis, the mixture was divided into two equal portions again. Calculating the newly added points to obtain Die counts corresponding to all class-III points, sorting the obtained Die counts in a descending order, selecting the points with the number of the Die counts ranked five at the top, and classifying the selected points as class-III suspected pointsAnd (4) point.
And S2-4, sequentially finding the IV-level suspected points and the V-level suspected points according to the steps, and taking the combination of the X offset and the Y offset corresponding to the largest Die Count in the V-level suspected points as the final optimal solution.
Example two
The present embodiment also provides a method for calculating Die array layout on a wafer, which is the same as the first embodiment and is not repeated herein, except that:
after the suspected points of each level are found in the first embodiment, the suspected points of each level are respectively subjected to cluster analysis, as shown in fig. 6, the suspected points are classified, and each closed curve in the diagram represents a class. The method for classifying suspected points by clustering analysis comprises the following steps: and calculating the spatial distance between the suspected points, setting a threshold value of the class, and classifying the suspected points which have the same numerical value and correspond to the Die Count and are less than the threshold value into one class. The threshold of the class is determined according to the number of the suspected points, for example, the I-level suspected points are far away from each other, and the threshold of the class is larger at the moment; for class V suspect points that are closer to each other, the threshold for this class is smaller. In this embodiment, the threshold value during classification is 2 times of the length and width of the grid corresponding to the suspected point level, for example, when classifying I-level suspected points, the threshold value during classification is X0/5、Y0(iii)/5; the length and width threshold value when classifying the III-grade suspected points is X0/20、Y0/20。
In order to obtain a more accurate optimal solution, after the level V suspected point is calculated in step S2-4, the algorithm is not stopped, and the algorithm continues to calculate downwards to obtain the level VI suspected point, the level VII suspected point, and … …, but the algorithm cannot calculate downwards all the time, and a judgment termination algorithm needs to be added. The condition of the termination algorithm is that the maximum Die Count obtained by the new step is the same as the previous step, and the class of the suspected point corresponding to the maximum Die Count is the same as the one calculated in the previous step. The significance of this determination is that, even if it is determined that the Die Count at this time is the maximum, and the suspected point corresponding to the Die Count is within the range of the class determined in the previous step, it is ensured that the suspected point does not appear outside the class range, otherwise, the suspected point outside the class range is continuously analyzed and calculated without stopping.
As shown in fig. 7, for the optimal points calculated and judged by the above algorithm, dice of 2.06mm by 1.64mm were arranged on a wafer having a diameter of 8 inches, and there were 5 optimal points in total, and the 5 optimal points were classified into three types. One class is represented within each small circle. As shown in fig. 8, for the specific information such as the coordinates of the 5 points, the final Die Count of the 5 points is 8515, and cluster indicates the class to which each of the 5 points belongs. The optimal Die arrangement is obtained by using the variable grid algorithm, the total time is 1016 times, and 3 times of 30 seconds are consumed. Compared with a fixed grid optimization algorithm, the method greatly reduces the calculation amount and shortens the time consumption. Meanwhile, the optimal point obtained through calculation and judgment of the algorithm is a real optimal point.
EXAMPLE III
The embodiment provides a method for calculating Die array layout on a wafer, which mainly aims at performing Die array layout on a wafer with unusable areas such as defects, mark bits and laser codes. The same points as those in the second embodiment are not described in detail, but the differences are as follows:
before S2 is executed, the unusable areas of the wafer are further divided, as shown in fig. 9, the unusable areas are accurately located on the wafer, when the array layout calculation is performed, the areas are classified as invalid areas, and when the Die Count is calculated, the invalid areas are excluded, so that the optimal point obtained by the algorithm calculation in embodiment 2 is the true optimal point and also the optimal point which best meets the actual situation.
Example four
The embodiment provides a method for calculating Shot arrangement on a wafer, which is mainly used for carrying out arrangement design on shots after Die array arrangement is completed so as to minimize the number of shots. The step is similar to the method for determining the optimal Die arrangement, and also adopts a method for gradually changing the offset to compare the Shot numbers under various offsets to obtain the optimal Shot arrangement. On the basis of the third embodiment, the embodiment further comprises the following steps:
s3, according to the Die array arrangement obtained in S2, setting the X direction offset (XRet) and the Y direction offset (YRet) of the Shot of a single exposure unit to minimize the number of shots covering the wafer, so as to obtain the Shot arrangement
The step S3 specifically includes the following steps:
as shown in fig. 10, after the Die array arrangement is determined, the position of the default Shot is shown by the dashed rectangle in the figure, i.e. the right angle of the Shot coincides with the right angle of the outermost periphery Die. Assuming that m × n Die are contained in the Shot, and the Shot shift is in the length and width of a single Die, there are m cases of Shot shift along the X axis and n cases of Shot shift along the Y axis, and all cases in both directions are grouped together to have m × n cases. As shown in fig. 10, the solid rectangle is the location of the Shot after the shift, and the shift amounts of the Shot in the X and Y directions are defined as XRet and YRet, respectively, when the Shot is shifted by a length of 1 Die in both the X and Y directions with respect to the default location, i.e., XRet and YRet are both 1.
As shown in fig. 11, which is a partial demonstration of the Shot calculation result in this embodiment, when XRet is fixed to 1, YRet increases from 1 to 20 in sequence, and the corresponding Shot number (Shot Count) has different results. The Shot number was 44 at minimum and 50 at maximum. As shown in fig. 12, which is a corresponding arrangement diagram when the Shot number is 44, it can be seen that the Shot number of all Die covered on the wafer is 44.
In summary, the optimization algorithm for the core particle arrangement of the variable grid provided by the invention has the following beneficial effects: when the optimal offset combination is found, firstly, suspected points are found, then, the area near the suspected points is analyzed, and the iteration is carried out to find the optimal points. The calculation amount is far less than that of a fixed grid optimization algorithm when the method is used, the calculation time is greatly shortened, and meanwhile, result judgment is added, so that the accuracy of the result is ensured. Therefore, the method effectively overcomes the defects of large optimization calculation amount, long time consumption, inaccurate result and the like in the prior art, and has higher practical value in the field of semiconductor manufacturing.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A core grain arrangement optimization algorithm of a variable grid is characterized by comprising the following steps:
s1, establishing a rectangular coordinate system, wherein the X, Y axis of the rectangular coordinate system is tangent to the edge of the wafer;
s2: and taking the coordinate origin of the rectangular coordinate system as a starting point, and finding the optimal combination of the X-direction offset and the Y-direction offset of the Die arrangement by adopting a bisection method to maximize the number of the Die divided on the wafer so as to obtain the Die arrangement.
2. The variable-grid kernel arrangement optimization algorithm according to claim 1, further comprising the steps of:
and S3, setting the X-direction offset and the Y-direction offset of the Shot of a single exposure unit according to the Die arrangement obtained in the S2 to minimize the number of shots required for covering the wafer, thereby obtaining the Shot arrangement.
3. The optimization algorithm for core grain arrangement of variable grid according to claim 2, wherein the step S2 specifically comprises the following steps:
s2-1: determining the length and width of a single Die to be X respectively0、Y0Is mixing X0、Y0Respectively equally dividing into a plurality of parts p and q;
s2-2: sequentially setting the X-direction offset of the Die arrangement as X0/p，2X0/p，……，X0Sequentially setting the Y-direction offset of the Die arrangement as Y0/q，2Y0/q，……，Y0Traversing the p X q combinations of the X-direction offset and the Y-direction offset, calculating the number of Die which can be arranged on the wafer under the p X q conditions, selecting the combination of the X-direction offset and the Y-direction offset which corresponds to the Die arrangement when the number of Die is larger than a certain threshold value, setting the selected combination as an I-level suspected point, and setting the selected combination as an I-level suspected pointSetting the threshold as a level I point threshold, wherein p and q are positive integers.
4. The variable-grid kernel assignment optimization algorithm according to claim 3, wherein the step S2 further comprises the steps of:
s2-3: on the basis of the class I suspected points selected in S2-2, class II points are regularly positioned around each class I suspected point in a shape of a Chinese character 'tian', and after the class II points are connected with each other in the X and Y directions, the length and the width of a formed grid are respectively X0/2p、Y02q, calculating the number of Dies corresponding to the II-level point, picking out a combination of X-direction offset and Y-direction offset which are distributed corresponding to the Dies when the number of the Dies is larger than a certain threshold value, setting the picked combination as the II-level suspected point, and setting the threshold value at the step as the II-level point threshold value;
s2-4: sequentially finding a class III suspected point, a class IV suspected point, a class V suspected point, … … and a class k suspected point by an iteration method, wherein the length and width of a formed grid are respectively X after the obtained class k suspected points are mutually connected in the X and Y directions0/2(k-1)p、Y0/2(k-1)And q, taking the combination of the X-direction offset and the Y-direction offset of the Die arrangement corresponding to the k-level suspected points with the largest number of Dies as a final optimal solution, wherein k is a positive integer.
5. The optimization algorithm for core grain arrangement of variable grid according to claim 2, wherein the step S3 specifically comprises the following steps:
determining that the number of Dies contained in a single Shot is m × n, the Shot offset step is the length and width of the single Die, so that m cases exist in the X-direction offset of the Shot, n cases exist in the Y-direction offset of the Shot, and all the cases of the X-direction offset and the Y-direction offset of the Shot are combined together to share the m × n cases. And calculating the number of the shots needed for covering the wafer under m × n conditions, wherein the offset corresponding to the minimum number of shots is the optimal Shot arrangement, and m and n are positive integers.
6. The variable-grid kernel assignment optimization algorithm according to claim 4, wherein the step S2 further comprises the steps of:
s2-5, finding k-level suspected points through the judgment condition in the step S2-4, terminating the algorithm after the judgment condition is met, wherein the obtained k-level suspected points are real optimal points, the judgment condition of the termination algorithm is that the maximum Die number obtained by the new-level calculation is the same as that of the previous-level calculation, and the class of the suspected points corresponding to the maximum Die number is the same as that of the previous-level calculation.
7. The variable-grid kernel arrangement optimization algorithm according to claim 6, wherein the suspected point class is determined by:
after the suspected points of each level are found in step S2, clustering analysis is performed on the suspected points of each level, a spatial distance between the suspected points is calculated, a threshold is set, the suspected points whose spatial distance is smaller than the threshold and whose corresponding Die number is the same are classified into a class, and the class threshold is determined according to the number of the suspected points.
8. The variable-grid core grain arrangement optimization algorithm according to claim 3, wherein before executing S2-1, the unusable areas with defects, flags, radium etching codes, etc. in the wafer are divided, and the specific steps are as follows: the unusable areas are accurately positioned on the wafer, the areas are classified as invalid areas when Die arrangement calculation is carried out, and the invalid areas are excluded when the Die number is calculated.
9. The variable-grid kernel assignment optimization algorithm according to claim 4, wherein the k-level point threshold setting rule is: and sorting the Die numbers corresponding to the k-level points in a descending order, and setting a threshold value to enable the points with the Die numbers sorted in the top i names to enter a k-level suspected point range, wherein i is a positive integer.
10. The varied-grid kernel placement optimization algorithm of claim 9, wherein the value of i is 5.
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