CN114423180A - QFN lead-free low-voidage welding method - Google Patents
QFN lead-free low-voidage welding method Download PDFInfo
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- CN114423180A CN114423180A CN202210150762.4A CN202210150762A CN114423180A CN 114423180 A CN114423180 A CN 114423180A CN 202210150762 A CN202210150762 A CN 202210150762A CN 114423180 A CN114423180 A CN 114423180A
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- qfn
- solder paste
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- pattern
- steel mesh
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
- H05K13/04—Mounting of components, e.g. of leadless components
- H05K13/046—Surface mounting
- H05K13/0465—Surface mounting by soldering
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
- H05K13/08—Monitoring manufacture of assemblages
- H05K13/081—Integration of optical monitoring devices in assembly lines; Processes using optical monitoring devices specially adapted for controlling devices or machines in assembly lines
- H05K13/0817—Monitoring of soldering processes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3494—Heating methods for reflowing of solder
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/043—Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Operations Research (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
The invention provides a QFN lead-free low-voidage welding method which comprises the following steps: identifying the chip packaging size of the QFN, the alloy area definition and the electronic design draft of the integrated circuit board; generating a tin paste printing transfer steel mesh design scheme according to the electronic design draft to obtain a steel mesh pattern; detecting the integrity of the steel mesh graph by adopting a photoplotting file, confirming the graph meeting the design requirement, and obtaining a design graph; using SAC305 solder paste No. 4 powder particles to perform environment tempering and stirring; erecting and transferring the steel mesh by using a solder paste printer and carrying out visual angle positioning; printing a solder paste pattern by using a printer, transferring, mounting a scraper and filling solder paste to obtain a printing pattern; transferring and detecting the printed pattern by using automatic 3D optical equipment; and mounting the QFN chip by using full-automatic mounting equipment. The problem that when a QFN packaged electronic product uses a traditional QFN lead-free welding process, the power consumption and the reliability of the product are affected due to the fact that the welding voidage is too high is solved.
Description
Technical Field
The invention relates to the field of integrated circuit electronic assembly, in particular to a QFN lead-free low-void-rate welding method.
Background
The defects of the conventional existing QFN welding basic process method for integrated circuit electronic products are as follows: firstly, when identifying the QFN chip closed metal layer, the graphic design of solder paste transfer printing needs to be verified repeatedly, which is not beneficial to effective mass operation of products and increases the period of product introduction; when the solder paste is transferred to the PCB, the parameters of the printer need to be repeatedly adjusted to ensure the volume and shape of the transfer, and the graphic volume of missing printing and demoulding is prevented from occurring in the process of transferring the solder paste to the PCB; and then, scanning and confirming graphs of the product by automatic 3D optical equipment, mounting the device by a chip mounter, and carrying out temperature curve welding by using nitrogen reflow soldering equipment.
When the product is provided with QFN packaged chips, the following problems exist: a. the consistency of the printed patterns is not well controlled, otherwise, the problems of missing printing and short circuit can be caused in the printing process; b. when the product is soldered with a reflow soldering temperature curve, the problem of cavities with a higher area can occur, so that the problems of chip power consumption increase and operation reliability decrease can occur.
Disclosure of Invention
In view of the above problems, the present invention has been made to provide a QFN lead-free low void ratio soldering method that overcomes or at least partially solves the above problems.
According to one aspect of the invention, a method for welding a QFN lead-free low voidage comprises the following steps:
identifying the chip packaging size of the QFN, the alloy area definition and the electronic design draft of the integrated circuit board;
generating a tin paste printing transfer steel mesh design scheme according to the electronic design draft to obtain a steel mesh pattern;
detecting the integrity of the steel mesh graph by adopting a photoplotting file, confirming the graph meeting the design requirement, and obtaining a design graph;
the SAC305 solder paste No. 4 powder particles are used for environment temperature return and stirring to meet the operation conditions;
erecting and transferring the steel mesh by using a solder paste printer and positioning a visual angle to ensure accurate superposition;
printing a solder paste pattern by using a printer, transferring, mounting a scraper and filling solder paste to obtain a printing pattern;
transferring the printed pattern by using automatic 3D optical equipment, detecting, and detecting whether the volume of the printed pattern meets a set requirement;
and mounting the QFN chip by using full-automatic mounting equipment.
Optionally, after the mounting of the QFN chip by using the fully automatic mounting apparatus, the method further includes:
measuring a temperature formula by using a KIC furnace temperature curve tester, and automatically analyzing curve parameters of the formula;
carrying out welding implementation of a temperature formula by using reflow welding equipment of an air medium;
mounting detection is carried out by using an automatic optical detection machine, and the accuracy of the mounting coordinate is detected;
and performing nondestructive inspection by using an X-ray inspection machine, and confirming the porosity after welding.
Optionally, the thickness of the solder paste printing transfer steel mesh design is 120 um.
Optionally, the pattern design of the solder paste printing transfer is an oblique angle type multi-rib position design.
Optionally, the temperature range of the welding implementation of the temperature formula is 235-245 ℃.
Optionally, the reflow temperature of the soldering implementation of the temperature formula is controlled within 60-80 seconds at 217 ℃.
Optionally, the temperature of the temperature formula is controlled within a range of 150-190 ℃ and kept within 100-120 seconds.
The invention provides a QFN lead-free low-voidage welding method which comprises the following steps: identifying the chip packaging size of the QFN, the alloy area definition and the electronic design draft of the integrated circuit board; generating a tin paste printing transfer steel mesh design scheme according to the electronic design draft to obtain a steel mesh pattern; detecting the integrity of the steel mesh graph by adopting a photoplotting file, confirming the graph meeting the design requirement, and obtaining a design graph; the SAC305 solder paste No. 4 powder particles are used for environment temperature return and stirring to meet the operation conditions; erecting and transferring the steel mesh by using a solder paste printer and positioning a visual angle to ensure accurate superposition; printing a solder paste pattern by using a printer, transferring, mounting a scraper and filling solder paste to obtain a printing pattern; transferring the printed pattern by using automatic 3D optical equipment, detecting, and detecting whether the volume of the printed pattern meets a set requirement; and mounting the QFN chip by using full-automatic mounting equipment. The problem that when a QFN packaged electronic product uses a traditional QFN lead-free welding process, the power consumption and the reliability of the product are affected due to the fact that the welding voidage is too high is solved.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of an implementation relationship in a QFN packaged chip lead-free low-cavity soldering method according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a method for soldering a QFN packaged chip without lead in a low cavity according to an embodiment of the present invention.
Description of the drawings: the device comprises a substrate 1, a chip graph 2, a solder paste transfer machine 3, a solder paste transfer graph steel mesh 4, automatic 3D optical graph detection equipment 5, a chip mounter 6, reflow soldering equipment 7 and an X-ray detection machine 8.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The terms "comprises" and "comprising," and any variations thereof, in the present description and claims and drawings are intended to cover a non-exclusive inclusion, such as a list of steps or elements.
The technical solution of the present invention is further described in detail with reference to the accompanying drawings and embodiments.
As shown in fig. 1 and fig. 2, a method for a chip lead-free low-cavity soldering process of a QFN package in the present embodiment includes:
identifying the chip packaging size and alloy area definition of QFN and an electronic design draft of a substrate 1 of an integrated circuit board, and confirming data by using Gerber View software;
step two, designing and generating a tin paste printing transfer steel mesh design scheme according to the chip graph 2, wherein the thickness of the steel mesh is designed to be 120 um;
step three, detecting the integrity of the steel mesh graph by using a photoplotting file, confirming the graph completely meeting the design requirement, designing the graph transferred by the solder paste into an oblique angle type multi-rib position design, and improving a welding flux reaction channel of a welding region;
step four, using SAC305 solder paste No. 4 powder particles to carry out environment temperature return and stirring, and meeting the operation conditions;
fifthly, erecting and transferring the solder paste transfer printing graphic steel mesh 4 by using a solder paste transfer printing machine 3 and carrying out visual angle positioning to ensure accurate superposition;
sixthly, printing the solder paste transfer pattern steel mesh 4 by using a printer for transfer, and mounting a scraper and filling solder paste;
seventhly, detecting the transferred pattern by using automatic 3D optical pattern detection equipment 5, wherein the volume of the printed pattern is detected to meet the set requirement;
step eight, mounting the QFN chip by using a full-automatic chip mounter 6;
step nine, measuring a temperature formula by using a KIC furnace temperature curve tester, and automatically analyzing the curve parameter welding temperature of the formula to be 235-245 ℃;
step ten, using reflow soldering equipment 7 of an air medium to perform soldering of a temperature formula, controlling the reflow time to be 217 ℃ for 60-80 seconds, and controlling the constant temperature to be 150-190 ℃ for 100-120 seconds;
step eleven, carrying out installation detection by using an automatic optical detector, and detecting the accuracy of the actual installation coordinates;
and step twelve, performing nondestructive exploration by using an X-ray detector 8, and confirming the porosity after welding.
Has the advantages that: by using a design scheme with high-quality solder paste transfer demolding and a standardized welding curve, repeated debugging and verification can be avoided, and the problem that when a QFN (quad Flat No-lead) packaging electronic product is used in a traditional QFN lead-free welding process, the power consumption and the reliability of the product are influenced due to the fact that the welding voidage is too high can be solved.
The above embodiments are provided to further explain the objects, technical solutions and advantages of the present invention in detail, it should be understood that the above embodiments are merely exemplary embodiments of the present invention and are not intended to limit the scope of the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (7)
1. A QFN lead-free low-void-rate soldering method, comprising:
identifying the chip packaging size of the QFN, the alloy area definition and the electronic design draft of the integrated circuit board;
generating a tin paste printing transfer steel mesh design scheme according to the electronic design draft to obtain a steel mesh pattern;
detecting the integrity of the steel mesh graph by adopting a photoplotting file, confirming the graph meeting the design requirement, and obtaining a design graph;
the SAC305 solder paste No. 4 powder particles are used for environment temperature return and stirring to meet the operation conditions;
erecting and transferring the steel mesh by using a solder paste printer and positioning a visual angle to ensure accurate superposition;
printing a solder paste pattern by using a printer, transferring, mounting a scraper and filling solder paste to obtain a printing pattern;
transferring the printed pattern by using automatic 3D optical equipment, detecting, and detecting whether the volume of the printed pattern meets a set requirement;
and mounting the QFN chip by using full-automatic mounting equipment.
2. The method for QFN lead-free low-void-rate soldering as claimed in claim 1, further comprising the following steps after the QFN chip is mounted by using the fully automatic mounting equipment:
measuring a temperature formula by using a KIC furnace temperature curve tester, and automatically analyzing curve parameters of the formula;
carrying out welding implementation of a temperature formula by using reflow welding equipment of an air medium;
mounting detection is carried out by using an automatic optical detection machine, and the accuracy of the mounting coordinate is detected;
and performing nondestructive inspection by using an X-ray inspection machine, and confirming the porosity after welding.
3. The method of claim 1, wherein the solder paste printed transfer web design has a thickness of 120 um.
4. The method of claim 1, wherein the pattern design of solder paste printing transfer is a bevel multi-fillet design.
5. The method for QFN lead-free low-void-ratio soldering as claimed in claim 1, wherein the temperature range for soldering is 235-245 ℃.
6. The method for QFN lead-free low void ratio solder bonding as claimed in claim 1, wherein the reflow temperature of the solder bonding application of the temperature formula is controlled within the range of 217 degrees for 60-80 seconds.
7. The method for QFN lead-free low void ratio solder bonding as claimed in claim 1, wherein the temperature of the temperature formulation is controlled within a range of 150-190 degrees for 100-120 seconds.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210150762.4A CN114423180A (en) | 2022-02-18 | 2022-02-18 | QFN lead-free low-voidage welding method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210150762.4A CN114423180A (en) | 2022-02-18 | 2022-02-18 | QFN lead-free low-voidage welding method |
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| Publication Number | Publication Date |
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| CN114423180A true CN114423180A (en) | 2022-04-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202210150762.4A Pending CN114423180A (en) | 2022-02-18 | 2022-02-18 | QFN lead-free low-voidage welding method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116321796A (en) * | 2023-01-12 | 2023-06-23 | 成都电科星拓科技有限公司 | LGA bottom surface solder paste printing soldering-assisted packaging device and technology |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005159076A (en) * | 2003-11-27 | 2005-06-16 | Matsushita Electric Ind Co Ltd | Solder packaging method of electronic part |
| CN106643554A (en) * | 2016-12-24 | 2017-05-10 | 大连日佳电子有限公司 | Method for detecting perforation precision of steel mesh |
| CN108040436A (en) * | 2017-12-08 | 2018-05-15 | 郑州云海信息技术有限公司 | A kind of asymmetric IC pads steel mesh of PCBA and its design method |
| CN109362189A (en) * | 2018-11-16 | 2019-02-19 | 漳州市鸿源电子工业有限公司 | A kind of SMT patch packaging technology |
| CN109874237A (en) * | 2019-03-11 | 2019-06-11 | 深圳市海能达通信有限公司 | SMT welding procedure and steel mesh for SMT welding procedure |
| CN210670835U (en) * | 2019-10-12 | 2020-06-02 | 芜湖启迪半导体有限公司 | Steel mesh for solder paste printing process |
| CN111372393A (en) * | 2020-03-31 | 2020-07-03 | 佰电科技(苏州)有限公司 | QFN element mounting method for reducing welding voidage |
| CN111367261A (en) * | 2020-04-03 | 2020-07-03 | 镇江市高等专科学校 | Intelligent module and multifunctional motor controller production process based on intelligent module |
| CN113677104A (en) * | 2021-08-27 | 2021-11-19 | 中国电子科技集团公司第二十研究所 | LGA device low-void-rate welding process method |
-
2022
- 2022-02-18 CN CN202210150762.4A patent/CN114423180A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005159076A (en) * | 2003-11-27 | 2005-06-16 | Matsushita Electric Ind Co Ltd | Solder packaging method of electronic part |
| CN106643554A (en) * | 2016-12-24 | 2017-05-10 | 大连日佳电子有限公司 | Method for detecting perforation precision of steel mesh |
| CN108040436A (en) * | 2017-12-08 | 2018-05-15 | 郑州云海信息技术有限公司 | A kind of asymmetric IC pads steel mesh of PCBA and its design method |
| CN109362189A (en) * | 2018-11-16 | 2019-02-19 | 漳州市鸿源电子工业有限公司 | A kind of SMT patch packaging technology |
| CN109874237A (en) * | 2019-03-11 | 2019-06-11 | 深圳市海能达通信有限公司 | SMT welding procedure and steel mesh for SMT welding procedure |
| CN210670835U (en) * | 2019-10-12 | 2020-06-02 | 芜湖启迪半导体有限公司 | Steel mesh for solder paste printing process |
| CN111372393A (en) * | 2020-03-31 | 2020-07-03 | 佰电科技(苏州)有限公司 | QFN element mounting method for reducing welding voidage |
| CN111367261A (en) * | 2020-04-03 | 2020-07-03 | 镇江市高等专科学校 | Intelligent module and multifunctional motor controller production process based on intelligent module |
| CN113677104A (en) * | 2021-08-27 | 2021-11-19 | 中国电子科技集团公司第二十研究所 | LGA device low-void-rate welding process method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116321796A (en) * | 2023-01-12 | 2023-06-23 | 成都电科星拓科技有限公司 | LGA bottom surface solder paste printing soldering-assisted packaging device and technology |
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