CN114420195A - ODT (on-die data) calibration method, computer equipment and storage medium - Google Patents
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Abstract
The invention discloses an ODT calibration method, computer equipment and a storage medium, wherein the method comprises the following steps: acquiring an initial resistance value and a total calibration frequency; acquiring the current calibration times; determining a target resistance value of the ODT according to the initial resistance value and the current calibration times; carrying out tracing action according to the target resistance value, and recording an operation index corresponding to the target resistance value; and when the current calibration times are larger than the total calibration times, selecting a final resistance value from a plurality of target resistance values according to the operation indexes as a calibrated resistance value of the ODT. The method realizes the automatic calibration of the ODT by dynamically adjusting the ODT value, and can automatically adjust the ODT value required by the memory. Compared with the fixed ODT value, the ODT automatic calibration can effectively solve the problems of poor chip consistency, adaptation and compatibility of different memory chips on the same SoC system and the same memory chip on different SoC systems, also can improve the problem of machine halt caused by the fact that the ODT value is not set, and reduces debugging time of developers.
Description
Technical Field
The invention relates to the technical field of memory test, in particular to an ODT (on-die termination) calibration method, computer equipment and a storage medium.
Background
In the related art, a large amount of termination resistors are added on the main board of the early DDR SDRAM to prevent the data line termination from reflecting signals, which not only increases the manufacturing cost, but also the effect is not good. From the DRR2, Termination resistance has been added to the DDR particle interior, also known as ODT (On-Die Termination). However, different ODT values may need to be matched on different socs for the same DRAM chip, and different types and capacities of DRAM chips may be adapted on the same SoC, and the required ODT values also differ. Currently, there is no corresponding ODT calibration method to adjust the ODT value required for the memory.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the prior art. Therefore, the invention provides an ODT calibration method, which can automatically adjust the ODT value required by the memory by dynamically adjusting the ODT value to calibrate the ODT.
The ODT calibration method according to the embodiment of the first aspect of the invention is applied to a memory, and comprises the following steps:
acquiring an initial resistance value and a total calibration frequency;
acquiring the current calibration times;
determining a target resistance value of the ODT according to the initial resistance value and the current calibration times;
carrying out a tracing action according to the target resistance value, and recording an operation index corresponding to the target resistance value, wherein the operation index is a parameter value related to the tracing action;
and when the current calibration times are larger than the total calibration times, selecting a final resistance value from the target resistance values according to the operation index to serve as the calibrated resistance value of the ODT.
The ODT calibration method provided by the embodiment of the invention has at least the following beneficial effects: the target resistance value of the ODT is continuously changed to obtain the operation index of the Training action under different target resistance values. And selecting the final resistance value from the plurality of target resistance values through the operation index to serve as the calibrated resistance value of the ODT. The ODT value required by the memory can be automatically adjusted by dynamically adjusting the ODT value to realize automatic calibration of the ODT. Compared with the fixed ODT value, the ODT automatic calibration can effectively solve the problems of poor chip consistency, adaptation and compatibility of different memory chips on the same SoC system and the same memory chip on different SoC systems, also can improve the problem of machine halt caused by the fact that the ODT value is not set, and reduces debugging time of developers.
According to some embodiments of the invention, the determining the target resistance value of the ODT according to the initial resistance value and the current calibration number comprises:
and determining the target resistance value of the ODT according to the ratio of the initial resistance value to the current calibration times.
According to some embodiments of the invention, the determining the target resistance value of the ODT according to the initial resistance value and the current calibration number comprises:
determining a gear position value according to the current calibration times, wherein the size of the gear position value is in negative correlation with the current calibration times;
and determining a target resistance value of the ODT according to the initial resistance value and the gear value.
According to some embodiments of the invention, the obtaining the initial resistance value and the total calibration number of the preset ODT includes:
and if the memory is in a high-frequency state, enabling ODT (ODT) to acquire an initial resistance value and the total calibration times.
According to some embodiments of the invention, further comprising:
and if the memory is in a low-frequency state, closing the ODT.
According to some embodiments of the invention, the operation index is at least one of an eye width value, an eye width pass rate, and a delay.
According to some embodiments of the invention, the selecting a final resistance value from a plurality of target resistance values according to the operation index comprises:
if the operation index is the eye width value, selecting a target resistance value corresponding to the maximum eye width value from a plurality of target resistance values as a final resistance value;
if the operation index is the eye width passing rate, selecting a target resistance value corresponding to the maximum eye width passing rate from the plurality of target resistance values as a final resistance value;
and if the operation index is the delay, selecting the target resistance value corresponding to the minimum delay from the plurality of target resistance values as the final resistance value.
According to some embodiments of the invention, selecting a final resistance value from a plurality of target resistance values according to the operation index further comprises:
if the operation index is the eye width value and the eye width passing rate, selecting a first target resistance value corresponding to the maximum eye width value from the plurality of target resistance values, and selecting a second target resistance value corresponding to the maximum eye width passing rate from the plurality of first target resistance values as a final resistance value;
if the operation index is the eye width value, the eye width passing rate and the time delay, a first target resistance value corresponding to the eye width value is selected from the target resistance values, a second target resistance value corresponding to the eye width passing rate is selected from the first target resistance values, and a third target resistance value corresponding to the time delay is selected from the second target resistance values as a final resistance value.
A computer device according to an embodiment of the second aspect of the present invention comprises a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method according to any one of the embodiments of the first aspect of the present invention when executing the computer program.
A storage medium according to an embodiment of the third aspect of the present invention is a computer-readable storage medium storing computer-executable instructions for performing the method of any one of the embodiments of the first aspect of the present invention.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
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The invention is further described with reference to the following figures and examples, in which:
FIG. 1 is a flowchart of a method for ODT calibration according to an embodiment of the present invention;
FIG. 2 is a flowchart of another ODT calibration method provided by an embodiment of the invention;
FIG. 3 is a flowchart of another ODT calibration method provided by an embodiment of the invention;
FIG. 4 is a flowchart of an ODT calibration method according to an exemplary embodiment of the present invention;
FIG. 5 is a flowchart of an ODT calibration method provided by example two of the present invention;
FIG. 6 is a flowchart illustrating an ODT calibration method according to example three of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, it should be understood that the orientation or positional relationship referred to in the description of the orientation, such as the upper, lower, front, rear, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the description of the present invention, the meaning of a plurality is one or more, the meaning of a plurality is two or more, and the above, below, exceeding, etc. are understood as excluding the present numbers, and the above, below, within, etc. are understood as including the present numbers. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present invention, unless otherwise explicitly limited, terms such as arrangement, installation, connection and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific contents of the technical solutions.
In the description of the present invention, reference to the description of the terms "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
SoC: the abbreviation of System on Chip, known as System on Chip, also known as System on Chip.
A large amount of termination resistors are added to the early DDR SDRAM motherboard to prevent the data line from terminating the reflected signal, which not only increases the manufacturing cost, but also the effect is not good. From the DRR2, Termination resistance has been added to the DDR particle interior, also known as ODT (On-Die Termination). The method allows a user to control the enabling and resistance value of the terminal resistor inside the DDR by reading and writing the value of the MR register.
The ODT is used simply to allow the DQS, RDQS, DQ and DM signals to drain through the termination resistors, preventing these signals from forming reflections on the circuit, and thus enhancing signal integrity. The ODT size determines the signal ratio and reflectivity of the data line, and if the ODT size is small, the signal reflection of the data line is low but the signal-to-noise ratio is also low; if the ODT is high, the signal-to-noise ratio of the data line is high, but the signal reflection is also increased.
Different ODT values may need to be matched on different SoCs by the same DRAM chip, different types and capacities of DRAM chips may be adapted on the same SoC, and the required ODT values are different. In order to save debug time and improve compatibility, the ODT auto-calibration method is very important.
The invention mainly solves the problems of adaptation and compatibility of different DRAM chips on different SoC systems, reduces signal reflection by automatically calibrating ODT value and enhances signal integrity.
Based on this, embodiments of the present invention provide an ODT calibration method, a computer device, and a storage medium, and specifically, the ODT calibration method in the embodiments of the present invention is described first by the following embodiments.
Referring to fig. 1, the ODT calibration method according to an embodiment of the present invention includes, but is not limited to, step S110 to step S140.
Step S110, acquiring an initial resistance value and a total calibration frequency;
step S120, acquiring the current calibration times;
step S130, determining a target resistance value of the ODT according to the initial resistance value and the current calibration times;
step S140, performing a tracing action according to the target resistance value, and recording an operation index corresponding to the target resistance value, wherein the operation index is a parameter value related to the tracing action;
and step S150, when the current calibration times is larger than the total calibration times, selecting a final resistance value from a plurality of target resistance values according to the operation index as a calibrated resistance value of the ODT.
In step S110, the initial resistance value is generally 240(Ω) RZQ, and the total calibration times may be set as needed, for example, set to 5, 6, or 7, and the embodiment of the present invention is not limited in particular.
In steps S120 to S130, the target resistance of the ODT is determined according to the initial resistance and the current calibration times, and it is understood that the current calibration times gradually increase as the calibration operation proceeds. The target resistance value may be increased with the increase of the current calibration number, and may be decreased with the increase of the current calibration number. For example, the current calibration number is 2, and the target resistance value is 120(Ω); the current calibration number is 3, and the target resistance value is 80(Ω). Or, the current calibration time is 2, and the target resistance value is 48 (omega); the current calibration number is 3, and the target resistance value is 60(Ω).
In steps S140 to S150, the tracking action performed on the ODT generates a series of parameter values, and it can be judged whether the tracking action on the ODT is performed in an optimal environment by recording the parameter values. And recording the operation index corresponding to the target resistance value each time until the current calibration times are greater than the total calibration times, and finishing recording. And selecting a final resistance value from the target resistance values according to the operation index, and using the final resistance value as the calibrated resistance value of the ODT.
Through the steps of the embodiment of the invention, compared with the fixed ODT value, the ODT automatic calibration can effectively solve the problems of poor chip consistency, adaptation and compatibility of different memory chips on the same SoC system and the same memory chip on different SoC systems, and can also improve the problem of machine halt caused by the fact that the ODT value is not set, and reduce the debugging time of developers.
Referring to fig. 2, the target resistance value in step S130 may be determined by:
step S210, determining a target resistance value of the ODT according to a ratio of the initial resistance value to the current calibration number.
For example, the initial resistance value is 240 Ω, and the current calibration times are 1 to 6, the target resistance values are 240/1(Ω), 240/2(Ω), 240/3(Ω), 240/4(Ω), 240/5(Ω), and 240/6(Ω) in this order.
Referring to fig. 3, the target resistance value in step S130 may also be determined by:
step S310, determining a gear position value according to the current calibration times, wherein the size of the gear position value is in negative correlation with the current calibration times;
and step S320, determining a target resistance value of the ODT according to the initial resistance value and the gear value.
For example, the current calibration times is 1 to 6, the corresponding gear value is 6 to 1, the initial resistance value is 240(Ω), and the target resistance values determined according to the ratio of the initial resistance value to the gear value are 240/6(Ω), 240/5(Ω), 240/4(Ω), 240/3(Ω), 240/2(Ω), and 240/1(Ω) in sequence. Or, the current calibration times is 1 to 6, the corresponding shift values are 6 to 1, the initial resistance value is 240, and the target resistance values determined according to the mapping relationship between the initial resistance value and the shift values are 40(Ω), 80(Ω), 120(Ω), 160(Ω), 200(Ω) and 240(Ω) in sequence.
It is appreciated that ODT can be divided into two states, off (Disable) and Enable (Enable). If the memory is in a high frequency state, the ODT is enabled, and the initial resistance value and the total calibration times are obtained. If the memory is in a low frequency state, the ODT is turned off.
Specifically, when the memory is in a low-frequency state, the ODT is generally turned off by default, and a normal tracing action is performed; the ODT function is turned on at a high frequency and an initial resistance value and a total number of calibrations N are obtained. Generally, the initial resistance defaults to 240 Ω, and N defaults to 6.
It is understood that the operation index is at least one of an eye width value, an eye width passing rate, and a delay time. After the ODT performs tracing according to the target resistance, there are eye width values (Window Sum) of TX and RX corresponding to the target resistance, eye width passing rates of each CHN and Rank, and DQ, DQs, or DQM delay. At least one of the resistance values is recorded as an operation index, so that the final resistance value is selected according to the operation index.
It can be understood that if the operation index is the eye width value, the target resistance value corresponding to the maximum eye width value is selected from the plurality of target resistance values as the final resistance value;
if the operation index is the eye width passing rate, selecting a target resistance value corresponding to the maximum eye width passing rate from the plurality of target resistance values as a final resistance value;
and if the operation index is delay, selecting a target resistance value corresponding to the minimum delay from the plurality of target resistance values as a final resistance value.
It can also be understood that if the operation indexes are the eye width value and the passing rate, the first target resistance value corresponding to the maximum eye width value is selected from the plurality of target resistance values, and then the second target resistance value corresponding to the maximum eye width passing rate is selected from the plurality of first target resistance values as the final resistance value;
if the operation indexes are the eye width value, the eye width passing rate and the time delay, a first target resistance value corresponding to the maximum eye width value is selected from the multiple target resistance values, a second target resistance value corresponding to the maximum eye width passing rate is selected from the multiple first target resistance values, and a third target resistance value corresponding to the minimum time delay is selected from the multiple second target resistance values to serve as a final resistance value.
The ODT calibration method of the present invention is illustrated below by three practical examples.
As an example one, referring to fig. 4, in the example one, the method specifically includes:
acquiring an initial resistance value R and a total calibration frequency N;
acquiring the current calibration time A as 1;
determining a target resistance R of the ODT according to the ratio of the initial resistance to the current calibration times, wherein R is R/A;
carrying out tracing action according to the target resistance value r, and recording an operation index corresponding to the target resistance value r, wherein the operation index is a parameter value related to the tracing action, A + 1;
and when the current calibration frequency A is greater than the total calibration frequency N, selecting the final resistance value from the multiple target resistance values according to the operation index as the calibrated resistance value of the ODT. For example, if the operation index is the eye width value, the target resistance value corresponding to the maximum eye width value is selected from the plurality of target resistance values as the final resistance value; if the operation index is the eye width passing rate, selecting a target resistance value corresponding to the maximum eye width passing rate from the plurality of target resistance values as a final resistance value; and if the operation index is delay, selecting a target resistance value corresponding to the minimum delay from the plurality of target resistance values as a final resistance value.
Example two, referring to fig. 5, in example two, the method specifically includes:
acquiring an initial resistance value R and a total calibration frequency N;
acquiring the current calibration time A as 1;
determining a gear value B according to the current calibration times A, and determining a target resistance value R of the ODT according to the ratio of the initial resistance value to the gear value, wherein R is R/B;
carrying out tracing action according to the target resistance value r, and recording an operation index corresponding to the target resistance value r, wherein the operation index is a parameter value related to the tracing action, A + 1;
and when the current calibration frequency A is greater than the total calibration frequency N, selecting the final resistance value from the multiple target resistance values according to the operation index as the calibrated resistance value of the ODT. For example, if the operation index is the eye width value, the target resistance value corresponding to the maximum eye width value is selected from the plurality of target resistance values as the final resistance value; if the operation index is the eye width passing rate, selecting a target resistance value corresponding to the maximum eye width passing rate from the plurality of target resistance values as a final resistance value; and if the operation index is delay, selecting a target resistance value corresponding to the minimum delay from the plurality of target resistance values as a final resistance value.
In example three, referring to fig. 6, in example three, the method specifically includes:
when the memory is in a low-frequency state, the ODT is generally closed by default, and normal tracing action is carried out;
enabling the ODT function under the condition that the memory is in a high-frequency state, and acquiring an initial resistance value R and a total calibration frequency N;
acquiring the current calibration time A as 1;
determining a target resistance R of the ODT according to the ratio of the initial resistance to the current calibration times, wherein R is R/A;
carrying out tracing action according to the target resistance value r, and recording an operation index corresponding to the target resistance value r, wherein the operation index is a parameter value A +1 related to the tracing action;
and continuing to perform the next Training action according to the A, and when the current calibration time A is greater than the total calibration time N, selecting the final resistance value from the target resistance values according to the operation index to serve as the calibrated resistance value of the ODT. For example, if the operation index is the eye width value, the target resistance value corresponding to the maximum eye width value is selected from the plurality of target resistance values as the final resistance value; if the operation index is the eye width passing rate, selecting a target resistance value corresponding to the maximum eye width passing rate from the plurality of target resistance values as a final resistance value; and if the operation index is delay, selecting a target resistance value corresponding to the minimum delay from the plurality of target resistance values as a final resistance value. The final resistance value is written to the corresponding MR register.
Furthermore, an embodiment of the present invention also provides a storage medium, which is a computer-readable storage medium storing computer-executable instructions for execution by one or more control processors, the one or more control processors executing the method in the above-described method embodiment, for example, executing the above-described method steps S110 to S150 in fig. 1, the method step S210 in fig. 2, and the method steps S310 to S320 in fig. 3.
The above-described embodiments of the apparatus are merely illustrative, and the units illustrated as separate components may or may not be physically separate, may be located in one place, or may be distributed over a plurality of network nodes. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
The embodiments described in the embodiments of the present disclosure are for more clearly illustrating the technical solutions of the embodiments of the present disclosure, and do not constitute a limitation to the technical solutions provided in the embodiments of the present disclosure, and it is obvious to those skilled in the art that the technical solutions provided in the embodiments of the present disclosure are also applicable to similar technical problems with the evolution of technology and the emergence of new application scenarios.
Those skilled in the art will appreciate that the embodiments shown in the examples are not intended to limit the embodiments of the present disclosure, and may include more or less steps than those shown, or some of the steps may be combined, or different steps may be included.
One of ordinary skill in the art will appreciate that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof.
The terms "first," "second," "third," "fourth," and the like in the description of the application and the above-described figures, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be understood that in the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" for describing an association relationship of associated objects, indicating that there may be three relationships, e.g., "a and/or B" may indicate: only A, only B and both A and B are present, wherein A and B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of single item(s) or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
One of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer readable storage media (or non-transitory media) and communication media (or transitory media). The term computer-readable storage medium includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer-readable storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention. Furthermore, the embodiments of the present invention and the features of the embodiments may be combined with each other without conflict.
Claims (10)
1. An ODT calibration method, applied to a memory, the method comprising:
acquiring an initial resistance value and a total calibration frequency;
acquiring the current calibration times;
determining a target resistance value of the ODT according to the initial resistance value and the current calibration times;
carrying out a tracing action according to the target resistance value, and recording an operation index corresponding to the target resistance value, wherein the operation index is a parameter value related to the tracing action;
and when the current calibration times are larger than the total calibration times, selecting a final resistance value from the target resistance values according to the operation index to serve as the calibrated resistance value of the ODT.
2. The ODT calibration method of claim 1, wherein determining the target ODT resistance based on the initial resistance and the current calibration number comprises:
and determining the target resistance value of the ODT according to the ratio of the initial resistance value to the current calibration times.
3. The ODT calibration method of claim 1, wherein determining the target ODT resistance based on the initial resistance and the current calibration number comprises:
determining a gear position value according to the current calibration times, wherein the size of the gear position value is in negative correlation with the current calibration times;
and determining a target resistance value of the ODT according to the initial resistance value and the gear value.
4. The ODT calibration method of claim 1, wherein obtaining the initial resistance and the total number of calibrations for the predetermined ODT comprises:
and if the memory is in a high-frequency state, enabling ODT (ODT) to acquire an initial resistance value and the total calibration times.
5. The method of claim 4, further comprising:
and if the memory is in a low-frequency state, closing the ODT.
6. The method of claim 1, wherein the performance metric is at least one of an eye width value, an eye width pass rate, and a latency.
7. The method of claim 6, wherein selecting the final resistance value from the plurality of target resistance values based on the performance metric comprises:
if the operation index is the eye width value, selecting a target resistance value corresponding to the maximum eye width value from a plurality of target resistance values as a final resistance value;
if the operation index is the eye width passing rate, selecting a target resistance value corresponding to the maximum eye width passing rate from the plurality of target resistance values as a final resistance value;
and if the operation index is the delay, selecting the target resistance value corresponding to the minimum delay from the plurality of target resistance values as the final resistance value.
8. The method of claim 7, wherein selecting the final resistance value from the plurality of target resistance values based on the performance metric further comprises:
if the operation index is the eye width value and the eye width passing rate, selecting a first target resistance value corresponding to the maximum eye width value from the plurality of target resistance values, and selecting a second target resistance value corresponding to the maximum eye width passing rate from the plurality of first target resistance values as a final resistance value;
if the operation index is the eye width value, the eye width passing rate and the time delay, a first target resistance value corresponding to the eye width value is selected from the target resistance values, a second target resistance value corresponding to the eye width passing rate is selected from the first target resistance values, and a third target resistance value corresponding to the time delay is selected from the second target resistance values as a final resistance value.
9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method of any one of claims 1 to 8 when executing the computer program.
10. A storage medium, being a computer-readable storage medium, characterized by computer-executable instructions stored thereon for performing the method of any one of claims 1 to 8.
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