CN111564175A

CN111564175A - Impedance configuration method of memory interface and computer readable storage medium

Info

Publication number: CN111564175A
Application number: CN201910211851.3A
Authority: CN
Inventors: 宋威良; 张启彬
Original assignee: Silicon Motion Inc
Current assignee: Silicon Motion Inc
Priority date: 2019-02-13
Filing date: 2019-03-20
Publication date: 2020-08-21
Anticipated expiration: 2039-03-20
Also published as: CN111564175B; TW202030728A; TWI701661B; TW202030603A; TW202030601A; TWI694378B; TWI740461B; CN111563011A

Abstract

The invention provides an impedance configuration method of a memory interface, which is executed by a processing unit and comprises the following steps: setting a first resistance value of the on-chip termination resistance associated with the first receiver to a first default resistance value; setting a second resistance value of the driving variable resistor associated with the second transmitter to a second default resistance value; performing tests for a plurality of test combinations, wherein each combination includes a third resistance value associated with the driving variable resistor of the first transmitter and a fourth resistance value associated with the on-chip termination resistor of the second receiver; and storing the test result of each test combination to a specific position of the static random access memory, so that the calibration host can obtain the test result of each test combination from the static random access memory and determine the impedance setting of the memory interface according to the test result.

Description

Impedance configuration method of memory interface and computer readable storage medium

Technical Field

The present invention relates to communication interfaces, and more particularly, to a method for configuring an impedance of a memory interface and a computer readable storage medium.

Background

After the speed of a bus of a Dynamic Random Access Memory (DRAM) reaches a high transmission rate, e.g., 500Mb/s or higher, system-level signal transmission and reception problems may occur, e.g., reflections may occur from the pin-lines of connected peer devices, e.g., controllers, DRAM modules, etc. The signal transmission and reception problem can be solved by a calibration Driver (Driver) and an On-Die Termination (ODT). Therefore, the present invention provides a configuration method of a memory interface and a computer readable storage medium for calibrating a termination resistor in a driver and a chip in the memory interface.

Disclosure of Invention

In view of the above, how to reduce or eliminate the above-mentioned deficiencies in the related art is a problem to be solved.

The invention provides an impedance configuration method of a memory interface, which is executed by a processing unit and comprises the following steps: setting a first resistance value of the on-chip termination resistance associated with the first receiver to a first default resistance value; setting a second resistance value of the driving variable resistor associated with the second transmitter to a second default resistance value; performing tests for a plurality of test combinations, wherein each combination includes a third resistance value associated with the driving variable resistor of the first transmitter and a fourth resistance value associated with the on-chip termination resistor of the second receiver; and storing the test result of each test combination to a specific position of the static random access memory, so that the calibration host can obtain the test result of each test combination from the static random access memory and determine the impedance setting of the memory interface according to the test result. The processing unit is coupled to a memory interface, the SRAM and a calibration interface, the memory interface is coupled to a memory device and includes the first transmitter and the first receiver, and the memory device includes the second transmitter and the second receiver.

The invention also provides a computer-readable storage medium of an impedance configuration of a memory interface for storing a computer program executable by a processing unit, and the computer program, when executed by the processing unit, implements the method described above.

One of the advantages of the above embodiments is that the test results of each test combination provided to the calibration host enable the calibration host to determine the impedance setting of the memory interface accordingly.

Other advantages of the present invention will be explained in more detail in conjunction with the following description and the accompanying drawings.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application.

FIG. 1 is a diagram of a calibration system according to an embodiment of the invention.

FIG. 2 is a block diagram of a calibration system according to an embodiment of the invention.

FIG. 3 is a graphical user interface of an impedance configuration of a memory interface according to an embodiment of the invention.

FIG. 4 is a flowchart illustrating a method for training a transmitter and a receiver in a memory interface according to an embodiment of the invention.

FIG. 5 is an initial data representation of write training for DDR4DRAM, in accordance with an embodiment of the present invention.

FIG. 6 is an initial data representation of read training for DDR4DRAM according to an embodiment of the invention.

FIG. 7 is a flowchart of a method for write and read training according to an embodiment of the present invention.

FIG. 8 shows exemplary results of write training for DDR4 DRAMs, in accordance with embodiments of the invention. FIG. 9 is a flowchart of a method of write training according to an embodiment of the present invention.

[ List of reference numerals ]

130 base plate

110 calibration host

115 processing unit

150 controller

170 memory device

190 display

210 processing unit

230 static random access memory

250 calibration interface

270 memory interface

271 physical layer

273 ODT shift register

275 drive notch register

277 MAC layer

290 direct memory access controller

300 graphical user interface for memory calibration

310 display the box

330 selection button

335 selection menu

350 test progress Box

370 start button

390 test information Box

Method steps S410 to S470

Method steps S711-S790

800 Box for defining normally operable resistance settings

Intermediate resistance values associated with 800a

Method steps S910 to S970

Detailed Description

Embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, the same reference numerals indicate the same or similar components or process flows.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of further features, integers, steps, operations, elements, components, and/or groups thereof.

The use of terms such as "first," "second," "third," and the like in the description of the invention is used for modifying the elements in the claims, and is not intended to indicate a priority order, precedence relationship, or chronological order in which one element precedes another element or in which method steps are performed, but rather to distinguish between elements having the same name.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe relationships between components may be similarly interpreted, such as "between" and "directly between," or "adjacent" and "directly adjacent," etc.

Referring to fig. 1, the controller 150 and the memory device 170 may be mounted (mount) on the substrate 130, and the controller 150 may be coupled or connected to the memory device 170 through the substrate 130. Memory device 370 may be a Dynamic Random Access Memory (DRAM, etc.). The calibration host 110 is coupled to the controller 150 for issuing a command requesting the controller 150 to perform an impedance test method, then reading the test result from the controller 150 and displaying the test result on the display 190, so that an engineer can determine impedance Configurations (Configurations) in the interfaces of the controller 150 and the memory device 170 according to the test result. Alternatively, in other embodiments, the calibration host 110 may execute an application program for interpreting the test results and automatically determining the impedance settings in the interface between the controller 150 and the memory device 170 according to an algorithm. Then, the calibration host 110 may issue a command and determine an impedance setting, requesting the controller 150 to execute an impedance setting method of the memory interface. When the processing unit 210 in the controller 150 loads and executes the firmware or software program code related to the impedance setting method of the memory interface, the determined impedance setting is written into the nonvolatile memory space in the controller 150 and the memory device 170 as a factory setting value.

Referring to fig. 2, the controller 150 includes a processing unit 210, which may be implemented in various ways, such as using general purpose hardware (e.g., a single processor, a plurality of processors with parallel processing capability, a graphics processor, or other processor with computing capability), and provides the functions described below when executing software and/or firmware instructions of a Mass Production Integrated System Program (mpips). The controller 150 may include a calibration interface 250, such as an I2C interface, for the calibration host 110 to send commands to the processing unit 210 through the calibration interface 250 to initiate and execute the impedance testing and setting method of the memory interface. After the calibration is completed, the calibration host 110 may request a Direct Memory Access Controller (Direct Memory Access DMA Controller) to read a test result from a default local read test of a Static random Access Memory (Static random Access SRAM)230 through the calibration interface 250. The mpips may be stored in a Read Only Memory (ROM) of the controller 150 at the time of factory shipment, or may be transmitted to the controller 150 by the test host 110 through the calibration interface 250 or other interface before calibration is started.

In some embodiments, the controller 170 may also be referred to as an Application-Specific Integrated Circuit ASIC-side (ASIC-side), and the memory device 170 may be a DRAM, referred to as a DRAM side, for caching data, such as variables, tables, etc., and various user data, required in executing software and firmware instructions. Memory interface 270 may communicate with DRAMs using a Double Data Rate (DDR) communication protocol, such as a third generation Double Data Rate (DDR3), Low Power DDR3(Low Power LPDDR3), fourth generation Double Data Rate (DDR4), or other interface. The input and output signals between the memory interface 270 and the DRAMs may include reset, CK _ N, CKE, ODT, CS _ N, ACT _ N, BG, BA, A, DM, DQS _ N, DQ _ lower, DQ _ upper, etc.

The memory interface 470 may include a Physical Layer (PHY) 471 with circuitry connected to the memory device 370. The DDR communication protocol and associated physical layer 471 provide communication capabilities for transferring commands, addresses, and data to and from memory device 370. The physical layer 471 includes a Transmitter (Transmitter) and a Receiver (Receiver) for respectively transmitting signals to and receiving signals from the Receiver of the memory device 370. The output terminal of the transmitter (also referred to as Driver) may be connected to a Variable resistor (referred to as Driving Variable resistor), so that the processing unit 210 may adjust the Resistance of the Driving Variable resistor by changing the setting of the Driving-stage Register (Driving-stage Register)275, thereby changing the Driving Strength (Driving Strength) of the output. On the other hand, a variable resistor (may be referred to as an ODT variable resistor) may be connected to an input terminal of the receiver, so that the processing unit 210 may adjust an Impedance (Impedance) of the ODT variable resistor by changing a setting of an On-chip termination ODT-stage Register (On-die termination) 275.

Drive notch register 275 may store a 4-bit value as shown in table 1:

TABLE 1

Value (decimal)	Z target (ohms)
		0	480
1	240
		2	160
3	120
		4	96
5	80
		6	68.6
7	60
		8	53.3
9	48
		10	43.6
11	40
		12	36.9
13	34.3
		14	32
15	30

For example, when the value stored in the driving range register 275 is set to 0, the resistance of the driving variable resistor is adjusted to 480 ohm. When the value stored in the drive position register 275 is set to 1, the resistance value of the drive variable resistor is adjusted to 240 ohm. The resistance change of the other setting pairs driving the variable resistor can be analogized, and the description is omitted for simplicity.

ODT range register 273 may store a value of 4 bits, as shown in table 2:

TABLE 2

For example, when the value stored in the ODT range register 273 is set to 2, the resistance value of the driving variable resistor is adjusted to 120 ohm. The change in resistance of the ODT variable resistor for the remaining settings may be analogized and will not be described again for brevity.

In contrast, memory device 170 may also include a variable resistance setting similar to that used to vary output drive strength and ODT impedance. Processing unit 210 may instruct MAC layer 277 to send commands to memory device 170 through physical layer 271 for changing the output drive strength of the transmitter and the ODT resistance of the receiver in memory device 170.

When memory interface 470 communicates with memory device 170 using the DDR3 communication protocol, processing unit 210 may instruct MAC layer 277 to send an output/input Configuration Command (I/O Configuration Command) and set values to memory device 170 through physical layer 271. Memory interface 470 may instruct memory device 170 to adjust the resistance of the driving variable resistor therein to a specific level via signals A5 and A1, as shown in Table 3:

TABLE 3

A5	A1	Output driver resistance
			0	0	RZQ/6
0	1	RZQ/7
			1	0	Reserved
1	1	Reserved

Those skilled in the art understand that RZQ is 240 ohm. For example, when the A5 and A1 signals are both 0, the memory device 170 adjusts the resistance of the driving variable resistor to 40ohm (i.e., RZQ/6). When the signals A5 and A1 are 1 and 0 (hold set values), respectively, the memory device 170 may not change the resistance of the driving variable resistor. The remaining settings may be similar to the resistance changes of the driving variable resistor in the memory device 170, and the description is omitted for brevity. In addition, the memory interface 470 may instruct the memory device 170 to adjust the resistance of the ODT variable resistor therein to a specific level through the a9, a6, and a2 signals, as shown in table 4:

TABLE 4

A9	A6	A2	Rtt_Nom
				0	0	0	Is not enabled
0	0	1	RZQ/4
				0	1	0	RZQ/2
0	1	1	RZQ/6
				1	0	0	RZQ/12
1	0	1	RZQ/8
				1	1	0	Retention
1	1	1	Retention

For example, when the a9, a6, and a2 signals are all 0, memory device 170 may not enable ODT. When the A9, A6, and A2 signals are 0, and 1, respectively, memory device 170 may adjust the ODT variable resistor to a value of 60ohms (i.e., RZQ/4). When the a9, a6, and a2 signals are 1, and 0 (hold setting), respectively, the memory device 170 may not change the resistance of the driving variable resistor. The remaining settings may be analogized to the change in resistance of the ODT variable resistor in memory device 170 and will not be described again for brevity.

When memory interface 470 communicates with memory device 170 using the DDR4 communication protocol, processing unit 210 may instruct MAC layer 277 to send output and input configuration commands and settings to memory device 170 through physical layer 271. Memory interface 470 may instruct memory device 170 to adjust the resistance of the driving variable resistor therein to a specific level via signals A5 and A1, as shown in Table 5:

TABLE 5

The details of the resistance change of the driving variable resistor described in table 5 can refer to the description in table 3, and are not repeated for brevity. In addition, the memory interface 470 may instruct the memory device 170 to adjust the resistance of the ODT variable resistor therein to a specific level through the a9, a6, and a2 signals, as shown in table 6:

TABLE 6

A9	A6	A2	ODT resistance value
				0	0	0	Is not enabled
0	0	1	RZQ/4
				0	1	0	RZQ/2
0	1	1	RZQ/6
				1	0	0	RZQ/1
1	0	1	RZQ/5
				1	1	0	RZQ/3
1	1	1	RZQ/7

The details of the resistance change of the ODT variable resistor described in table 6 can be referred to the description of table 4, and are not repeated for brevity.

When the memory interface 470 communicates with the memory device 170 using the LPDDR3 communication protocol, the processing unit 210 may instruct the MAC layer 277 to send a mode register Write Command (mode register Write Command) and a setting value to the memory device 170 through the physical layer 271. The memory interface 470 may instruct the memory device 170 to perform an input-output Configuration (I/O Configuration) by writing "03H" to MA [7:0] in the mode register, and writing a specific value to OP <3:0> in the mode register instructs the memory device 170 to adjust the resistance value of the driving variable resistor therein to a specific level, as shown in Table 7:

TABLE 7

For example, when Op <3:0> in the mode register is written to "0010" (default), the memory device 170 will adjust the resistance value of the drive variable resistor to 34.3ohm (i.e., RZQ/6). When Op <3:0> in the mode register is written to "1001," the memory device 170 adjusts the pull-down resistance to 34.3 ohms, the pull-up resistance to 40 ohms, and the termination resistance to 240 ohms driving the variable resistor. When Op <3:0> in the mode register is written to "0000" (holding the set value) or other values not listed in table 7, the memory device 170 may not change the resistance value of the driving variable resistor. The remaining settings may be similar to the resistance changes of the driving variable resistor in the memory device 170, and the description is omitted for brevity.

Further, the memory interface 470 may instruct the memory device 170 to perform ODT control by writing "0 BH" to MA [7:0] in the mode register, and writing a specific value to OP <1:0> in the mode register instructs the memory device 170 to adjust the resistance value of the ODT variable resistor therein to a specific level, as shown in table 8:

TABLE 8

Op<1:0>	ODT resistance value
		00	Not enabled (default)
01	Retention
		10	RZQ/2
11	RZQ/1

For example, when Op <1:0> in the mode register writes "00" (the default value), the memory device 170 may not enable ODT. When Op <1:0> in the mode register writes "01" (the set value is reserved), the memory device 170 may not change the resistance value of the ODT variable resistor. When Op <1:0> in the mode register is written to "10," the memory device 170 adjusts the resistance of the ODT variable resistor to 120ohm (i.e., RZQ/2). The remaining settings may be analogized to the change in resistance of the ODT variable resistor in memory device 170 and will not be described again for brevity.

The processing unit 115 in the calibration host 110 may execute a calibration tool that may provide a man-machine interface to facilitate an engineer configuring the impedance of the memory interface. The display 190 displays a graphical user interface (hereinafter referred to as a calibration GUI)300 for memory calibration as shown in FIG. 3. The calibration GUI 300 may provide a selection button 330. When the user clicks the selection button 330, the processing unit 115 may execute a click Event Handler (On _ click () Event Handler) of the selection button 330 for displaying a selection menu 335 On the display 190 containing a plurality of items, each associated with an MPISP, such as DRAM MPISP, stored in the read only memory of the controller 150. Display box 310 may display the MPISP that the user decides by operating selection menu 335. The calibration GUI 300 may additionally provide a start button 370. When the user clicks the start button 370, the processing unit 115 of the calibration host 110 may execute a click event handler of the start button 330 for instructing the processing unit 210 of the controller 150 to load and execute the user-determined mpips through the calibration interface 250. The calibration host 110 can continuously obtain the test results of the memory interface 270 and the transceiver in the memory device 170 through the calibration interface 250 and the dma controller 290, and can update the contents of the test progress block 350 and the calibration information block 390 accordingly.

The process flow shown in fig. 4 may be implemented when the processing unit 210 loads and executes the designated mpips. After initializing memory device 170, processing unit 210 may execute the instructions of function vInitDramZQRemapIdx () to initialize a data table for storing test results. (step S410). Next, the processing unit 210 may execute the instruction of the function vsscandreamwindow (wrtraining) to perform Write-Training (step S430), and execute the instruction of the function vsscandreamwindow (rdtraining) to perform Read-Training (step S450). It should be noted that although the embodiment uses a single function program code, and uses different input parameters "WrTraining" and "RdTraining" to implement the memory write and read training, those skilled in the art can implement the memory write and read training with different functions. In other embodiments, processing unit 210 may perform memory read training first, followed by memory write training. In other embodiments, processing unit 210 may not perform memory read training and directly set the ODT of the receiver of controller 150 and the impedance in the drive variable resistance of the transmitter of memory device 170 for memory reads to default values (e.g., intermediate gear). Finally, the test result is provided to a Static Random Access Memory (SRAM) 230 (step S470).

In step S410, the processing unit 210 initializes different data tables for the write and read training respectively for recording the subsequent test results. Taking DRAM as an example: write to training data table contains two axes: one axis is arranged from weak to strong or from strong to weak in relation to the signal intensity of the ODT at the DRAM terminal; the other axis is associated with the ASIC side drive signal strength, ranging from weak to strong or from strong to weak. Reading the training data table comprises two axes: one axis is related to the driving signal intensity of the DRAM end and is arranged from weak to strong or from strong to weak; the other axis relates to the signal strength of the ODT at the ASIC end and is arranged from weak to strong or from strong to weak. The purpose of the write training is to optimize the resistance matching between the variable resistor and the DRAM terminal ODT at the ASIC terminal, and the purpose of the read training is to optimize the resistance matching between the variable resistor and the ASIC terminal ODT at the DRAM terminal. Such Remapping may help engineers or application algorithms interpret and more efficiently find the appropriate resistance range. The initialized data table may be stored in the SRAM 230.

Taking DDR4DRAM as an example: referring to fig. 5, for convenience of interpretation by an engineer or application program, the Size (Size) of the written training data table is 16 × 16 bytes, each of which records the test result when the driving variable resistor of the ASIC terminal is set to a first resistance value and the ODT of the DRAM terminal is set to a second resistance value. The data table Cells (Cells) are conceptually divided into groups of 16 bytes each. For example, when the driving variable resistor of the ASIC terminal is set to a specific resistance value (e.g., 480ohm), the test result of changing the ODT resistance value of the DRAM terminal from high to low (e.g., from not enabling ODT to setting the ODT resistance value to RZQ/7) is obtained. Alternatively, when the ODT resistance value of the DRAM side is set to a specific resistance value (RZQ/1), the test result of changing the resistance value of the driving variable resistor of the ASIC side from high to low (e.g., from 480ohm to 30ohm) is obtained. Since the ODT range of the DDR4DRAM is only 8, the values of 0h to 7h of the cells associated with each specific resistance value (i.e., each row) of the driving variable resistor of the ASIC terminal are initially "0 x 00", and the values of 8h to Fh of the cells are initially "0 x 05" (which may be called ignore values) to tell an engineer or application that the test result is negligible.

Taking DDR4DRAM as an example: referring to fig. 6, for convenience of interpretation by an engineer or an application program, the read training data table has a capacity of 16 × 16 bytes, each of which records a test result when the driving variable resistor of the DRAM terminal is set to a first resistance value and the ODT of the ASIC terminal is set to a second resistance value. The data table's cells may be conceptually divided into groups of 16 bytes each. For example, when the driving variable resistor of the DRAM terminal is set to a specific resistance (e.g., RZQ/5), the ODT resistance of the ASIC terminal is changed from high to low (e.g., from 120ohm to 40 ohm). Alternatively, when the ODT resistance value of the ASIC terminal is set to a specific resistance value (120ohm), the test result of changing the resistance value of the driving variable resistor of the DRAM terminal (e.g., from RZQ/5 to RZQ/7) from high to low. Since the driving rank of the DDR4DRAM has only 2 files, the values of the cells of 0h to 1h associated with each specific resistance value (i.e., each horizontal row) of the ASIC terminal ODT are initially "0 x 00", and the values of the cells of 2h to Fh are initially "0 x 05". Those skilled in the art may change the neglected value to any value between "0 x 05" to "0 xFF", and the present invention is not limited thereby.

In some embodiments, the details of the write training in step S430 may refer to a flowchart of the method as shown in fig. 9. The method is implemented by the processing unit 210 when loading and executing the program code of the software or firmware module, and comprises the following steps: setting the resistance value of the ODT of the receiver associated with the ASIC terminal as a default resistance value (step S910), setting the resistance value of the driving variable resistor associated with the transmitter of the device terminal as a default resistance value (step S930), and testing for a plurality of different test combinations according to the scan order, wherein each test combination includes the resistance value of the driving variable resistor associated with the transmitter of the ASIC terminal and the resistance value of the ODT of the receiver associated with the device terminal (step S950); and storing the test result of each test combination to a specific location of the SRAM 230, so that the calibration host 110 can retrieve the test result of each test combination from the SRAM 230 through the calibration interface 250 (step S970). For details of the scan sequence, the test combination, the test procedure and the test results, reference may be made to the description in the following paragraphs.

In other embodiments, the training details of steps S430 and S450 may be referred to the flowchart of the method shown in fig. 7. Whether the memory write or read training is performed, the whole process is repeated (steps S711 to S790) until all the resistance values of the ASIC and device terminals are tested (i.e., scanned) (yes in step S790). The details of the execution of the write training and the read training are described below:

when the write training is determined (yes in step S711), the processing unit 210 may determine the resistances of the ODT of the ASIC terminal and the driving variable resistor of the device terminal as default resistances, and determine the resistance steps of the ODT of the device terminal and the driving variable resistor of the ASIC terminal according to the scanning sequence (step S713). Taking DDR4DRAM as an example, the default resistance of the ODT resistance of the ASIC terminal may be 60ohms in table 2, and the default resistance of the driving variable resistor resistance of the device terminal may be RZQ/5 in table 5. Regarding the scanning sequence, for example, referring to fig. 5, the processing unit 210 may fix the ODT resistance of the device terminal in a specific gear, and then sequentially change the resistance of the driving variable resistor of the ASIC terminal from 480ohm to 30 ohm. And after all the resistance values of the driving variable resistor at the ASIC end are tested, fixing the ODT resistance value at the device end at the next gear and continuing the test. Next, the memory device is initialized (step S730). Taking DDR4DRAM as an example, in step S730, the processing unit 410 may change the value of the ODT range register 273 to the default resistance value determined in step S713, and change the driving range register 275 to the range determined in step S713 according to the scanning order. In addition, the processing unit 410 may instruct the MAC layer 277 to transmit an input/output configuration command and set values to the memory device 170 through the physical layer 271 for setting the resistance value of the driving variable resistor of the memory device 170 to the default resistance value determined in step S713, and setting the ODT resistance value of the memory device 170 to the rank determined according to the scan order in step S713. The memory space of the memory device 170 includes a small test-portion, and in step S730, the memory device 170 can perform a test-write-then-read (test-write-then-read) process on the test-portion, which may be referred to as device-side self-training. The memory device 170 may send the device-side self-training information to the processing unit 210 through the memory interface 270. When the device-side self-training does not pass (no in step S751), the processing unit 210 may store "0 x 01" to the corresponding cell written in the training data table as the test result (step S773).

To improve the reliability of the test, when the device side self-trains through (yes path in step S751), the processing unit 210 may further perform a random read/write test (step S753). In the Random read/write test, the processing unit 210 may instruct the MAC layer 277 to write 8MB of Data in a Random Data Pattern (Random Data Pattern) to the memory device 170, and then instruct the MAC layer 277 to read back the Data from the memory device 170, and check whether the read-back Data is consistent with the previously written Data. The processing unit 210 stores the test result into the corresponding storage cell written in the training data table according to the execution condition of the random read-write test (step S773). In detail, when a Read Timeout (Read Timeout) occurs, the processing unit 210 may store "0 x 02" to the corresponding cell in the write training data table. When the read back data is inconsistent with the previously written data, processing unit 210 may store "0 x 03" to the corresponding storage cell in the write training data table. When a Write Timeout (Write Timeout) occurs, the processing unit 210 may store "0 x 04" to the corresponding cell in the Write training data table. When the data read back is consistent with that previously written, processing unit 210 may store "0 x 00" to the corresponding memory cell in the write training data table, or in other embodiments, may not store any data to the write training data table because the corresponding memory cell was already initially "0 x 00".

When the determination is that the read training is performed (no in step S711), the processing unit 210 may determine the resistance values of the driving variable resistor of the ASIC terminal and the device terminal ODT as default resistance values, and determine the resistance value steps of the driving variable resistor of the device terminal and the ASIC terminal ODT according to the scanning sequence (step S715). Taking DDR4DRAM as an example, the default resistance of the driving variable resistor on the ASIC side may be 60ohms in table 1, and the default resistance of the ODT on the device side may be RZQ/4 in table 6. For example, referring to fig. 6, the processing unit 210 may fix the resistance of the driving variable resistor at the device end to a specific gear, and then sequentially change the ODT resistance at the ASIC end from 120ohm to 40 ohm. And after all the ODT resistance values of the ASIC end are tested, fixing the resistance value of the driving variable resistor of the device end at the next gear and continuing the test. Next, the memory device is initialized (step S730). For details of the step S730, reference may be made to the above description, and details are not repeated for brevity. When the device-side self-training passes (yes path in step S751), the processing unit 210 may further perform a random read/write test (step S753). The details of the step S753 can be referred to the description of the above paragraphs, which are not described again for brevity. Next, the processing unit 210 stores the test result into the corresponding cell in the read training data table according to the execution condition of the random read/write test (step S775). In detail, when the read timeout occurs, the processing unit 210 may store "0 x 02" to the corresponding storage cell in the read training data table. When the read back data is inconsistent with the previously written data, processing unit 210 may store "0 x 03" to the corresponding storage cell in the read training data table. When a write timeout occurs, the processing unit 210 may store "0 x 04" to the corresponding storage cell in the read training data table. When the read back data is consistent with the previously written data, processing unit 210 may store "0 x 00" to the corresponding cell in the read training data table, or in other embodiments, may not store any data to the read training data table because the corresponding cell was already initially "0 x 00".

It will be appreciated that the more types of errors that are recorded in the memory cells may be useful to an engineer or a program application executed by the processing unit 115 to diagnose an impedance matching problem with a particular setting.

In step S470, the processing unit 115 of the calibration host 110 can drive the direct memory access controller 290 through the calibration interface 250 to read the contents of a specific part of the SRAM 230 as a basis for configuring the transceiver of the memory interface. The read content may be displayed on a display 190 for reference by an engineer during configuration. Referring to the example result shown in FIG. 8, when the engineer or the processing unit 115 executes the application program, it can be seen that the memory interface 270 can operate normally when the values of the ASIC driver varactors range from 60ohm to 36.9ohm and the ODT values range from RZQ/1 to RZQ/5 (as shown in the dashed box 800). When executing the application program, the engineer or the processing unit 115 may write the shift positions of the driving variable resistor and ODT resistance values of the ASIC terminal and the shift positions of the driving variable resistor and ODT resistance values of the device terminal, which are associated with the intermediate value 800a in the normal local area 800, into the nonvolatile memory space in the controller 150 as factory settings.

All or a portion of the steps of the methods described herein may be implemented in a computer program, such as the operating system of a computer, a driver for specific hardware in a computer, or a software program. In addition, other types of programs as shown above may also be implemented. Those skilled in the art can write the method of the embodiment of the present invention as a computer program, and will not be described again for the sake of brevity. The computer program implemented according to the embodiments of the present invention can be stored in a suitable computer readable data carrier, such as a DVD, a CD-ROM, a USB disk, a hard disk, or can be disposed in a network server accessible via a network (e.g., the internet, or other suitable carrier).

Although the components described above are included in fig. 2, it is not excluded that more additional components may be used to achieve better technical results without departing from the spirit of the invention. Further, although the flowcharts of fig. 4, 7 and 9 are executed in a designated order, those skilled in the art can modify the order of the steps without departing from the spirit of the invention to achieve the same effect, and therefore, the present invention is not limited to the order of only the steps as described above. In addition, one skilled in the art may integrate several steps into one step, or perform more steps in sequence or in parallel besides the steps, and the present invention is not limited thereby.

While the present invention has been illustrated by the above examples, it is noted that these descriptions are not intended to limit the present invention. Rather, this invention encompasses modifications and similar arrangements as would be apparent to one skilled in the art. Therefore, the protection scope of the present application shall be subject to the scope defined by the claims.

Claims

1. A method for configuring impedance of a memory interface, the method implemented by a processing unit when loading and executing program code of a software or firmware module, wherein the processing unit is coupled to a memory interface, a static random access memory and a calibration interface, the memory interface is coupled to a memory device and comprises a first transmitter and a first receiver, the memory device comprises a second transmitter and a second receiver, the method comprising:

setting a first resistance value of a termination resistance within a chip associated with the first receiver to a first default resistance value;

setting a second resistance value of a driving variable resistor associated with the second transmitter to a second default resistance value;

performing a test for a plurality of first test combinations, wherein each of the first test combinations comprises a third resistance value and a fourth resistance value, the third resistance value being associated with a driving variable resistor of the first transmitter, and the fourth resistance value being associated with an on-chip termination resistor of the second receiver; and

storing the test result of each of the first test combinations to a specific location of the SRAM, so that the calibration host can obtain the test result of each of the first test combinations from the SRAM through the calibration interface.

2. The method of configuring impedances for a memory interface of claim 1, comprising:

receiving a command and an impedance setting from the calibration host, wherein the impedance setting is determined by the calibration host according to the test result of the first test combination; and

and writing the impedance setting into a nonvolatile storage space of a controller and the memory device as a factory setting value, wherein the controller comprises the processing unit.

3. The method according to any one of claims 1 or 2, wherein the test result of the first test combination is stored in a data table, the data table comprises a first axis and a second axis, the first axis is arranged from weak to strong or from strong to weak in relation to the signal strength of the on-chip termination resistance of the memory device, and the second axis is arranged from weak to strong or from strong to weak in relation to the driving signal strength of the memory interface.

4. The method as claimed in claim 3, wherein the data table comprises a plurality of bytes, each of the bytes recording a test result when the driving variable resistor of the memory interface is set to a fifth resistance value and the on-chip termination resistor of the memory device is set to a sixth resistance value.

5. The method as claimed in claim 4, wherein the byte is the first value indicating that the memory device fails to perform the read-test and write-test in the test portion of the memory space.

6. The method as claimed in claim 4, wherein the byte is a second value indicating that a read timeout occurs when the processing unit instructs the memory interface to perform a random read/write test; when the byte is a third value, the processing unit indicates that the write-in timeout occurs when the memory interface executes the random read-write test; and when the byte is a fourth value, the read-back data is inconsistent with the previously written data when the processing unit instructs the memory interface to execute the random read-write test.

7. The method of configuring impedances for a memory interface of claim 1, comprising:

setting a fifth resistance value of the on-chip termination resistance associated with the second receiver to a third default resistance value;

setting a sixth resistance value of the driving variable resistor associated with the first transmitter to a fourth default resistance value;

performing a test for a plurality of second test combinations, wherein each of the second test combinations comprises a seventh resistance value and an eighth resistance value, the seventh resistance value being associated with the driving variable resistor of the second transmitter, and the eighth resistance value being associated with the terminating resistor within the chip of the first receiver; and

storing the test result of each of the second test combinations to a specific location of the SRAM, so that the calibration host can obtain the test result of each of the second test combinations from the SRAM through the calibration interface.

8. The method of configuring impedance of a memory interface of claim 7, comprising:

receiving a command and an impedance setting from the calibration host, wherein the impedance setting is determined by the calibration host according to the test results of the first test combination and the second test combination; and

9. A computer-readable storage medium of an impedance configuration of a memory interface for storing a computer program capable of being executed by a processing unit, wherein the processing unit is coupled to a memory interface, a static random access memory and a calibration interface, the memory interface is coupled to a memory device and comprises a first transmitter and a first receiver, the memory device comprises a second transmitter and a second receiver, the computer program when executed by the processing unit implements the steps of:

10. The computer-readable storage medium of claim 1, wherein the computer program when executed by the processing unit implements the steps of:

11. The computer-readable storage medium of impedance configuration of a memory interface of any of claims 9 or 10, wherein the test result of the first test combination is stored in a data table, the data table comprising a first axis and a second axis, the first axis being associated with a signal strength of an on-chip termination resistance of the memory device, ranging from weak to strong or from strong to weak, and the second axis being associated with a driving signal strength of the memory interface, ranging from weak to strong or from strong to weak.

12. The computer-readable storage medium of impedance matching for a memory interface of claim 11, wherein the data table comprises a plurality of bytes, each of the bytes recording a test result when the drive variable resistor of the memory interface is set to a fifth resistance value and the on-chip termination resistor of the memory device is set to a sixth resistance value.

13. The computer-readable storage medium of claim 12, wherein the byte is a first value indicating that the memory device fails to read or write from or to a test location of the memory space.

14. The computer-readable storage medium of claim 12, wherein the byte is a second value indicating a read timeout occurs when the processing unit instructs the memory interface to perform a random read/write test; when the byte is a third value, the processing unit indicates that the write-in timeout occurs when the memory interface executes the random read-write test; and when the byte is a fourth value, the read-back data is inconsistent with the previously written data when the processing unit instructs the memory interface to execute the random read-write test.