CN115862714A

CN115862714A - SSD (solid State disk) read delay optimization method and device, computer equipment and storage medium

Info

Publication number: CN115862714A
Application number: CN202211689422.5A
Authority: CN
Inventors: 王猛; 徐伟华; 李建; 韩道静
Original assignee: Suzhou Yilian Information System Co Ltd
Current assignee: Suzhou Yilian Information System Co Ltd
Priority date: 2022-12-27
Filing date: 2022-12-27
Publication date: 2023-03-28

Abstract

The invention relates to an SSD read delay optimization method, an SSD read delay optimization device, computer equipment and a storage medium, wherein the method comprises the following steps: initializing an optimal reading voltmeter and a latest scanning timestamp table, and writing the optimal reading voltmeter and the latest scanning timestamp table into the NAND; loading the corresponding optimal read voltmeter and the latest scanning timestamp table into the memory; judging whether the SSD meets a background voltage scanning condition; data scanning is carried out on the physical block, a voltage value which can correctly read back data and has the least error bit data is written into an optimal reading voltage table, and a latest scanning timestamp table is updated; acquiring a command issued by a host; judging whether the command is a read command; searching for an optimal read voltage; perform a NAND read and return the correct data to the host. According to the invention, data is scanned in the background in the SSD, each read reference voltage is used for reading, the number of error bits is counted, and the optimal read reference voltage is recorded in the optimal read reference voltage table, so that the performance is improved, and the response delay of a command is ensured.

Description

SSD (solid State disk) read delay optimization method and device, computer equipment and storage medium

Technical Field

The invention relates to the technical field of SSD read latency, in particular to an SSD read latency optimization method, an SSD read latency optimization device, computer equipment and a storage medium.

Background

With the evolution of NAND technology, the data storage capacity of the NAND technology has been gradually increased from 1bit/ce l (SLC) to 2bit/ce l (MLC), 3b bit/ce l (TLC) and 4bit/ce l (QLC) in the early period, but the voltage distribution is denser due to the increase of the number of bits of each ce l.

The data characterization of the NAND is achieved by comparing voltages, and as the voltage distribution becomes denser, the voltages of adjacent regions are prone to generate offset/aliasing, so that the conventional read reference voltage cannot read correct data. Based on this, manufacturers provide a Read Retry method, which tries to Read correct data by offsetting the Read reference voltage, and in the process, the reference voltage needs to be trimmed left and right, whether the data is correct or not is judged according to methods such as decoding and checking, and the process needs to be tried repeatedly, and takes a long time to correct the data. When the host initiates data reading, there is a requirement for response delay, for example, in an enterprise-class application, 99.9% of the response delay of the Read command is generally required to be within a specific threshold (e.g., 1 ms), and if the Read Retry is triggered frequently, the command delay is very large, so that the product requirement cannot be met.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides an SSD read delay optimization method, an SSD read delay optimization device, computer equipment and a storage medium.

In order to solve the technical problems, the invention adopts the following technical scheme:

in a first aspect, the present embodiment provides an SSD read latency optimization method, including the following steps:

initializing an optimal reading voltmeter and a latest scanning timestamp table, and writing the optimal reading voltmeter and the latest scanning timestamp table into the NAND;

electrifying and loading the corresponding optimal reading voltmeter and the latest scanning timestamp table into the memory;

judging whether the SSD meets a background voltage scanning condition;

if the background voltage scanning condition is met, data scanning is carried out on the physical blocks meeting the condition, the voltage value which can correctly read back data and has the least error bit data is written into the optimal reading voltmeter, and meanwhile, the latest scanning timestamp table is updated;

acquiring a command issued by a host;

judging whether the command is a read command;

if the command is a read command, searching for an optimal read voltage according to a physical page address in the accessed physical block;

and performing NAND reading according to the optimal reading voltage and returning correct data to the host.

The further technical scheme is as follows: the data scanning is carried out on the physical block which meets the conditions, the voltage value which can correctly read back data and has the least error bit data is written into the optimal reading voltage table, and the latest scanning timestamp table is updated at the same time, and the method comprises the following steps:

arranging all physical blocks containing user data according to a writing time sequence;

screening a physical block which meets the condition that the difference value is larger than a first threshold value according to the writing time stamp and the current system time stamp, and calling the physical block as a first physical block set;

screening physical blocks, called second physical block sets, of which the difference value between the latest scanning timestamp and the current system timestamp is greater than a second threshold value from the first physical block sets according to the latest scanning timestamp table;

acquiring one physical block in the second physical block set, and recording as a selected physical block;

acquiring the next available read reference voltage according to the read voltage configuration table, configuring the NAND to use the corresponding read reference voltage, and selecting one physical page from the selected physical block to be marked as a selected physical page;

reading NAND, counting the number of error bits, and recording in a memory, namely recording a value;

judging whether other read reference voltage settings exist in the NAND;

if no other read reference voltage is set in the NAND, comparing and selecting all record value combinations of the physical page, selecting the minimum error bit number, and acquiring a corresponding reference voltage value to be recorded as an optimal reference voltage value;

updating the optimal reading voltage table, and updating the optimal reading voltage of the selected physical page to be the optimal reference voltage value;

judging whether other physical pages exist in the selected physical block or not;

and if no other physical page exists in the selected physical block, updating the scanning timestamp of the selected physical block in the latest scanning timestamp table to be the current timestamp of the system.

The further technical scheme is as follows: after the step of updating the scanning timestamp of the selected physical block in the latest scanning timestamp table to be the current timestamp of the system, the method further comprises the following steps:

judging whether the second physical block set has residual unscanned physical blocks or not;

and if the second physical block set does not have the remaining unscanned physical blocks, finishing the current background data reading voltage scanning.

The further technical scheme is as follows: after the step of judging whether the command is a read command, the method further comprises the following steps:

acquiring other commands issued by the host;

judging whether the NAND has erasure or not;

if the NAND has the erasure, clearing the optimal read voltage of all the physical pages in the optimal read voltage meter;

and clearing the timestamp corresponding to the physical block in the latest scanning timestamp table.

In a second aspect, the present embodiment provides an SSD read latency optimization apparatus, including: the device comprises an initialization writing unit, a loading unit, a first judgment unit, a scanning writing updating unit, a first acquisition unit, a second judgment unit, a searching unit and a reading returning unit;

the initialization writing unit is used for initializing the optimal reading voltmeter and the latest scanning timestamp table and writing the optimal reading voltmeter and the latest scanning timestamp table into the NAND;

the loading unit is used for electrically loading the corresponding optimal reading voltmeter and the latest scanning timestamp table into the memory;

the first judging unit is used for judging whether the SSD meets the background voltage scanning condition;

the scanning write-in updating unit is used for scanning data of the physical block meeting the condition if the background voltage scanning condition is met, writing the voltage value which can correctly read the data and has the least error bit data into the optimal read voltage table, and updating the latest scanning timestamp table;

the first acquisition unit is used for acquiring a command issued by the host;

the second judging unit is used for judging whether the command is a read command;

the searching unit is used for searching the optimal reading voltage according to the physical page address in the accessed physical block if the command is a reading command;

and the reading return unit is used for performing NAND reading according to the optimal reading voltage and returning correct data to the host.

The further technical scheme is as follows: the scan write update unit includes: the device comprises a writing module, a first screening module, a second screening module, an acquisition configuration selection module, a reading statistical record module, a first judgment module, a comparison selection acquisition module, a first updating module, a second judgment module and a second updating module;

the writing module is used for arranging all physical blocks containing user data according to a writing time sequence;

the first screening module is used for screening a physical block which meets the condition that the difference value is larger than a first threshold value according to the writing time stamp and the current system time stamp and is called a first physical block set;

the second screening module is used for screening the physical blocks with the difference value between the latest scanning timestamp and the current system timestamp larger than a second threshold value from the first physical block set according to the latest scanning timestamp table, and the physical blocks are called a second physical block set;

the acquisition module is used for acquiring one physical block in the second physical block set and recording the physical block as a selected physical block;

the acquisition configuration selection module is used for acquiring the next available read reference voltage according to the read voltage configuration table, configuring the NAND to use the corresponding read reference voltage, and selecting one physical page from the selected physical block and marking the physical page as the selected physical page;

the reading statistic recording module is used for reading the NAND, counting the number of error bits and recording the error bits in the memory, namely recording values;

the first judgment module is used for judging whether other read reference voltage settings exist in the NAND;

the comparison selection acquisition module is used for comparing and selecting all recording value combinations of the physical pages if no other read reference voltage is set in the NAND, selecting the smallest error bit number, acquiring the corresponding reference voltage value and recording the reference voltage value as the optimal reference voltage value;

the first updating module is used for updating the optimal reading voltage table and updating the optimal reading voltage of the selected physical page into an optimal reference voltage value;

the second judging module is used for judging whether other physical pages exist in the selected physical block;

and the second updating module is used for updating the scanning timestamp of the selected physical block in the latest scanning timestamp table to be the current timestamp of the system if no other physical page exists in the selected physical block.

The further technical scheme is as follows: the scan write update unit further comprises: a third judging module and a finishing module;

the third judging module is used for judging whether the second physical block set has the remaining unscanned physical blocks;

and the completion module is used for completing the current background data reading voltage scanning if the second physical block set does not have the remaining unscanned physical blocks.

The further technical scheme is as follows: the device further comprises: the device comprises a second acquisition unit, a third judgment unit, a first zero clearing unit and a second zero clearing unit;

the second acquisition unit is used for acquiring other commands issued by the host;

the third judging unit is used for judging whether the NAND has erasure;

the first zero clearing unit is used for clearing the optimal read voltage of all physical pages in the optimal read voltage meter if the NAND is erased;

and the second zero clearing unit is used for clearing the timestamp corresponding to the physical block in the latest scanning timestamp table.

In a third aspect, this embodiment provides a computer device, where the computer device includes a memory and a processor, where the memory stores a computer program, and the processor implements the SSD read latency optimization method when executing the computer program.

In a fourth aspect, the present embodiment provides a storage medium storing a computer program comprising program instructions which, when executed by a processor, may implement the SSD read latency optimization method as described above.

Compared with the prior art, the invention has the beneficial effects that: a tracking table of the optimal read voltage of the physical block/page is introduced, data is scanned in a background in the SSD, each read reference voltage is used for reading, the number of error bits is counted, the optimal read reference voltage is recorded in the optimal read reference voltage table, so that the optimal read voltage can be used for reading the physical page at the first time when a host accesses the data, the performance consistency is greatly improved, and the response delay of commands is guaranteed.

The invention is further described below with reference to the accompanying drawings and specific embodiments.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

Fig. 1 is a schematic flowchart of an SSD read latency optimization method according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of an optimal read voltage table according to an embodiment of the present invention;

FIG. 3 is a diagram of a recent scan timestamp table according to an embodiment of the present invention;

fig. 4 is a schematic sub-flow diagram of an SSD read latency optimization method according to an embodiment of the invention;

FIG. 5 is a schematic block diagram of an SSD read latency optimization apparatus provided by an embodiment of the present invention;

FIG. 6 is a sub-schematic block diagram of an SSD read latency optimization apparatus provided by an embodiment of the present invention;

FIG. 7 is a schematic block diagram of a computer device provided by an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

A typical NAND composition is as follows: DIE, independently concurrently operable units; a Block, which is an independently erasable unit, wherein after data at each physical position is written, the whole Block must be erased before the next writing; page, read-write unit, pages in the same physical block must be programmed with 0- >1- >2- >3 \8230insequence.

Referring to the embodiment shown in fig. 1, the present invention discloses an SSD read latency optimization method, comprising the following steps:

s1, initializing an optimal read voltmeter and a latest scanning timestamp table, and writing the optimal read voltmeter and the latest scanning timestamp table into an NAND;

referring to FIG. 2, the preferred read voltage table includes:

CH, SSD internal physical channel number, different CH bus independent, can be totally concurrent execution;

CE, SSD internal physical chip selection number, bus time sharing between different CEs, typically one DIE is connected under each CE;

block, corresponding to the physical Block number in DIE;

page, corresponding to the physical Page number in Block;

best read voltage for the corresponding physical page (least number of error bits).

Referring to fig. 3, the latest scanning timestamp table includes:

block, corresponding to the physical Block number in DIE;

LatestScanTimestamp, the timestamp of the last read voltage scan of the physical block.

Specifically, the initialization means to clear both bestreddvref and latex scantimestamp, where bestreddvref being 0 indicates that the read reference voltage is not being used (no offset), and latex scantimestamp being 0 indicates that the read voltage scan has not been performed.

S2, electrifying and loading the corresponding optimal reading voltmeter and the latest scanning timestamp table into a memory;

s3, judging whether the SSD meets background voltage scanning conditions or not; if the background voltage scanning condition is not met, skipping to execute the step S5;

specifically, the SSD is run first, and then it is determined whether the SSD satisfies the background voltage scan condition. Background voltage scanning conditions can be customized, and one implementation mode is to trigger background voltage scanning periodically (minute/hour/day and the like); one way is that the host triggers when idle without command access.

S4, if the background voltage scanning condition is met, data scanning is carried out on the physical blocks meeting the condition, the voltage value which can correctly read back the data and has the least error bit data is written into the optimal reading voltmeter, and meanwhile, the latest scanning timestamp table is updated;

specifically, the physical block that meets the condition refers to a physical block in which user valid data is stored, and does not include a blank block/a bad block/a system data block, and the like.

In an embodiment, referring to fig. 4, the data scanning of the eligible physical blocks, and writing the voltage values with the least error bit data and the least data read back correctly into the optimal read voltage table, and updating the latest scanning timestamp table, includes the following steps:

s4a, arranging all physical blocks containing user data according to a writing time sequence;

s4b, screening a physical block which accords with the difference value larger than a first threshold value according to the writing time stamp and the current system time stamp, and calling the physical block as a first physical block set;

specifically, the first threshold (Data _ Hold _ TH) can be defined by itself, such as 100.

S4c, screening the physical blocks with the difference value between the latest scanning timestamp and the current system timestamp larger than a second threshold value from the first physical block set according to the latest scanning timestamp table, and calling the physical blocks as a second physical block set;

specifically, the second threshold (Data _ Scan _ TH) can be defined by itself, such as 50.

S4d, acquiring one physical block in the second physical block set, and recording as a selected physical block;

specifically, one physical block is randomly selected from the second set of physical blocks in a random selection manner.

S4e, acquiring the next available reading reference voltage according to the reading voltage configuration table, configuring the NAND to use the corresponding reading reference voltage, and selecting one physical page from the selected physical block and marking as the selected physical page;

in particular, the read voltage configuration table is generally provided by the NAND vendor. The corresponding read reference voltage is denoted as Vref _ i.

S4f, reading the NAND, counting the number of error bits, and recording in the memory, namely recording values;

specifically, the recorded value is (Vref _ i, error _ bit _ num _ i).

S4g, judging whether other read reference voltages are set in the NAND; if other read reference voltages are set in the NAND, returning to execute the step S4 e;

s4h, if no other read reference voltage is set in the NAND, comparing and selecting all record value combinations of the physical page, selecting the minimum error bit number, and acquiring a corresponding reference voltage value to be recorded as an optimal reference voltage value;

specifically, the combination of the recording values is (Vref, error _ bit _ num), the number of error bits is (error _ bit _ num), and the optimum reference voltage value is Vref _ Best.

S4i, updating the optimal reading voltage table, and updating the optimal reading voltage of the selected physical page to be the optimal reference voltage value;

s4j, judging whether other physical pages exist in the selected physical block or not; if other physical pages exist in the selected physical block, returning to execute the step S4 e;

and S4k, if no other physical page exists in the selected physical block, updating the scanning timestamp of the selected physical block in the latest scanning timestamp table to be the current timestamp of the system.

In an embodiment, after the step of updating the scanning timestamp of the selected physical block in the latest scanning timestamp table to be the current timestamp of the system, the method further includes:

s4l, judging whether the second physical block set has residual unscanned physical blocks or not;

s4m, if the second physical block set does not have the remaining unscanned physical blocks, finishing the current background data reading voltage scanning;

and S4n, if the remaining unscanned physical blocks exist in the second physical block set, acquiring a next physical block to be scanned in the second physical block set, and returning to execute the step S4 e.

S5, acquiring a command issued by the host;

s6, judging whether the command is a read command;

s7, if the command is a read command, searching for an optimal read voltage according to a physical page address in an accessed physical block;

specifically, the physical Page address in the physical Block is corresponding CH/CE/Block/Page.

And S8, performing NAND reading according to the optimal reading voltage, and returning correct data to the host.

In an embodiment, after the step S8, the method further includes: and returning to execute the step S3.

In an embodiment, after the step of determining whether the command is a read command, the method further includes:

s9, acquiring other commands issued by the host;

in particular, the amount of the solvent to be used, other commands refer to other conventional commands besides read commands.

S10, judging whether the NAND is erased or not; if the NAND is not erased, returning to execute the step S3;

s11, if the NAND is erased, resetting the optimal read voltage of all physical pages in the optimal read voltmeter;

specifically, all physical pages refer to all pages under CH/CE/Block.

And S12, clearing the time stamp corresponding to the physical block in the latest scanning time stamp table.

In an embodiment, after the step S12, the method further includes: and returning to execute the step S3.

Further, the optimal read voltage table and the latest scanning timestamp table in the memory can be periodically stored on the NAND, or stored on the NAND when the host sends a power-down command, so that the information can be inherited after power-down/power-up.

The invention introduces the tracking table of the optimal read voltage of the physical block/page, scans data in a background in the SSD, reads by using each read reference voltage and counts the number of error bits, and records the optimal read reference voltage into the optimal read reference voltage table, so that the optimal read voltage can be used for reading the physical page at the first time when a host accesses the data, thereby greatly improving the performance consistency and ensuring the response delay of commands.

Referring to fig. 5, the present invention also discloses an SSD read latency optimization device, comprising: the device comprises an initialization write-in unit 10, a loading unit 20, a first judgment unit 30, a scanning write-in updating unit 40, a first acquisition unit 50, a second judgment unit 60, a search unit 70 and a read return unit 80;

the initialization writing unit 10 is configured to initialize the optimal read voltmeter and the latest scanning timestamp table, and write the optimal read voltmeter and the latest scanning timestamp table into the NAND;

the loading unit 20 is configured to electrically load the corresponding optimal read voltmeter and the latest scan timestamp table into the memory;

the first judging unit 30 is configured to judge whether the SSD satisfies a background voltage scanning condition;

the scanning write-in updating unit 40 is configured to scan data of the physical block meeting the background voltage scanning condition, write a voltage value, which can read data correctly and has the least error bit data, into the optimal read voltmeter, and update the latest scanning timestamp table at the same time;

the first obtaining unit 50 is configured to obtain a command issued by a host;

the second judging unit 60 is configured to judge whether the command is a read command;

the lookup unit 70 is configured to, if the command is a read command, searching the optimal read voltage according to the physical page address in the accessed physical block;

the read return unit 80 is configured to perform NAND reading according to the optimal read voltage and return correct data to the host.

In one embodiment, referring to fig. 6, the scan write update unit 40 includes: a write-in module 40a, a first screening module 40b, a second screening module 40c, an obtaining module 40d, an obtaining configuration selection module 40e, a reading statistical record module 40f, a first judgment module 40g, a comparison selection obtaining module 40h, a first updating module 40i, a second judgment module 40j and a second updating module 40k;

the writing module 40a is configured to arrange all physical blocks containing user data according to a writing time sequence;

the first screening module 40b is configured to screen, according to the write timestamp and the current system timestamp, a physical block that meets a condition that a difference value is greater than a first threshold value, which is referred to as a first physical block set;

the second screening module 40c is configured to screen, according to the latest scanning timestamp table, a physical block in the first physical block set, where a difference between the latest scanning timestamp and the current system timestamp is greater than a second threshold, and the physical block is referred to as a second physical block set;

the obtaining module 40d is configured to obtain one physical block in the second set of physical blocks, and record the physical block as a selected physical block;

the obtaining configuration selecting module 40e is configured to obtain a next available read reference voltage according to the read voltage configuration table, configure the NAND to use the corresponding read reference voltage, and select one physical page from the selected physical block, which is recorded as a selected physical page;

the reading statistic recording module 40f is configured to read the NAND, count the number of error bits, and record the error bits in the memory, that is, record a value;

the first judging module 40g is configured to judge whether there are other read reference voltage settings in the NAND;

the comparison selection acquisition module 40h is used for comparing and selecting all recording value combinations of the physical pages if no other read reference voltage is set in the NAND, selecting the smallest error bit number, acquiring the corresponding reference voltage value, and recording the reference voltage value as the optimal reference voltage value;

the first updating module 40i is configured to update the optimal read voltage table, and update the optimal read voltage of the selected physical page to the optimal reference voltage value;

the second judging module 40j is configured to judge whether there are other physical pages in the selected physical block;

the second updating module 40k is configured to update the scanning timestamp of the selected physical block in the latest scanning timestamp table to be the current system timestamp if there is no other physical page in the selected physical block.

In an embodiment, referring to fig. 6, the scan write update unit 40 further includes: a third judging module 40l and a finishing module 40m;

the third judging module 40l is configured to judge whether remaining unscanned physical blocks exist in the second physical block set;

and the completion module 40m is configured to complete the current background data read voltage scanning if the remaining unscanned physical blocks do not exist in the second physical block set.

In an embodiment, referring to fig. 6, the scan write update unit 40 further includes: and an obtaining and returning module 40n, configured to obtain a next physical block to be scanned in the second physical block set, and return to execute obtaining a next available read reference voltage according to the read voltage configuration table, configure the NAND to use the corresponding read reference voltage, and select one physical page from the selected physical blocks, which is recorded as a selected physical page.

In one embodiment, please refer to fig. 5, the apparatus further includes: a second obtaining unit 90, a third judging unit 100, a first clear unit 110 and a second clear unit 120;

the second obtaining unit 90 is configured to obtain other commands issued by the host;

the third judging unit 100 is configured to judge whether the NAND has erasure;

the first clearing unit 110 is configured to clear the optimal read voltages of all physical pages in the optimal read voltage table if the NAND is erased;

the second clearing unit 120 is configured to clear the timestamp corresponding to the physical block in the latest scanning timestamp table.

It should be noted that, as can be clearly understood by those skilled in the art, the specific implementation processes of the SSD read delay optimization device and each unit may refer to the corresponding descriptions in the foregoing method embodiments, and for convenience and brevity of description, no further description is provided herein.

The SSD read latency optimization apparatus described above may be implemented in the form of a computer program that can be run on a computer device as shown in fig. 7.

Referring to fig. 7, fig. 7 is a schematic block diagram of a computer device according to an embodiment of the present application; the computer device 500 may be a terminal or a server, where the terminal may be an electronic device with a communication function, such as a smart phone, a tablet computer, a notebook computer, a desktop computer, a personal digital assistant, and a wearable device. The server may be an independent server or a server cluster composed of a plurality of servers.

Referring to fig. 7, the computer device 500 includes a processor 502, memory, and a network interface 505 connected by a system bus 501, where the memory may include a non-volatile storage medium 503 and an internal memory 504.

The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032. The computer programs 5032 include program instructions that, when executed, cause the processor 502 to perform a SSD read latency optimization method.

The processor 502 is used to provide computing and control capabilities to support the operation of the overall computer device 500.

The internal memory 504 provides an environment for the operation of the computer program 5032 in the non-volatile storage medium 503, and when the computer program 5032 is executed by the processor 502, the processor 502 may be enabled to perform an SSD read latency optimization method.

The network interface 505 is used for network communication with other devices. Those skilled in the art will appreciate that the configuration shown in fig. 7 is a block diagram of only a portion of the configuration associated with the present application and does not constitute a limitation of the computer device 500 to which the present application may be applied, and that a particular computer device 500 may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.

Wherein the processor 502 is configured to run the computer program 5032 stored in the memory to implement the following steps:

initializing an optimal reading voltmeter and a latest scanning timestamp table, and writing the optimal reading voltmeter and the latest scanning timestamp table into the NAND; electrifying and loading the corresponding optimal reading voltmeter and the latest scanning timestamp table into the memory; judging whether the SSD meets a background voltage scanning condition; if the background voltage scanning condition is met, data scanning is carried out on the physical blocks meeting the condition, the voltage value which can correctly read back data and has the least error bit data is written into the optimal reading voltmeter, and meanwhile, the latest scanning timestamp table is updated; acquiring a command issued by a host; judging whether the command is a read command; if the command is a read command, searching for an optimal read voltage according to a physical page address in the accessed physical block; and performing NAND reading according to the optimal reading voltage and returning correct data to the host.

It should be understood that, in the embodiment of the present Application, the processor 502 may be a Central Processing Unit (CPU), and the processor 502 may also be other general purpose processors, digital Signal Processors (DSPs), application Specific Integrated Circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and the like. Wherein a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

It will be understood by those skilled in the art that all or part of the flow of the method implementing the above embodiments may be implemented by a computer program instructing associated hardware. The computer program includes program instructions, and the computer program may be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the flow steps of the embodiments of the method described above.

Accordingly, the present invention also provides a storage medium. The storage medium may be a computer-readable storage medium. The storage medium stores a computer program, wherein the computer program comprises program instructions that, when executed by a processor, may implement the SSD read latency optimization method described above. The storage medium stores a computer program comprising program instructions which, when executed by a processor, implement the method described above. The program instructions include the steps of:

initializing the optimal reading voltmeter and the latest scanning timestamp table, and writing the optimal reading voltmeter and the latest scanning timestamp table into the NAND; electrifying and loading the corresponding optimal reading voltmeter and the latest scanning timestamp table into the memory; judging whether the SSD meets a background voltage scanning condition; if the background voltage scanning condition is met, data scanning is carried out on the physical blocks meeting the condition, the voltage value which can correctly read the data and has the least error bit data is written into the optimal reading voltmeter, and meanwhile, the latest scanning timestamp table is updated; acquiring a command issued by a host; judging whether the command is a read command; if the command is a read command, searching for an optimal read voltage according to a physical page address in the accessed physical block; and performing NAND reading according to the optimal reading voltage and returning correct data to the host.

The storage medium may be a usb disk, a removable hard disk, a Read-only memory (ROM), a magnetic disk or an optical disk, and various computer readable storage media that can store program codes.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described in a functional general in the foregoing description for the purpose of illustrating clearly the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative. For example, the division of each unit is only one logic function division, and there may be another division manner in actual implementation. For example, various elements or components may be combined or may be integrated in another system or some features may be omitted, or not implemented.

The steps in the method of the embodiment of the invention can be sequentially adjusted, combined and deleted according to actual needs. The units in the device of the embodiment of the invention can be combined, divided and deleted according to actual needs. In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a storage medium. Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a terminal, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention.

The above embodiments are preferred implementations of the present invention, and the present invention can be implemented in other ways without departing from the spirit of the present invention.

Claims

An SSD read latency optimization method, comprising the steps of:

initializing an optimal reading voltmeter and a latest scanning timestamp table, and writing the optimal reading voltmeter and the latest scanning timestamp table into the NAND;

electrifying and loading the corresponding optimal reading voltmeter and the latest scanning timestamp table into the memory;

judging whether the SSD meets a background voltage scanning condition;

if the background voltage scanning condition is met, data scanning is carried out on the physical blocks meeting the condition, the voltage value which can correctly read back data and has the least error bit data is written into the optimal reading voltmeter, and meanwhile, the latest scanning timestamp table is updated;

acquiring a command issued by a host;

judging whether the command is a read command;

if the command is a read command, searching for an optimal read voltage according to a physical page address in the accessed physical block;

and performing NAND reading according to the optimal reading voltage and returning correct data to the host.
2. The SSD read delay optimization method of claim 1, wherein the data scanning is performed on eligible physical blocks, and the voltage values with the least amount of erroneous bit data and the correctly read data are written into the optimal read voltage table, and the latest scan timestamp table is updated, comprising the steps of:

arranging all physical blocks containing user data according to a writing time sequence;

screening a physical block which meets the condition that the difference value is larger than a first threshold value according to the writing time stamp and the current system time stamp, and calling the physical block as a first physical block set;

screening physical blocks, called second physical block sets, of which the difference value between the latest scanning timestamp and the current system timestamp is greater than a second threshold value from the first physical block sets according to the latest scanning timestamp table;

acquiring one physical block in the second physical block set, and recording as a selected physical block;

acquiring the next available read reference voltage according to the read voltage configuration table, configuring the NAND to use the corresponding read reference voltage, and selecting one physical page from the selected physical block to be marked as a selected physical page;

reading NAND, counting the number of error bits, and recording in a memory, namely recording a value;

judging whether other read reference voltage settings exist in the NAND;

if no other read reference voltage is set in the NAND, comparing and selecting all record value combinations of the physical page, selecting the minimum error bit number, and acquiring a corresponding reference voltage value to be recorded as an optimal reference voltage value;

updating the optimal reading voltage table, and updating the optimal reading voltage of the selected physical page to be the optimal reference voltage value;

judging whether other physical pages exist in the selected physical block or not;

and if no other physical page exists in the selected physical block, updating the scanning timestamp of the selected physical block in the latest scanning timestamp table to be the current timestamp of the system.
3. The SSD read delay optimization method of claim 2, wherein after the step of updating the scan timestamp of the selected physical block in the latest scan timestamp table to be the system current timestamp, further comprising:

judging whether the second physical block set has residual unscanned physical blocks or not;

and if the second physical block set does not have the remaining unscanned physical blocks, finishing the current background data reading voltage scanning.
4. The SSD read latency optimization method of claim 1, wherein after the step of determining whether the command is a read command, further comprising:

acquiring other commands issued by the host;

judging whether the NAND has erasure or not;

if the NAND has the erasure, clearing the optimal read voltage of all the physical pages in the optimal read voltage meter;

and clearing the timestamp corresponding to the physical block in the latest scanning timestamp table.
An SSD read latency optimization apparatus, comprising: the device comprises an initialization writing unit, a loading unit, a first judgment unit, a scanning writing updating unit, a first acquisition unit, a second judgment unit, a searching unit and a reading returning unit;

the initialization writing unit is used for initializing the optimal reading voltmeter and the latest scanning timestamp table and writing the optimal reading voltmeter and the latest scanning timestamp table into the NAND;

the loading unit is used for electrically loading the corresponding optimal reading voltmeter and the latest scanning timestamp table into the memory;

the first judging unit is used for judging whether the SSD meets the background voltage scanning condition;

the scanning write-in updating unit is used for scanning data of the physical block meeting the condition if the background voltage scanning condition is met, writing the voltage value which can correctly read the data and has the least error bit data into the optimal read voltage table, and updating the latest scanning timestamp table;

the first obtaining unit is used for obtaining a command issued by a host;

the second judging unit is used for judging whether the command is a read command;

the searching unit is used for searching the optimal reading voltage according to the physical page address in the accessed physical block if the command is a reading command;

and the reading return unit is used for performing NAND reading according to the optimal reading voltage and returning correct data to the host.
6. The SSD read latency optimization device of claim 5, wherein the scan write update unit comprises: the device comprises a writing module, a first screening module, a second screening module, an acquisition configuration selection module, a reading statistical record module, a first judgment module, a comparison selection acquisition module, a first updating module, a second judgment module and a second updating module;

the writing module is used for arranging all physical blocks containing user data according to a writing time sequence;

the first screening module is used for screening a physical block which meets the condition that the difference value is larger than a first threshold value according to the writing time stamp and the current system time stamp and is called a first physical block set;

the second screening module is used for screening the physical blocks with the difference value between the latest scanning timestamp and the current system timestamp larger than a second threshold value from the first physical block set according to the latest scanning timestamp table, and the physical blocks are called a second physical block set;

the acquisition module is used for acquiring one physical block in the second physical block set and recording the physical block as a selected physical block;

the acquisition configuration selection module is used for acquiring the next available read reference voltage according to the read voltage configuration table, configuring the NAND to use the corresponding read reference voltage, and selecting one physical page from the selected physical block to be marked as a selected physical page;

the reading statistic recording module is used for reading the NAND, counting the number of error bits and recording the error bits in the memory, namely recording values;

the first judgment module is used for judging whether other read reference voltage settings exist in the NAND;

the comparison selection acquisition module is used for comparing and selecting all record value combinations of the physical pages if no other read reference voltage is set in the NAND, selecting the smallest error bit number, acquiring the corresponding reference voltage value and recording the reference voltage value as the optimal reference voltage value;

the first updating module is used for updating the optimal reading voltage table and updating the optimal reading voltage of the selected physical page into an optimal reference voltage value;

the second judging module is used for judging whether other physical pages exist in the selected physical block;

and the second updating module is used for updating the scanning timestamp of the selected physical block in the latest scanning timestamp table to be the current timestamp of the system if no other physical page exists in the selected physical block.
7. The SSD read latency optimization device of claim 6, wherein the scan write update unit further comprises: a third judging module and a finishing module;

the third judging module is used for judging whether the second physical block set has the remaining unscanned physical blocks;

and the completion module is used for completing the current background data reading voltage scanning if the second physical block set does not have the remaining unscanned physical blocks.
8. The SSD read latency optimization apparatus of claim 5, wherein the apparatus further comprises: the device comprises a second acquisition unit, a third judgment unit, a first zero clearing unit and a second zero clearing unit;

the second acquisition unit is used for acquiring other commands issued by the host;

the third judging unit is used for judging whether the NAND has erasure or not;

the first zero clearing unit is used for clearing the optimal reading voltage of all physical pages in the optimal reading voltmeter if the NAND is erased;

and the second zero clearing unit is used for clearing the timestamp corresponding to the physical block in the latest scanning timestamp table.
9. A computer device comprising a memory having stored thereon a computer program and a processor that, when executing the computer program, implements the SSD read latency optimization method of any of claims 1-4.
10. A storage medium, characterized in that the storage medium stores a computer program comprising program instructions which, when executed by a processor, implement the SSD read latency optimization method of any of claims 1-4.