CN114415969B - Method for dynamically storing messages of exchange chip - Google Patents
Method for dynamically storing messages of exchange chip Download PDFInfo
- Publication number
- CN114415969B CN114415969B CN202210119985.4A CN202210119985A CN114415969B CN 114415969 B CN114415969 B CN 114415969B CN 202210119985 A CN202210119985 A CN 202210119985A CN 114415969 B CN114415969 B CN 114415969B
- Authority
- CN
- China
- Prior art keywords
- mapping
- queues
- chip
- exchange chip
- messages
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 23
- 238000013507 mapping Methods 0.000 claims abstract description 98
- 230000005540 biological transmission Effects 0.000 claims description 3
- 238000012423 maintenance Methods 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000003139 buffering effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000013259 porous coordination polymer Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/544—Buffers; Shared memory; Pipes
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Software Systems (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention discloses a dynamic message storage method of a switching chip, which comprises the following steps: setting a plurality of mapping queues in a switching chip; setting a storage mode of a part of mapping queues to obtain a plurality of first mapping queues, wherein the storage mode of the plurality of first mapping queues is an internal buffer storage mode only; setting the storage modes of the rest mapping queues as a mixed storage mode, and obtaining a plurality of second mapping queues; setting an internal buffer storage threshold and a mixed buffer storage threshold of a plurality of second mapping queues; and the switching chip switches and applies a plurality of first mapping queues and a plurality of second mapping queues to store the messages in the internal buffer and the external buffer according to the flow state of the messages input into the switching chip. The invention ensures the low time delay characteristic of the exchange chip, increases the buffer capacity of the exchange chip, reduces the production cost and the maintenance cost of the exchange chip, and improves the input-output efficiency of the exchange chip.
Description
Technical Field
The invention relates to the technical field of exchange chip software, in particular to a dynamic storage method for exchange chip messages.
Background
In the prior art, under the burst scene, the switching device mainly absorbs the burst message by improving the bandwidth of the switching chip or increasing the buffer capacity in the chip, thereby achieving the purposes of high priority, low time delay and low priority without packet loss.
The prior art has the defects of high production cost, high maintenance cost and low input-output efficiency of the exchange chip.
Disclosure of Invention
According to the embodiment of the invention, a method for dynamically storing messages of a switching chip is provided, which comprises the following steps:
setting a plurality of mapping queues in a switching chip;
setting a storage mode of a part of mapping queues to obtain a plurality of first mapping queues, wherein the storage mode of the plurality of first mapping queues is an internal buffer storage mode only;
setting the storage modes of the rest mapping queues to obtain a plurality of second mapping queues, wherein the storage modes of the plurality of second mapping queues are mixed storage modes;
setting an internal buffer storage threshold and a mixed buffer storage threshold of a plurality of second mapping queues;
the switching chip switches and applies a plurality of first mapping queues and a plurality of second mapping queues to store the messages input into the internal buffer of the switching chip and the external buffer of the switching chip according to the flow state of the messages input into the switching chip.
Further, the residual messages of the plurality of mapping queues are emptied before setting the storage modes of the plurality of mapping queues.
Further, a plurality of mapping queues are set in the exchange chip, comprising the following substeps:
based on 802.1q protocol, the priority of the message input into the exchange chip is configured to a plurality of priority templates through external software;
mapping a plurality of priority templates to a plurality of queues to obtain a plurality of mapping queues.
Further, the plurality of first mapping queues are all high priority queues.
Further, the plurality of second mapping queues are low priority queues.
Further, the setting rules of the internal buffer storage threshold and the mixed buffer storage threshold of the plurality of second mapping queues are as follows:
the mixed buffer storage threshold is larger than the sum of the internal buffer storage threshold and the maximum transmission unit of the exchange chip;
when the statistics of the internal buffer messages input into the exchange chip reaches an internal buffer storage threshold, the exchange chip uses a plurality of second mapping queues to store the messages input into the exchange chip in the external buffer of the exchange chip;
when the internal buffer message statistics of the exchange chip is smaller than the internal buffer storage threshold, and the sum of the internal buffer message statistics and the external message statistics of the exchange chip is smaller than the mixed buffer storage threshold, the exchange chip uses a plurality of second mapping queues to store the messages which are subsequently input into the exchange chip in the internal buffer of the exchange chip.
Further, the switching chip switches and applies a plurality of first mapping queues and a plurality of second mapping queues to store the message input into the internal buffer of the switching chip and the external buffer of the switching chip according to the flow state of the message input into the switching chip, and the switching chip comprises the following substeps:
when the flow state of the input message of the exchange chip is a stable state, the input exchange chip message does not meet the requirements of the internal buffer storage threshold value and the mixed buffer storage threshold value of the second mapping queue, and the exchange chip applies a plurality of first mapping queues and a plurality of second mapping queues to store the message in the internal buffer of the exchange chip;
when the traffic state of the input message of the exchange chip is a burst state, the input exchange chip message meets the requirements of the internal buffer storage threshold and the mixed buffer storage threshold of the second mapping queue, the exchange chip uses the first mapping queue to store the message input into the internal buffer of the exchange chip, and the exchange chip uses a plurality of second mapping queues to store the message input into the second mapping queue into the internal buffer of the exchange chip and the external buffer of the exchange chip.
According to the method for dynamically storing the messages of the exchange chip, the low-delay characteristic of the exchange chip is guaranteed, the buffer capacity of the exchange chip is increased, meanwhile, the production cost and the maintenance cost of the exchange chip are reduced, and the input and output efficiency of the exchange chip is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the technology claimed.
Drawings
FIG. 1 is a flow chart showing steps of a method for dynamically storing messages of a switching chip according to an embodiment of the present invention;
FIG. 2 is a flow chart of sub-steps of step S1 according to an embodiment of the present invention;
fig. 3 is a flow chart of the sub-steps of step S5 according to an embodiment of the invention.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the attached drawings, which further illustrate the present invention.
Firstly, a method for dynamically storing a message of a switching chip according to an embodiment of the present invention will be described with reference to fig. 1 to 3, where the method is used for guaranteeing high priority low latency and caching capability of the switching chip in case of improving traffic emergency, and has a wide application scenario.
As shown in fig. 1 to 3, the method for dynamically storing the messages of the switch chip according to the embodiment of the invention includes the following steps:
in S1, as shown in fig. 1, a plurality of mapping queues are set in the switch chip.
Further, a plurality of mapping queues are set in the exchange chip, comprising the following substeps:
in S11, as shown in fig. 2, based on the 802.1q protocol, the priority of the message input to the switch chip is configured to a plurality of priority templates by external software, that is, eight templates are mapped to 8 PCPs.
In S12, as shown in fig. 2, a plurality of priority templates are mapped to a plurality of queues, and a plurality of mapped queues are obtained, that is, eight templates are mapped to 8 queues according to the priority size.
In S2, as shown in fig. 1, the storage mode of the partial mapping queues is set to obtain a plurality of first mapping queues, where the storage mode of the plurality of first mapping queues is an Only internal buffer storage mode (Only buffer) and is used to store the message input into the switch chip in the internal buffer of the switch chip, that is, SRAM, and 4 queues with high priority are preferably set as 4 first mapping queues.
Further, the residual messages of the plurality of mapping queues are emptied before setting the storage modes of the plurality of mapping queues.
Further, the plurality of first mapping queues are all high priority queues.
In S3, as shown in fig. 1, the storage modes of the remaining mapping queues are set to obtain a plurality of second mapping queues, where the storage modes of the plurality of second mapping queues are a hybrid storage mode (Mix), and the remaining 4 queues are preferably set as 4 second mapping queues.
Further, the plurality of second mapping queues are low priority queues.
In S4, as shown in fig. 1, an internal buffer storage threshold and a mixed buffer storage threshold of the plurality of second mapping queues are set.
Further, the setting rules of the internal buffer storage threshold and the mixed buffer storage threshold of the plurality of second mapping queues are as follows:
the hybrid buffer memory threshold (mix_th) is greater than the sum of the internal buffer memory threshold (in_th) and the Maximum Transmission Unit (MTU) of the switching chip.
When the burst or congestion exists in the message flow, the statistics of the internal buffer messages input into the exchange chip reaches an internal buffer storage threshold (mix_th), and the exchange chip uses a plurality of second mapping queues to store the messages input into the exchange chip in the external buffer of the exchange chip, namely DDR or HBM.
When the message flow is reduced or the burst is smaller, the internal buffer message statistics of the exchange chip is smaller than the internal buffer storage threshold (mix_th), and the sum of the internal buffer message statistics and the external message statistics of the exchange chip is smaller than the mixed buffer storage threshold (mix_th), and the exchange chip uses a plurality of second mapping queues to store the messages which are subsequently input into the exchange chip in the internal buffer of the exchange chip.
In S5, as shown in fig. 1, the switch chip switches and applies a plurality of first mapping queues and a plurality of second mapping queues to store the message input to the switch chip in the internal buffer of the switch chip and the external buffer of the switch chip according to the traffic state of the message input to the switch chip.
Further, the switching chip switches and applies a plurality of first mapping queues and a plurality of second mapping queues to store the message input into the internal buffer of the switching chip and the external buffer of the switching chip according to the flow state of the message input into the switching chip, and the switching chip comprises the following substeps:
in S51, as shown in fig. 3, when the traffic state of the input packet of the switch chip is a steady state, the input switch chip packet does not meet the requirements of the internal buffer storage threshold and the mixed buffer storage threshold of the second mapping queue, and the switch chip applies a plurality of first mapping queues and a plurality of second mapping queues to store the packet in the internal buffer of the switch chip.
In S52, as shown in fig. 3, when the traffic state of the input packet of the switch chip is a burst state, the input switch chip packet does not meet the requirements of the internal buffer storage threshold and the mixed buffer storage threshold of the second mapping queue, the switch chip applies the first mapping queue to store the input packet of the first mapping queue in the internal buffer of the switch chip, and the switch chip applies a plurality of second mapping queues to store the input packet of the second mapping queue in the internal buffer of the switch chip and the external buffer of the switch chip.
In this embodiment, by using an external buffer, under the condition that the bandwidth of the exchange chip is satisfied, all messages can be exchanged through the internal buffer, when there is a burst in the message traffic of the input chip, the messages with low priority are stored into the external buffer through the second mapping queue of the hybrid storage mode (Mix), and the messages with high priority are forwarded through the internal buffer.
In the above, the method for dynamically storing the messages of the exchange chip according to the embodiment of the invention is described with reference to fig. 1 to 3, which ensures the low-delay characteristic of the exchange chip and increases the buffering capacity of the exchange chip, and simultaneously reduces the production cost and maintenance cost of the exchange chip and improves the input-output efficiency of the exchange chip.
It should be noted that in this specification the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
While the present invention has been described in detail through the preferred embodiments, it should be understood that the description is not to be considered as limiting the invention. Many modifications and substitutions of this invention will now become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be limited only by the attached claims.
Claims (6)
1. A dynamic storage method for exchanging chip messages is characterized by comprising the following steps:
setting a plurality of mapping queues in a switching chip;
setting the storage modes of part of the mapping queues to obtain a plurality of first mapping queues, wherein the storage modes of the plurality of first mapping queues are only internal buffer storage modes;
setting the storage modes of the rest of the mapping queues to obtain a plurality of second mapping queues, wherein the storage modes of the plurality of second mapping queues are mixed storage modes;
setting an internal buffer storage threshold and a mixed buffer storage threshold of the plurality of second mapping queues;
the switching chip switches and applies the first mapping queues and the second mapping queues to store the messages input into the switching chip in an internal buffer of the switching chip and an external buffer of the switching chip according to the flow state of the messages input into the switching chip;
the switching chip switches and applies the first mapping queues and the second mapping queues to store the messages input into the switching chip in the internal buffer of the switching chip and the external buffer of the switching chip according to the traffic state of the messages input into the switching chip, and the switching chip comprises the following substeps:
when the flow state of the input message of the exchange chip is a stable state, the input message of the exchange chip does not meet the requirements of the internal buffer storage threshold and the mixed buffer storage threshold of the second mapping queue, and the exchange chip applies the plurality of first mapping queues and the plurality of second mapping queues to store the message in the internal buffer of the exchange chip;
when the traffic state of the input message of the exchange chip is a burst state, the input message of the exchange chip meets the requirements of an internal buffer storage threshold and a mixed buffer storage threshold of the second mapping queue, the exchange chip applies the first mapping queue to store the message input into the internal buffer of the exchange chip, and the exchange chip applies the plurality of second mapping queues to store the message input into the internal buffer of the exchange chip and the external buffer of the exchange chip.
2. The method for dynamically storing messages of a switching chip according to claim 1, wherein, in said mapping queues, said plurality of mapping queues are mapped
And clearing residual messages of the mapping queues before the storage mode of the columns is set.
3. The method for dynamically storing messages in a switching chip according to claim 1, wherein said switching chip is provided with
A plurality of mapping queues comprising the sub-steps of:
based on 802.1q protocol, configuring the priority of the message input into the exchange chip to a plurality of priority templates through external software;
mapping the priority templates to the queues to obtain mapping queues.
4. The method for dynamically storing messages in a switch chip as recited in claim 1, wherein said plurality of first mapping queues are all high priority queues.
5. The method for dynamically storing messages in a switch chip as recited in claim 1, wherein said plurality of second mapping queues are low priority queues.
6. The method for dynamically storing the messages in the switch chip according to claim 1, wherein the setting rules of the internal buffer storage threshold and the mixed buffer storage threshold of the plurality of second mapping queues are as follows:
the mixed buffer storage threshold is larger than the sum of the internal buffer storage threshold and the maximum transmission unit of the exchange chip;
when the statistics of the internal buffer messages input into the exchange chip reaches the internal buffer storage threshold, the exchange chip uses the plurality of second mapping queues to store the messages input into the exchange chip in the external buffer of the exchange chip;
when the statistics of the internal buffer messages of the exchange chip is smaller than the internal buffer storage threshold value and the sum of the statistics of the internal buffer messages and the statistics of the external messages of the exchange chip is smaller than the mixed buffer storage threshold value, the exchange chip uses the plurality of second mapping queues to store the messages which are subsequently input into the exchange chip in the internal buffer of the exchange chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210119985.4A CN114415969B (en) | 2022-02-09 | 2022-02-09 | Method for dynamically storing messages of exchange chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210119985.4A CN114415969B (en) | 2022-02-09 | 2022-02-09 | Method for dynamically storing messages of exchange chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114415969A CN114415969A (en) | 2022-04-29 |
| CN114415969B true CN114415969B (en) | 2023-09-29 |
Family
ID=81278408
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210119985.4A Active CN114415969B (en) | 2022-02-09 | 2022-02-09 | Method for dynamically storing messages of exchange chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114415969B (en) |
Citations (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6148382A (en) * | 1996-12-23 | 2000-11-14 | Emc Corporation | Arrangement for filtering data item updates to reduce the number of updates to a data item to be stored on mass data storage facility |
| CN1411211A (en) * | 2002-04-17 | 2003-04-16 | 华为技术有限公司 | Ethernet exchange chip output queue management and dispatching method and device |
| CN102480426A (en) * | 2010-11-25 | 2012-05-30 | 迈普通信技术股份有限公司 | Communication method based on peripheral component interconnect-express (PCIE) switching bus and PCIE switching system |
| CN103152281A (en) * | 2013-03-05 | 2013-06-12 | 中国人民解放军国防科学技术大学 | Two-level switch-based load balanced scheduling method |
| CN103763215A (en) * | 2014-01-10 | 2014-04-30 | 迈普通信技术股份有限公司 | Chip array priority mapping method and system |
| CN103902474A (en) * | 2014-04-11 | 2014-07-02 | 华中科技大学 | Mixed storage system and method for supporting solid-state disk cache dynamic distribution |
| AU2014200239A1 (en) * | 2013-11-08 | 2015-05-28 | Tata Consultancy Services Limited | System and method for multiple sender support in low latency fifo messaging using rdma |
| CN104796352A (en) * | 2015-03-20 | 2015-07-22 | 汉柏科技有限公司 | Method for using network card DCB to perform speed limit to improve use experience |
| CN105743814A (en) * | 2016-01-22 | 2016-07-06 | 盛科网络（苏州）有限公司 | Network chip memory management method |
| WO2017067215A1 (en) * | 2015-10-21 | 2017-04-27 | 深圳市中兴微电子技术有限公司 | Method and system for packet scheduling using many-core network processor and micro-engine thereof, and storage medium |
| CN109547352A (en) * | 2018-11-07 | 2019-03-29 | 杭州迪普科技股份有限公司 | The dynamic allocation method and device of packet buffer queue |
| WO2019232694A1 (en) * | 2018-06-05 | 2019-12-12 | 华为技术有限公司 | Queue control method, device and storage medium |
| CN110995598A (en) * | 2019-11-12 | 2020-04-10 | 芯创智（北京）微电子有限公司 | Variable-length message data processing method and scheduling device |
| CN111092829A (en) * | 2019-12-09 | 2020-05-01 | 昆高新芯微电子(江苏)有限公司 | Multi-core switching chip based on switching architecture and data transmission method thereof |
| CN113206800A (en) * | 2021-03-15 | 2021-08-03 | 新华三信息安全技术有限公司 | Message caching method and device and network equipment |
| CN113590199A (en) * | 2021-01-28 | 2021-11-02 | 腾讯科技（深圳）有限公司 | Instruction scheduling method, artificial intelligence chip, computer device and storage medium |
| CN113904997A (en) * | 2021-10-21 | 2022-01-07 | 烽火通信科技股份有限公司 | Method and device for caching and scheduling multi-priority service at receiving end of switching chip |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7751422B2 (en) * | 2006-03-29 | 2010-07-06 | Intel Corporation | Group tag caching of memory contents |
| US8977997B2 (en) * | 2013-03-15 | 2015-03-10 | Mentor Graphics Corp. | Hardware simulation controller, system and method for functional verification |
| US9361227B2 (en) * | 2013-08-30 | 2016-06-07 | Soft Machines, Inc. | Systems and methods for faster read after write forwarding using a virtual address |
-
2022
- 2022-02-09 CN CN202210119985.4A patent/CN114415969B/en active Active
Patent Citations (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6148382A (en) * | 1996-12-23 | 2000-11-14 | Emc Corporation | Arrangement for filtering data item updates to reduce the number of updates to a data item to be stored on mass data storage facility |
| CN1411211A (en) * | 2002-04-17 | 2003-04-16 | 华为技术有限公司 | Ethernet exchange chip output queue management and dispatching method and device |
| CN102480426A (en) * | 2010-11-25 | 2012-05-30 | 迈普通信技术股份有限公司 | Communication method based on peripheral component interconnect-express (PCIE) switching bus and PCIE switching system |
| CN103152281A (en) * | 2013-03-05 | 2013-06-12 | 中国人民解放军国防科学技术大学 | Two-level switch-based load balanced scheduling method |
| AU2014200239A1 (en) * | 2013-11-08 | 2015-05-28 | Tata Consultancy Services Limited | System and method for multiple sender support in low latency fifo messaging using rdma |
| CN103763215A (en) * | 2014-01-10 | 2014-04-30 | 迈普通信技术股份有限公司 | Chip array priority mapping method and system |
| CN103902474A (en) * | 2014-04-11 | 2014-07-02 | 华中科技大学 | Mixed storage system and method for supporting solid-state disk cache dynamic distribution |
| CN104796352A (en) * | 2015-03-20 | 2015-07-22 | 汉柏科技有限公司 | Method for using network card DCB to perform speed limit to improve use experience |
| WO2017067215A1 (en) * | 2015-10-21 | 2017-04-27 | 深圳市中兴微电子技术有限公司 | Method and system for packet scheduling using many-core network processor and micro-engine thereof, and storage medium |
| CN105743814A (en) * | 2016-01-22 | 2016-07-06 | 盛科网络（苏州）有限公司 | Network chip memory management method |
| WO2019232694A1 (en) * | 2018-06-05 | 2019-12-12 | 华为技术有限公司 | Queue control method, device and storage medium |
| CN109547352A (en) * | 2018-11-07 | 2019-03-29 | 杭州迪普科技股份有限公司 | The dynamic allocation method and device of packet buffer queue |
| CN110995598A (en) * | 2019-11-12 | 2020-04-10 | 芯创智（北京）微电子有限公司 | Variable-length message data processing method and scheduling device |
| CN111092829A (en) * | 2019-12-09 | 2020-05-01 | 昆高新芯微电子(江苏)有限公司 | Multi-core switching chip based on switching architecture and data transmission method thereof |
| CN113590199A (en) * | 2021-01-28 | 2021-11-02 | 腾讯科技（深圳）有限公司 | Instruction scheduling method, artificial intelligence chip, computer device and storage medium |
| CN113206800A (en) * | 2021-03-15 | 2021-08-03 | 新华三信息安全技术有限公司 | Message caching method and device and network equipment |
| CN113904997A (en) * | 2021-10-21 | 2022-01-07 | 烽火通信科技股份有限公司 | Method and device for caching and scheduling multi-priority service at receiving end of switching chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114415969A (en) | 2022-04-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7606151B2 (en) | Power reduction in switch architectures | |
| CN111052689B (en) | Hybrid packet memory for buffering packets in a network device | |
| US20220210071A1 (en) | Network congestion control method, node, system, and storage medium | |
| US10419370B2 (en) | Hierarchical packet buffer system | |
| CN113726671B (en) | Network congestion control method and related products | |
| JPH05508283A (en) | Low latency or low loss switch for ATM | |
| US20230164078A1 (en) | Congestion Control Method and Apparatus | |
| US8223788B1 (en) | Method and system for queuing descriptors | |
| EP3657744B1 (en) | Message processing | |
| EP3188419B1 (en) | Packet storing and forwarding method and circuit, and device | |
| CN114415969B (en) | Method for dynamically storing messages of exchange chip | |
| CN114531488B (en) | High-efficiency cache management system for Ethernet switch | |
| US7822051B1 (en) | Method and system for transmitting packets | |
| WO2023155815A1 (en) | Packet processing method, apparatus, terminal device, and storage medium | |
| CN104022961A (en) | Data transmission method, apparatus and system | |
| US20100238946A1 (en) | Apparatus for processing packets and system for using the same | |
| US11388115B2 (en) | Circuit within switch and method for managing memory within switch | |
| CN116346720A (en) | Information transmission device and method | |
| US20130107891A1 (en) | Target issue intervals | |
| CN111371692A (en) | Window control method and device based on TCP (Transmission control protocol) and electronic equipment | |
| JP2006174265A (en) | Stream packet receiver | |
| CN115695311A (en) | RoCE v2 network environment flow control method, system and storage medium | |
| WO2021253999A1 (en) | Data access method and apparatus, chip and computer storage medium | |
| US20230236975A1 (en) | Apparatus for managing buffers and method thereof | |
| US20040146059A1 (en) | Method for controlling the bandwidth of a bridge device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 3 / F, 665 Zhangjiang Road, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai Patentee after: Yunhe Zhiwang (Shanghai) Technology Co.,Ltd. Country or region after: China Address before: 311203 floor 12, building 2, Purple Orange International Center, No. 39, Jincheng Road, Xiaoshan District, Hangzhou, Zhejiang Province Patentee before: Hangzhou yunhezhi Network Technology Co.,Ltd. Country or region before: China |
|
| CP03 | Change of name, title or address |