CN111092829A - Multi-core switching chip based on switching architecture and data transmission method thereof - Google Patents
Multi-core switching chip based on switching architecture and data transmission method thereof Download PDFInfo
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- CN111092829A CN111092829A CN201911252160.4A CN201911252160A CN111092829A CN 111092829 A CN111092829 A CN 111092829A CN 201911252160 A CN201911252160 A CN 201911252160A CN 111092829 A CN111092829 A CN 111092829A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/109—Integrated on microchip, e.g. switch-on-chip
Abstract
The invention discloses a multi-core exchange chip based on exchange architecture and a data transmission method thereof, wherein the multi-core exchange chip comprises: more than two single-core packet processors and more than one switching fabric; the interconnection or concurrent transmission between every two single-core packet processors is realized through a switching architecture; each single-core packet processor comprises an IPE module, a queue management module and an EPE module; the transmission method comprises the following steps: the data transmission method S1 comprises the steps of processing a data packet to obtain a data packet head, and sending the data packet head to an IPE module to obtain data packet information; and S2, judging a target transmission address of the data packet according to the data packet information, and realizing enqueuing and dequeuing according to the target transmission address so as to complete transmission of the data packet. The invention has simple logic, is very consistent with single-core logic, has lower design difficulty, is easy to expand and has strong practicability.
Description
Technical Field
The invention relates to the technical field of network communication, in particular to a multi-core switching chip based on a switching architecture and a data transmission method thereof.
Background
A Switching Fabric (Switching Fabric) is a cross-bar network implemented by using a new-generation Switching device in combination with a cross-bar packet technology, and multiple point-to-point communication links in the system are organized together, so that finally, any interconnection and concurrent transmission among all chips or modules can be realized, and the system bandwidth is multiplied accordingly.
With the increase of technology and demand, the switching capacity of the switching chip has been in the era of rapid development from 8G to 32T. The speed is increased to more than 4000 times, while the interface is raised from 1G to 400G, the speed is increased to 400 times, however, these changes bring about the following two problems for the person skilled in the art:
1) insufficient RAM bandwidth
At present, the high-end switching chip mainly costs the RAM and the SERDES, and for a switching capacity of 1T, if one RAM is accessed only once, the RAM needs to be run to 1.5M × 1000 ═ 1.5G, and for a capacity of 32T, the RAM needs to be run to 32 × 1.5G ═ 48G, which is a bandwidth heard by a hacker.
2) The chip is IO limited and no longer Die Size limited
The high-speed SERDES is a technology which must be used by a high-speed chip, the electrical characteristics of the high-speed SERDES determine that the high-speed SERDES can be arranged around the chip only, and although 2.5D or even 3D packaging technology exists, the Die Size is very large due to the fact that the high-speed SERDES are too much, and IO limitation of the chip is very obvious.
Therefore, it is an urgent need to solve the problem of the art to design a high-speed and high-bandwidth multi-core switch chip based on a switch architecture and a data transmission method thereof.
Disclosure of Invention
In view of this, the present invention provides a multi-core switch chip based on a switch architecture and a data transmission method thereof, and the method expands the switch chip from a single core to a multi-core through a non-blocking switch architecture, so as to solve the problems of small switch capacity and low speed of the switch chip in the prior art.
In order to achieve the purpose, the invention adopts the following technical scheme:
a multi-core switch chip based on a switch fabric, comprising: more than two single-core packet processors and more than one switching fabric;
the interconnection or concurrent transmission between every two single-core packet processors is realized through the switching architecture;
each single-core packet processor comprises an IPE module, a queue management module and an EPE module;
the IPE module is an entrance processing engine module, is connected with the queue management module and is used for generating data packet information according to a data packet and sending the data packet information to the queue management module;
the queue management module is used for realizing the enqueuing and the dequeuing of the data packet information;
the EPE module is an exit processing engine module, is connected with the queue management module and is used for searching a buffer area and extracting a message;
the queue management module is further connected with the switching architecture, and the switching architecture is used for connecting the two single-core packet processors.
Preferably, the IPE module includes the core processor IPE and the virtual core processor IPE, and the queue management module includes the core data packet buffer, the virtual core data packet buffer and the VoQ interface;
the local core processor IPE is connected with the local core data packet buffer, and the virtual core processor IPE is connected with the virtual core data packet buffer;
the VoQ interface is connected with the EPE module and the exchange framework.
Preferably, the core processor IPE includes a buffer memory, and the buffer memory is connected to the core packet buffer.
A data transmission method of a multi-core switching chip based on a switching architecture comprises the following steps:
s1, processing a data packet to obtain a data packet head, and sending the data packet head to an IPE module to obtain data packet information;
and S2, judging a target transmission address of the data packet according to the data packet information, and enabling the data packet information to be enqueued and dequeued according to the target transmission address so as to complete transmission of the data packet.
Preferably, the specific contents of S1 include:
and after entering the IPE module, the data packet is cached in the core data packet cache through a cache memory, the data packet head of the data packet is obtained in the core data packet cache, the data packet head is transmitted to the core processor IPE, and data packet information is generated in the core processor IPE.
Preferably, the specific contents of S2 include:
s21, judging whether a target transmission address is a single-core packet processor where the data packet information is located currently;
s211, if yes, enqueuing in a queue management module of the current single-core packet processor, and dequeuing in an EPE module of the current single-core packet processor;
s222, if not, sending the data packet and the data packet information to a target single-core packet processor through an exchange architecture, enqueuing in a queue management module in the target single-core packet processor, and dequeuing in an EPE module of the target single-core packet processor;
and S22, the EPE module carries out buffer area retrieval on the core data packet buffer, extracts the message and returns the packet buffer.
Preferably, the specific contents of S212 include:
the target transmission address of the data packet is not the current single-core packet processor, buffer area retrieval is carried out on a VoQ interface in the current single-core packet processor, and the data packet and data packet information are simultaneously transmitted to the target single-core packet processor through an exchange architecture;
and while buffer retrieval is carried out on the VoQ interface, buffer retrieval is carried out in a virtual core processor IPE in the current single-core packet processor through a virtualization technology, and the data packet is cached in a corresponding virtual core data packet buffer.
Preferably, the specific contents of enqueuing in S2 include:
judging a communication mode according to the data packet information, and if the communication mode is a unicast mode, directly enqueuing in a queue management module; and if the communication mode is multicast, the data packet information is subjected to multicast replication and then enqueued.
Preferably, the packet information is subjected to traffic shaping and scheduling before dequeuing.
Compared with the prior art, the multi-core switching chip based on the switching architecture and the data transmission method thereof disclosed by the invention have the advantages that:
1. the invention has simple logic, lower design difficulty, is very consistent with single-core logic, and is easier in software development;
the Switching Fabric technology is mature, and many companies have development capacity, simple structure, stable work and strong reliability;
3. most multi-core chips are limited by technology, and 2, 4, 8, 16 cores and the like are generally adopted, but the architecture in the invention is easy to expand and can be expanded into 3, 5 cores and the like.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a multi-core switch chip based on a switch architecture according to the present invention;
FIG. 2 is a flowchart illustrating a method for transmitting data of a multi-core switch chip based on a switch fabric according to the present invention;
fig. 3 is a schematic diagram illustrating a specific flow of S2 in the data transmission method of a multi-core switch chip based on a switch architecture according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention discloses a multi-core exchange chip based on an exchange architecture, which comprises: more than two single-core packet processors and more than one switching fabric;
the interconnection or concurrent transmission between every two single-core packet processors is realized through a switching architecture;
each single-core packet processor comprises an IPE module, a queue management module and an EPE module;
the IPE module is an entrance processing engine module, is connected with the queue management module and is used for generating data packet information according to the data packet and sending the data packet information to the queue management module;
the queue management module is used for realizing the enqueuing and the dequeuing of the data packet information;
the EPE module is an exit processing engine module, is connected with the queue management module and is used for searching a buffer area and extracting the message;
the queue management module is also connected with a switching architecture, and the switching architecture is used for connecting the two single-core packet processors.
In order to further realize the technical scheme, the IPE module comprises the core processor IPE and the virtual core processor IPE, and the queue management module comprises the core data packet buffer, the virtual core data packet buffer and a VoQ interface;
the IPE is connected with the core data packet buffer, and the IPE is connected with the virtual core data packet buffer;
the VoQ interface is connected with the EPE module and is connected with the switching framework.
In order to further implement the above technical solution, the core processor IPE includes a buffer memory, and the buffer memory is connected to the core packet buffer.
Fig. 1 discloses a 2-core switch chip based on the present invention, in which a core one and a core two respectively refer to two single-core packet processors, a core one packet buffer is a core data packet buffer in the core one, a core two packet buffer virtually mapped is a core two virtual core packet buffer in the core one, a core one IPE is a core processor IPE of the core one, a core two IPE virtually mapped is a core two virtual core processor IPE in the core one, and the meaning of each module in the core two is analogized.
A data transmission method of a multi-core switching chip based on a switching architecture comprises the following steps:
s1, processing a data packet to obtain a data packet head, and sending the data packet head to an IPE module to obtain data packet information;
and S2, judging a target transmission address of the data packet according to the data packet information, and enabling the data packet information to be enqueued and dequeued according to the target transmission address so as to complete transmission of the data packet.
In order to further implement the above technical solution, the specific content of S1 includes:
after entering the IPE module, the data packet is cached in the core data packet cache through the cache memory, the data packet head of the data packet is obtained in the core data packet cache, the data packet head is transmitted to the core processor IPE, and data packet information is generated in the core processor IPE.
In order to further implement the above technical solution, the specific content of S2 includes:
s21, judging whether a target transmission address is a single-core packet processor where the current data packet information is located;
s211, if yes, enqueuing in a queue management module of the current single-core packet processor, and dequeuing in an EPE module of the current single-core packet processor;
s212, if not, sending the data packet and the data packet information to the target single-core packet processor through the exchange architecture, enqueuing in a queue management module in the target single-core packet processor, and dequeuing in an EPE module of the target single-core packet processor;
and S22, the EPE module carries out buffer area retrieval on the core data packet buffer, extracts the message and returns the packet buffer.
In order to further implement the above technical solution, the specific content of S212 includes:
the target transmission address of the data packet is not the current single-core packet processor, buffer area retrieval is carried out on a VoQ interface in the current single-core packet processor, and the data packet and data packet information are simultaneously transmitted to the target single-core packet processor through an exchange architecture;
and while buffer retrieval is carried out on the VoQ interface, buffer retrieval is carried out in a virtual core processor IPE in the current single-core packet processor through a virtualization technology, and the data packet is cached in a corresponding virtual core data packet buffer.
In order to further implement the above technical solution, the specific contents of enqueuing in S2 include:
judging a communication mode according to the data packet information, and if the communication mode is unicast, directly enqueuing in a queue management module; and if the communication mode is multicast, the data packet information is subjected to multicast replication and then enqueued.
In order to further realize the technical scheme, flow shaping and scheduling are carried out before dequeuing of the data packet information.
For the 2-core switching chip, the specific process of transmitting data from the core to the core two is as follows:
the data packet enters a media interface from a serial deserializer of the first core, so that the data packet enters the first core IPE module, the data packet is cached in a first core data packet buffer through a buffer memory, a data packet head of the data packet is obtained in the first core data packet buffer, the data packet head is transmitted to the IPE module, and data packet information is generated in the IPE module; sending the data packet and the data packet information to a second core single-core packet processor through a switching architecture, enqueuing in a queue management module in the second core, and dequeuing in an EPE module in the second core; and carrying out buffer area retrieval on the core data packet buffer, carrying out message extraction and returning to the packet buffer.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A multi-core switch chip based on a switch fabric, comprising: more than two single-core packet processors and more than one switching fabric;
the interconnection or concurrent transmission between every two single-core packet processors is realized through the switching architecture;
each single-core packet processor comprises an IPE module, a queue management module and an EPE module;
the IPE module is an entrance processing engine module, is connected with the queue management module and is used for generating data packet information according to a data packet and sending the data packet information to the queue management module;
the queue management module is used for realizing the enqueuing and the dequeuing of the data packet information;
the EPE module is an exit processing engine module, is connected with the queue management module and is used for searching a buffer area and extracting a message;
the queue management module is further connected with the switching architecture, and the switching architecture is used for connecting the two single-core packet processors.
2. The multi-core switch chip based on the switch architecture of claim 1,
the IPE module comprises a core processor IPE and a virtual core processor IPE, and the queue management module comprises a core data packet buffer, a virtual core data packet buffer and a VoQ interface;
the local core processor IPE is connected with the local core data packet buffer, and the virtual core processor IPE is connected with the virtual core data packet buffer;
the VoQ interface is connected with the EPE module and the exchange framework.
3. The switch fabric-based multi-core switch chip of claim 1, wherein the core processor IPE comprises a buffer memory, and the buffer memory is connected to the core packet buffer.
4. A data transmission method of a multi-core switching chip based on a switching architecture is characterized by comprising the following steps:
s1, processing a data packet to obtain a data packet head, and sending the data packet head to an IPE module to obtain data packet information;
and S2, judging a target transmission address of the data packet according to the data packet information, and realizing enqueuing and dequeuing according to the target transmission address so as to complete transmission of the data packet.
5. The method according to claim 4, wherein the specific content of S1 includes:
and after entering the IPE module, the data packet is cached in the core data packet cache through a cache memory, the data packet head of the data packet is obtained in the core data packet cache, the data packet head is transmitted to the core processor IPE, and data packet information is generated in the core processor IPE.
6. The method according to claim 4, wherein the specific content of S2 includes:
s21, judging whether a target transmission address is a single-core packet processor where the data packet information is located currently;
s211, if yes, enqueuing in a queue management module of the current single-core packet processor, and dequeuing in an EPE module of the current single-core packet processor;
s212, if not, the data packet and the data packet information are both sent to a target single-core packet processor through an exchange architecture, and the data packet information are enqueued in a queue management module in the target single-core packet processor and dequeued in an EPE module of the target single-core packet processor;
and S22, the EPE module carries out buffer area retrieval on the core data packet buffer, extracts the message and returns the packet buffer.
7. The method according to claim 5, wherein the specific content of S212 includes:
the target transmission address of the data packet is not the current single-core packet processor, buffer area retrieval is carried out on a VoQ interface in the current single-core packet processor, and the data packet and data packet information are simultaneously transmitted to the target single-core packet processor through an exchange architecture;
and while buffer retrieval is carried out on the VoQ interface, buffer retrieval is carried out in a virtual core processor IPE in the current single-core packet processor through a virtualization technology, and the data packet is cached in a corresponding virtual core data packet buffer.
8. The method according to claim 4, wherein the specific contents of enqueuing in S2 include:
judging a communication mode according to the data packet information, and if the communication mode is a unicast mode, directly enqueuing in a queue management module; and if the communication mode is multicast, the data packet information is subjected to multicast replication and then enqueued.
9. The method according to claim 4, wherein the packet information is subjected to traffic shaping and scheduling before dequeuing.
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