JP2006174265A - Stream packet receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an economical stream packet receiver in which an expensive memory means for reception packets can be saved. <P>SOLUTION: In the stream packet receiver (SPR1), a packet length detector (107) detects lengths of all reception packets and based on detected reception packet length information, a DMA controller (102) transfers reception packet of which the length is shorter than a preset length, in the packets received from a network, to a first memory (104) and transfers reception packets of which the length is equal with or longer than said length, to a second memory (105). <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to stream packet reception on the receiving side of a device that transmits temporally continuous information such as audio and moving image, generally called stream information, over a network, and in particular, a large number of functions are generally integrated on one chip. The present invention relates to a stream packet receiving apparatus suitable for a multi-function LSI called a system LSI.

  The basic elements in a network transmission / reception apparatus are a CPU (central processing unit) that handles information to be transmitted / received in the apparatus, a controller that transmits / receives a packet to / from a data link constituting the network, and a transmission packet that includes information to be transmitted. Or a main memory for storing and storing received packets arriving from the network.

  As the main memory, a DRAM (dynamic RAM) having a small physical dimension per capacity and low cost is generally used. DRAM has a relatively long latency as a structural characteristic. In other words, it takes a long time from when the data output request occurs until the data actually returns in response to the request. However, since the size of data that can be requested at one time can be increased, the data input / output rate per unit time, that is, the bandwidth is not low.

  When accessing the memory constituted by the DRAM from the CPU, data cannot be read and written with the latency required by the CPU. Therefore, a high-speed small-capacity SRAM (static RAM) called a cache memory is separately provided between the CPU and the main memory. ) A buffer composed of a memory is provided, and mutual data transfer is adjusted.

  Memory access generated by the CPU is characterized by high locality and repeatability. Once information is stored in the cache memory, the frequency of access to the main memory having a long latency can be significantly reduced. It becomes possible. As a result, the CPU can access the memory without being bothered by the latency of the DRAM.

  By the way, when a packet received from the network is handled, a header is discriminated in order to identify the packet, or a checksum is inspected to detect an error. Although this operation also has high data localization, it cannot be said that the repeatability is high because received packets arrive one after another.

  In other words, since the controller sequentially transfers packets received to different areas on the main memory, the information stored in the cache memory becomes invalid and must be read from the DRAM with a long latency each time. During that time, the CPU waits. This is recognized as a significant performance degradation compared to the level expected from the processing performance achieved by the CPU in combination with the cache memory.

  Naturally, the processing speed can be increased by replacing the main memory of the network transmission / reception device with an SRAM having a short latency. And since SRAM is comprised only from a transistor, the special manufacturing process like DRAM which consists of a transistor and a capacitor | condenser is not required. In addition, since the memory holding operation required in the DRAM is unnecessary, it is suitable for integration on a multi-function LSI called a system LSI.

However, since SRAM requires a larger number of semiconductor elements than DRAM, the cost per storage capacity is higher than that of DRAM. Therefore, simply replacing the DRAM with the SRAM is extremely uneconomical for the construction of the device itself. Therefore, in order to improve the processing efficiency of the received packet, a configuration in which the CPU can access the received packet on the intermediate buffer existing between the controller and the main memory (for example, Patent Document 1), or the controller is main. A configuration has been proposed in which received packets can be transferred to a cache memory instead of a memory (for example, Patent Document 2).
In any of the configurations, an existing short-latency memory unit is used in a network transmission / reception apparatus to increase the processing speed of a received packet.
JP-A-9-101931 (page 8, FIG. 1) JP 2002-278834 A (page 11, FIG. 1)

  However, in either case, even if the received packet is on a memory with a short latency, it is temporary and is moved to the main memory with a long latency for a reason unrelated to the receiving operation from the network. I can't prevent that.

  In the former configuration in which the received packet on the intermediate buffer can be accessed, the received packet on the memory with a short latency is unintentionally main by unintentionally, for example, due to the occurrence of data transfer from an I / O device other than the network interface. It will be moved to memory. Similarly, even in the configuration in which the received packet can be transferred to the latter cache memory, for example, the received packet on the memory having a short latency is unintentionally moved to the main memory by reading the CPU instruction word from the main memory. Will be.

  That is, in any case, since the intermediate buffer or the cache memory is used as a received packet buffer for a purpose different from the original purpose, the effect of speeding up the received packet processing must be limited. Absent.

  The present invention solves the above-mentioned problems in the prior art, and can provide a memory means with a short latency for the received packet to improve the processing performance of the received packet. At the same time, the statistical properties of the received packet can be improved. An object of the present invention is to provide an economical stream packet receiving apparatus that can save expensive memory means for received packets.

The present invention is a stream packet receiving device comprising:
First memory means for storing a part of received packets coming from the network to the receiving device;
Second memory means for storing received packets other than those stored in the first memory means;
A packet length inspection means for detecting the length of all received packets;
Receiving the received packet length information output from the packet length inspection means, among the packets received from the network, transfer a received packet having a length less than a preset length to the first memory means, and the length equal to or greater than the length DMA means for transferring the received packet to the second memory means.

  Provide low-latency memory means for received packets, improve received packet processing performance, and at the same time save the expensive memory means for received packets by utilizing the statistical properties of received packets It is possible to provide an economical stream packet receiving apparatus that can perform the above.

  Prior to specific description of the stream packet receiving apparatus according to the embodiment of the present invention, first, statistical characteristics of received packets handled by the stream packet receiving apparatus will be described with reference to FIG. 5 and FIG. FIGS. 5 and 6 show histograms representing the relationship between the length of received packets received and their appearance frequencies when communicating with other devices via Ethernet (registered trademark). That is, FIG. 5 shows a histogram in a state where a packet from another specific transmission device on the network is received, and FIG. 6 shows a histogram in a state where a transmission packet from another device is not received. Show.

  What can be read from FIG. 5 is that the size of the received packet when communicating with other devices is bipolarized between short and long. Short received packets having a length of 96 bytes or less occupy about 1/2 of the whole, and long received packets close to the maximum length determined by the Ethernet (registered trademark) standard are about 1/3.

  This is because short packets frequently cause exchange of control signals with a communication partner device, for example, packet reception confirmation. A long packet is a packet that contains a portion of data carried by some transport protocol. Stream data usually has a data size that is greater than or equal to the maximum transfer length that can be carried in one packet, and is therefore divided into a number of packets and transmitted. In order to minimize the overhead that is divided on the transmission side and combined on the reception side, the packet length tends to be as long as possible. Among the above, if the speed of the reception confirmation process carried by a short packet can be increased, it is possible to improve the maximum transmission speed by the TCP protocol that performs transmission while confirming the reception of the transmitted data.

  Next, what can be read from FIG. 6 is that the length of the received packet when not communicating with a specific device tends to be short. In the case shown in FIG. 6, only a packet of 96 bytes or less is nearly 90% of all received packets. These short received packets are generally broadcast communication packets that are used when a communication partner cannot be specified or when communicating simultaneously with a plurality of devices.

  However, most of the broadcast communications are not destined for the self-receiving device, and when these unnecessary packets are received, the packets should be quickly discarded. As a result, it is possible to reduce the processing load related to the management of received packets and to improve the utilization efficiency of the memory holding the received packets.

  As described above, whether or not the communication is performed with a specific device, the length of the received packet does not exist uniformly within the possible range, but is biased toward a short packet. In addition, improvement in processing performance for short packets greatly contributes to improvement in received packet processing performance of the entire apparatus. Therefore, in the present invention, the statistical characteristics of the received packet are used to improve the received packet processing performance by allocating a memory, for example, SRAM, which is expensive for processing a short received packet but has a short latency. is there. Further, since a small memory capacity is required for processing a short received packet, it is possible to do this economically.

(First embodiment)
With reference to FIG. 1, description will be given of a stream packet reception device SPR1 according to the first embodiment of the present invention. In the stream packet receiving device SPR 1, a received packet arriving from the network is received by the network controller 101, and transferred to the SRAM 104 or DRAM 105 via the bus 103 by the DMA controller 102. When the transfer is completed, the DMA controller 102 notifies the CPU 106 to that effect.

  Upon receiving the notification, the CPU 106 accesses the SRAM 104 or DRAM 105 in which the received packet is stored, and performs necessary processing. Then, the CPU 106 also sets an address on the SRAM 104 and an address on the DRAM 105 as a transfer destination address for DMA transfer to the DMA controller 102.

  In FIG. 1, the code | symbol 107 has shown the packet length detector which detects the length of a received packet. The packet length detector 107 instructs the DMA controller 102 on the transfer destination of the DMA transfer based on the detection result. That is, an instruction is given to transfer a received packet having a length less than a preset length to the SRAM 104 and other long received packets to the DRAM 105.

  In this example, the SRAM 104 and the DRAM 105 are assigned different addresses so that the DMA controller 102 and the CPU 106 can explicitly recognize them as different access destinations. The components other than the DRAM 105 are integrated on the same LSI chip 108 indicated by a broken line.

  When a packet arrives at the stream packet reception device SPR1 configured as described above, the DMA controller 102 transfers the packet according to the instruction of the packet length detector 107 as described above, thereby receiving less than a preset length. Packets are stored in the SRAM 104, and other long received packets are stored in the DRAM 105. The SRAM 104 can be accessed with a short latency due to being integrated on the same LSI as the CPU 106. In addition, since only a short received packet needs to be stored, the size may be sufficiently smaller than the size of the area for storing the received packet secured on the DRAM 105.

(Second Embodiment)
With reference to FIG. 2, a description will be given of a stream packet reception device SPR2 according to the second embodiment of the present invention. A received packet that has arrived from the network is received by the network controller 201 and transferred by the DMA controller 202 to the SRAM 204 and the DRAM 205 via the bus 203. When the DMA controller 202 completes the transfer, it notifies the CPU 206 to that effect. In response to the notification, the CPU 206 accesses the SRAM 204 and DRAM 205 in which the received packet is stored, and performs necessary processing. The components other than the DRAM 205 are integrated on the same LSI chip 207 indicated by a broken line.

  Then, the CPU 206 sets an address on the SRAM 204 and an address on the DRAM 205 as a transfer destination address for DMA transfer, to the DMA controller 202. In this example, the DMA controller 202 transfers from the beginning of the received packet to a preset length to the SRAM 204 and a portion exceeding the length to the DRAM 205.

  In the stream packet receiving device SPR2, when a short packet less than a preset length arrives, the DMA controller 202 sequentially transfers the packet from the head of the packet to the SRAM 204 as described above. Since the short received packet ends before reaching a preset length, the entire packet is stored in the SRAM 204 without being transferred to the DRAM 205. Next, when a packet longer than a preset length arrives, the DMA controller 202 transfers the packet from the beginning of the packet to the set length to the SRAM 204, and transfers the part beyond that to the DRAM 205.

  The SRAM 204 stores a short received packet and a head portion of a long received packet. The header of the packet includes a destination area on the network, a port number, and various flags. Therefore, among the long received packet processing, these header processing must also be performed on the SRAM 204 with short latency. Can do. Since the second half of the long received packet is stored in the DRAM 205, the size of the SRAM 204 may be small.

(Third embodiment)
FIG. 3 is a block diagram of a stream packet reception device SPR3 according to the third embodiment of the present invention. As shown in FIG. 3, in the stream packet receiving device SPR3, a received packet that has arrived from the network is received by the network controller 301 and transferred to the SRAM 304 via the bus 303 by the first DMA controller 302. When the first DMA controller 302 completes the transfer, it notifies the CPU 306 to that effect.

  In response to the notification from the first DMA controller 302, the CPU 306 accesses the SRAM 304 in which the received packet is stored, and checks whether or not the received packet stored therein includes a data portion carried by the transport protocol. . If not included, the received packet is processed on the SRAM 304.

  If the received packet includes a data portion, the CPU 306 instructs the second DMA controller 307 to transfer from the SRAM 304 to the DRAM 305. When the second DMA controller 307 completes the transfer, it notifies the CPU 306 accordingly. In response to the notification from the second DMA controller 307, the CPU 306 accesses the DRAM 305 in which the received packet is stored, and processes the received packet including the data portion stored therein.

  The CPU 306 also sets an address on the SRAM 204 as the transfer destination address for performing the DMA transfer to the first DMA controller 302. The components other than the DRAM 305 are integrated on the same LSI chip 308 indicated by a broken line. In the stream packet receiving device SPR3, processing of a short packet that does not include a data portion carried by a transport protocol that occupies most of the received packet can be performed on the SRAM 304 with a short latency. Since the second DMA controller 307 transfers a long packet to the DRAM 305, the size of the SRAM 204 may be small.

(Fourth embodiment)
With reference to FIG. 4, a stream packet reception device SPR4 according to a fourth embodiment of the present invention will be described. In the stream packet receiving device SPR4, a received packet that has arrived from the network is received by the network controller 401, and transferred by the DMA controller 402 to the SRAM 404 or DRAM 405 via the bus 403. When the transfer is completed, the DMA controller 402 notifies the CPU 406 accordingly.

  In response to the notification from the DMA controller 402, the CPU 406 accesses the SRAM 404 or DRAM 405 in which the received packet is stored, and processes the received packet. The components other than the DRAM 405 are integrated on the same LSI chip 407 indicated by a broken line. The CPU 406 also designates the SRAM 404 or the DRAM 405 as a transfer destination for performing DMA transfer to the DMA controller 402. At this time, if transfer to the SRAM 404 is possible, the SRAM 404 is always designated as the transfer destination. That is, the SRAM 404 is designated as a transfer destination with a higher priority than the DRAM 405.

  In the stream packet receiver SPR4, a received packet that does not include a data portion carried by the transport protocol, that is, a short packet that occupies most of the received packet can be processed on the SRAM 404 with a short probability with a short latency. . When a large number of received packets arrive in a short period of time and the SRAM 404 cannot be designated as the transfer destination, the received packets are transferred to the DRAM 405, so the size of the SRAM 404 may be small enough to be integrated on the LSI 407. .

  The present invention can be applied to reception of stream packets that are temporally continuous information such as audio and video images that are generally transmitted as stream information and transmitted over a network.

The block diagram which shows the structure of the stream packet receiver which concerns on the 1st Embodiment of this invention The block diagram which shows the structure of the stream packet receiver which concerns on the 2nd Embodiment of this invention The block diagram which shows the structure of the stream packet receiver concerning the 3rd Embodiment of this invention The block diagram which shows the structure of the stream packet receiver concerning the 4th Embodiment of this invention Histogram for each packet length of received packets during communication with a specific device Histogram for each packet length of received packets when not communicating with a specific device

Explanation of symbols

101 Network controller 102 DMA controller 103 Bus 104 SRAM
105 DRAM
106 CPU
107 packet length detector 108 LSI
201 Network controller 202 DMA controller 203 Bus 204 SRAM
205 DRAM
206 CPU
207 LSI
301 Network Controller 302 First DMA Controller 303 Bus 304 SRAM
305 DRAM
306 CPU
307 Second DMA controller 308 LSI
401 Network controller 402 DMA controller 403 Bus 404 SRAM
405 DRAM
406 CPU
407 LSI

Claims (7)

First memory means for storing a part of received packets coming from the network to the receiving device;
Second memory means for storing received packets other than those stored in the first memory means;
A packet length inspection means for detecting the length of all received packets;
Receiving the received packet length information output from the packet length inspection means, among the packets received from the network, transfer a received packet having a length less than a preset length to the first memory means, and the length equal to or greater than the length Stream packet receiving apparatus comprising DMA means for transferring the received packet to the second memory means. First memory means for storing part or all of the received packet;
Second memory means for storing a portion of the received packet that is not stored in the first memory means;
When the received packet received from the network does not exceed a predetermined set length, the entire received packet is transferred to the first memory means. When the set length exceeds the set length, the received packet is divided and A stream packet receiving apparatus comprising DMA means for transferring from the beginning to the set length to the first memory means and transferring the remaining part to the second memory means. First memory means for temporarily storing all received packets arriving at the receiving device from the network;
Inspection means for inspecting a received packet stored in the first memory means;
Second memory means for storing a part of received packets received from the network to the receiving device;
DMA means for transferring the received packet from the first memory means to the second memory means when the inspection means detects that the received packet includes a data portion carried by a transport protocol. Stream packet receiver. First memory means for storing a part of received packets coming from the network to the receiving device;
Second memory means for storing received packets other than those stored in the first memory means;
Empty buffer detection means for detecting the usage status of the first memory means and the second memory means;
In response to the usage status information output from the empty buffer detecting means, if the first memory means is available, the received packet is transferred to the first memory means, and the first memory means is free. A stream packet receiving apparatus comprising DMA means for transferring the received packet to the second memory means.   5. The stream packet receiving apparatus according to claim 1, wherein the first memory means is a static RAM.   5. The stream packet receiving apparatus according to claim 1, wherein the first memory means is integrated on the same integrated circuit as the DMA means. 5. The stream packet receiving apparatus according to claim 1, wherein the second memory means is a dynamic RAM.

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