CN114414066B - Infrared imaging reading special integrated circuit and infrared imager - Google Patents
Infrared imaging reading special integrated circuit and infrared imager Download PDFInfo
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- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
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- H—ELECTRICITY
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- G—PHYSICS
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- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
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Abstract
The invention provides an infrared imaging reading special integrated circuit and an infrared imager, and relates to the field of special integrated circuits. The method comprises the following steps: the device comprises a ring oscillator, a sampling unit and a counter; the ring oscillator includes: a multi-stage inverter; the ring oscillator receives signal current to generate a pulse signal, the pulse signal is transmitted to the counter, and the counter counts the pulse signal to obtain oscillation times; the sampling unit is connected with the multi-level inverter and used for sampling the phase of the multi-level inverter and transmitting the phase to the digital register; and at the end of each analog-to-digital conversion period, storing the phase and the oscillation frequency of the multi-stage inverter in the digital register based on the sampling signal, and outputting the phase and the oscillation frequency through the digital register. The invention has no frequency multiplication operation, thereby greatly reducing the power consumption and complexity of the counter and the sampling circuit. The area overhead and the power consumption of the analog-to-digital conversion circuit are effectively reduced, and the analog-to-digital conversion circuit is extremely suitable for realizing a column-level or pixel-level ADC under a small pixel and an advanced process.
Description
Technical Field
The invention relates to the field of special integrated circuits, in particular to an infrared imaging reading special integrated circuit and an infrared imager.
Background
Infrared imaging is a technique for identifying an object by detecting infrared radiation emitted by the object, and is widely applied to the fields of military, space technology, medicine, and the like. The infrared focal plane array component is a main body of the infrared imaging system and consists of an infrared detector and an infrared focal plane reading circuit. An infrared read-out Application Specific Integrated Circuit (ASIC) is a signal processing system that converts an electrical signal generated by an infrared detector and outputs the converted signal to the outside of a chip. Digital readout schemes are receiving more and more research attention due to their low noise and high accuracy, and analog-to-digital converters are the key technology for digital readout of ASICs.
The basic principle of the present ADC (analog-to-digital converter) architecture based on a ring oscillator is to utilize the characteristic that the oscillation frequency of the ring oscillator is proportional to the control voltage (or current), and obtain a digital code by detecting the frequency (or phase) of the ring oscillator, where the digital code is the result of analog-to-digital conversion. In the whole analog-to-digital conversion process, the ring oscillator replaces a capacitor in the traditional ADC structure and serves as an integrator, the structure is simpler, the size of the oscillator can be reduced along with the reduction of a process node, and compared with capacitance integration, the ring oscillator is more suitable for an advanced process, so that the ring oscillator can be used for realizing the ADC with low power consumption, small area and high precision.
However, the ring oscillator only detects the oscillation frequency of a certain point of the oscillator at present, and the accuracy is lost; if the frequency of the N-stage oscillator is increased by N times by means of frequency multiplication, the power consumption of the counter is also increased by N times. Meanwhile, due to the need of frequency multiplication, a circuit for realizing the frequency multiplication function needs to be additionally added, so that the complexity, the area overhead and the power consumption of the equipment are indirectly increased, and the miniaturization of the ADC is not facilitated.
Disclosure of Invention
The invention provides an infrared imaging reading special integrated circuit and an infrared imager, and provides a technical scheme for effectively reducing the area overhead and the power consumption of an analog-to-digital conversion circuit without reducing the quantization precision.
A first aspect of an embodiment of the present invention provides an infrared imaging readout asic, where the asic includes: the device comprises a ring oscillator, a sampling unit and a counter;
the ring oscillator includes: a multi-stage inverter;
the ring oscillator receives signal current, generates a pulse signal and transmits the pulse signal to the counter, and the counter counts the pulse signal to obtain oscillation times;
the sampling unit is connected with the multistage phase inverter, is used for sampling the phase of the multistage phase inverter and transmitting the phase to the digital register;
and at the end of each analog-to-digital conversion period, storing the phase of the multistage inverter and the oscillation times in the digital register based on a sampling signal, and outputting the phase and the oscillation times through the digital register.
Optionally, the sampling unit includes: a plurality of sampling subunits;
the output end of each stage of phase inverter in the multistage phase inverters is connected with a sampling subunit;
each sampling sub-unit samples the phase of the inverter connected thereto and outputs the phase upon receiving the sampled signal.
Optionally, the counter is connected to an input end of a first-stage inverter of the multi-stage inverters and a sampling subunit, respectively;
the number of the sampling subunits is larger than the number of stages of the ring oscillator.
Optionally, if the number of stages of the multi-stage inverter is N, the ring oscillator has 2N phases, and the ring oscillator performs a periodic cycle based on the 2N phases in one analog-to-digital conversion period.
Optionally, when the ring oscillator starts oscillating based on the signal current, the counter records the oscillation frequency of the input end of the first-stage inverter;
and when each analog-digital conversion period is finished, the controller sends the sampling signal, the sampling subunit connected with the output end of each level of inverter stores the phase of the inverter connected with the sampling subunit in the digital register, the sampling subunit connected with the counter stores the oscillation frequency in the digital register, and the phase and the oscillation frequency are both output through the digital register as the result of the analog-digital conversion.
Optionally, the relationship between the oscillation frequency of each stage of inverter and the magnitude of the signal current is obtained according to the following manner:
performing product operation on the capacitance of the phase inverter at each stage and the voltage amplitude oscillated by the ring oscillator to obtain a first product result;
and taking the magnitude of the signal current as a dividend and the first product result as a divisor, and performing division operation on the dividend and the first product result to obtain the oscillation frequency of each stage of inverter.
Optionally, at the end of each analog-to-digital conversion period, the result of the analog-to-digital conversion is obtained according to the following manner:
performing product operation on the oscillation times and the stage number of the ring oscillator to obtain a second product result;
and carrying out summation operation on the phase of the multistage phase inverter and the second product result to obtain the result of the analog-to-digital conversion.
A second aspect of an embodiment of the present invention provides an infrared imager, including: a photo-current detector and an infrared imaging readout application specific integrated circuit as described in any of the first aspects.
According to the infrared imaging reading special integrated circuit provided by the invention, the ring oscillator receives signal current, generates a pulse signal and transmits the pulse signal to the counter, and the counter counts the pulse signal to obtain the oscillation frequency; the sampling unit is connected with the multi-level inverter and used for sampling the phase of the multi-level inverter and transmitting the phase to the digital register. At the end of each analog-to-digital conversion period, the phase and the oscillation number of the multi-stage inverter are stored in a digital register based on the sampling signal and output through the digital register.
Based on the structure, frequency multiplication operation is not carried out, the same precision as that of the frequency multiplication operation can be realized only by acquiring the phase information and the oscillation frequency of the oscillator after the integration is finished every time, and the power consumption and the complexity of a counter and a sampling circuit are greatly reduced. On the premise of not reducing the precision, the area overhead and the power consumption of the analog-to-digital conversion circuit are effectively reduced, and the analog-to-digital conversion circuit is extremely suitable for realizing the column-level or pixel-level ADC under small pixels and advanced processes.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive labor.
FIG. 1 is a schematic diagram of a preferred IR imaging readout ASIC according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another preferred IR imaging readout ASIC according to an embodiment of the present invention;
FIG. 3 is a timing diagram of a ring oscillator with 3-stage inverters according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.
The infrared imaging reading special integrated circuit of the embodiment of the invention comprises: the device comprises a ring oscillator, a sampling unit and a counter; the ring oscillator includes: a multi-stage inverter; the ring oscillator receives the signal current and generates a pulse signal, which is a signal of the oscillation frequency of the ring oscillator. And transmitting the pulse signal to a counter, and counting the pulse signal by the counter to obtain the oscillation frequency.
The sampling unit is connected with the multi-level inverter and used for sampling the phase of the multi-level inverter and transmitting the phase to the digital register; at the end of each analog-to-digital conversion period, the phase and the oscillation frequency of the multi-stage inverter are stored in a digital register based on a sampling signal and are output through the digital register.
Specifically, the sampling unit includes: a plurality of sampling subunits; the output end of each stage of inverter in the multi-stage inverters is connected with a sampling subunit; each sampling sub-unit samples the phase of the inverter connected thereto and outputs the phase upon receiving the sampled signal. The counter is connected with the input end of the first-stage inverter in the multi-stage inverters and a sampling subunit respectively; it will be appreciated that the number of sampling sub-units is greater than the number of stages of the ring oscillator. Because the counter is connected with one sampling subunit, and each stage of inverter is respectively connected with one sampling subunit, the number of the sampling subunits is one more than the number of stages of the ring oscillator. For example: the number of stages of the ring oscillator is 3, the number of sampling subunits is 4, and so on.
Based on the above structure, if the number of stages of the multi-stage inverter is N, the ring oscillator has 2N phases, and the ring oscillator performs a periodic cycle based on the 2N phases within one analog-to-digital conversion period. When the ring oscillator starts to oscillate based on the signal current, the counter records the oscillation frequency of the input end of the first-stage inverter; when each analog-digital conversion period is finished, the controller sends a sampling signal, the sampling subunit connected with the output end of each level of inverter stores the phase of the inverter connected with the sampling subunit in the digital register, the sampling subunit connected with the counter stores the oscillation frequency in the digital register, and the phase and the oscillation frequency are used as the results of the analog-digital conversion and are output through the digital register.
For a clearer explanation of the above-mentioned ir imaging readout asic, referring to fig. 1, a schematic structural diagram of a preferred ir imaging readout asic is shown, which is exemplified by a column-level readout asic. Fig. 1 includes: the device comprises a Blind pixel Blind, a photosensitive pixel PX, a transconductance amplifier GM, a switching tube M, a ring oscillator VCO, a plurality of sampling subunits SH, a counter and a digital Register.
The ring oscillator VCO includes: multi-stage inverter Q 1 、Q 2 、Q 3 …Q n . First stage inverter Q 1 The output end of the first-stage inverter is connected with a sampling subunit SH and a second-stage inverter Q 2 The output end of the first-stage inverter Q is also connected with a sampling subunit SH and a third-stage inverter Q 3 The output end of the sampling subunit SH is also connected with a sampling subunit SH, and so on, the nth-stage inverter Q n Is also connected to a sampling subunit SH.
Counter countr and first stage inverter Q 1 And a sampling subunit SH, respectively. Stage, the number of sampling subunits SH is n + 1.
The working principle of the infrared imaging reading special integrated circuit in fig. 1 is as follows: at the beginning of any integration quantization period, the switch tube M receives the on signal INT to be turned on. The transconductance amplifier GM converts the voltage difference between the photosensitive pixel PX and the Blind pixel Blind, i.e. V in And V blind Is converted into a signal current I SIG The signal circuit I SIG I.e. the current flowing into the ring oscillator VCO. The ring oscillator VCO starts oscillating.
Since the oscillation frequency of each inverter in the ring oscillator VCO is the same, the counter only needs to be applied to the first inverter Q 1 The oscillation frequency of the input end is counted, so that the oscillation frequency can be obtained, and meanwhile, the sampling subunits SH connected with each stage of phase inverter respectively sample the phase of the corresponding phase inverter. At the end of the integrating quantization period, the controller sends a sampling signal Φ SH All the sampling subunits SH record the oscillation times obtained by the counter and the phase of each level of inverter at the same time, store the oscillation times and the phase of each level of inverter in the digital Register, and output the oscillation times and the phase of each level of inverter through the digital Register, wherein the oscillation times and the phase of each level of inverter are used as the result of analog-to-digital conversion in the integration quantization period.
Since the ir imaging readout asic of the present invention can also be applied to ADC at pixel level, referring to fig. 2, a schematic structural diagram of another preferred ir imaging readout asic is shown, where fig. 2 includes: the circuit comprises a circuit detector Cdr, a switching tube M, a ring oscillator VCO, a plurality of sampling subunits SH, a counter and a digital Register. The pixel level analog-to-digital conversion circuit directly generates a signal current I by a circuit detector Cdr at the beginning of any integral quantization period SIG The rest of the working principle is the same as that of the column-level analog-to-digital conversion circuit, and is not described in detail.
For the phase distribution, taking 6 phase distributions of a ring oscillator of a 3-stage inverter as an example, the phase distribution, P, is given in table 1 below 0 ～P 5 Distribution representationDifferent phase distributions, each phase 60 degrees.
TABLE 1
With reference to the timing diagram of the ring oscillator of the 3-stage inverter shown in FIG. 3, the reset signal Φ starts RST Resetting a ring oscillator to P 0 Phase, after reset, ring oscillator starts oscillation, counter records first stage inverter Q 1 The oscillation frequency of the input end sends out a sampling signal phi at the end of the integral quantization period T SH 3 stage inverter Q 1 、Q 2 、Q 3 And the oscillation number of the counter is stored in the digital Register and then output.
The oscillation frequency f of each stage of inverter is determined according to the characteristics of the ring oscillator itself CCO，Q The relationship with the magnitude of the signal current is obtained as follows:
performing product operation on the capacitance of each stage of inverter and the voltage amplitude oscillated by the ring oscillator to obtain a first product result;
and taking the magnitude of the signal current as a dividend and the first product result as a divisor, and performing division operation on the dividend and the first product result to obtain the oscillation frequency of each stage of inverter.
Expressed by the formula:
wherein f is CCO ， Q Indicating the oscillation frequency, I, of each stage of the inverter SIG Representing the magnitude of the signal current, N representing the number of stages of the multi-stage inverter, C CCO Denotes the capacitance of each inverter stage and U denotes the voltage amplitude of the ring oscillator oscillation.
Then for the column stage analog-to-digital conversion circuit, the transconductance amplifier GM converts the voltage difference into a signal current, and the relationship between the ring oscillator frequency and the voltage difference is:
wherein, G M Representing the transconductance, V, of a transconductance amplifier GM in Voltage, V, representing photosensitive pixel PX blind Representing the voltage of the Blind pixel Blind.
At the end of each analog-to-digital conversion cycle, the result of the analog-to-digital conversion is obtained according to the following manner:
performing product operation on the oscillation times and the stage number of the ring oscillator to obtain a second product result;
and carrying out summation operation on the phase of the multistage phase inverter and the second product result to obtain an analog-digital conversion result.
Is expressed by the formula:
Dout＝N·K 1 +K 2
where Dout denotes the result of the analog-to-digital conversion, K 1 Denotes the number of oscillations, K 2 Indicating the phase of the multi-level inverter.
Based on the above-mentioned ir imaging readout asic, an embodiment of the present invention further provides an ir imager, where the ir imager includes any one of the above-mentioned ir imaging readout asics.
By the above example, in the infrared imaging reading asic of the present invention, the ring oscillator receives a signal current, generates a pulse signal, and transmits the pulse signal to the counter, and the counter counts the pulse signal to obtain the oscillation frequency; the sampling unit is connected with the multi-level inverter and is used for sampling the phase of the multi-level inverter and transmitting the phase to the digital register. At the end of each analog-to-digital conversion period, the phase and the oscillation frequency of the multi-stage inverter are stored in a digital register based on the sampling signal and output through the digital register.
Based on the structure, frequency multiplication operation is not carried out, the same precision as that of the frequency multiplication operation can be realized only by acquiring the phase information and the oscillation frequency of the oscillator after the integration is finished every time, and the power consumption and the complexity of a counter and a sampling circuit are greatly reduced. On the premise of not reducing the precision, the area overhead and the power consumption of the analog-to-digital conversion circuit are effectively reduced, and the analog-to-digital conversion circuit is extremely suitable for realizing a column-level or pixel-level ADC under the conditions of small pixels and advanced technology.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
While the present invention has been described with reference to the particular illustrative embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but is intended to cover various modifications, equivalent arrangements, and equivalents thereof, which may be made by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (6)
1. An infrared imaging readout asic, comprising: the device comprises a ring oscillator, a sampling unit and a counter;
the ring oscillator includes: a multi-stage inverter;
the ring oscillator receives signal current, generates a pulse signal and transmits the pulse signal to the counter, and the counter counts the pulse signal to obtain oscillation times;
the sampling unit is connected with the multistage phase inverter, is used for sampling the phase of the multistage phase inverter and transmitting the phase to the digital register;
at the end of each analog-to-digital conversion period, storing the phase of the multi-stage inverter and the oscillation times in the digital register based on a sampling signal, and outputting the phase and the oscillation times through the digital register;
the relationship between the oscillation frequency of each stage of the multi-stage inverter and the signal current is obtained according to the following modes:
performing product operation on the capacitance of each stage of inverter and the voltage amplitude oscillated by the ring oscillator to obtain a first product result;
taking the magnitude of the signal current as a dividend, taking the product of the stage number of the multistage phase inverter and the first product result as a divisor, and performing division operation on the dividend and the multistage phase inverter to obtain the oscillation frequency of each stage of phase inverter;
at the end of each analog-to-digital conversion cycle, the result of the analog-to-digital conversion is obtained according to the following manner:
performing product operation on the oscillation times and the stage number of the ring oscillator to obtain a second product result;
and carrying out summation operation on the phase of the multistage phase inverter and the second product result to obtain the result of the analog-to-digital conversion.
2. The infrared imaging readout asic according to claim 1, wherein said sampling unit comprises: a plurality of sampling subunits;
the output end of each stage of phase inverter in the multistage phase inverters is connected with a sampling subunit;
each sampling sub-unit samples the phase of the inverter connected thereto and outputs the phase upon receiving the sampling signal.
3. The ir imaging readout asic according to claim 2, wherein the counter is connected to the input of the first of the plurality of inverters and to a sampling sub-unit;
the number of the sampling subunits is larger than the number of stages of the ring oscillator.
4. The ir imaging readout asic according to claim 1, wherein if the number of stages of the multi-stage inverter is N, the ring oscillator has 2N phases, and the ring oscillator performs a cycle based on the 2N phases within one analog-to-digital conversion cycle.
5. The ir imaging readout asic according to claim 3, wherein the counter records the number of oscillations at the input of the first inverter, when the ring oscillator starts to oscillate based on the signal current;
and when each analog-digital conversion period is finished, the controller sends the sampling signal, the sampling subunit connected with the output end of each level of inverter stores the phase of the inverter connected with the sampling subunit in the digital register, the sampling subunit connected with the counter stores the oscillation frequency in the digital register, and the phase and the oscillation frequency are both output through the digital register as the result of the analog-digital conversion.
6. An infrared imager, characterized in that it comprises an infrared imaging readout application specific integrated circuit according to any one of claims 1 to 5.
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