CN116626361A - Voltage detection circuit and method, analog-to-digital converter and SOC (system on chip) - Google Patents

Voltage detection circuit and method, analog-to-digital converter and SOC (system on chip) Download PDF

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Publication number
CN116626361A
CN116626361A CN202310584662.7A CN202310584662A CN116626361A CN 116626361 A CN116626361 A CN 116626361A CN 202310584662 A CN202310584662 A CN 202310584662A CN 116626361 A CN116626361 A CN 116626361A
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ring oscillator
oscillation
signal
clock
voltage
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CN116626361B (en
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张书磊
金军贵
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Haiguang Integrated Circuit Design Beijing Co ltd
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Haiguang Integrated Circuit Design Beijing Co ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/0084—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring voltage only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The application provides a voltage detection circuit and method, an analog-to-digital converter and an SOC (system on chip) chip, and relates to the field of electronic circuits. The voltage detection circuit includes: the device comprises a ring oscillator, a sampling circuit and a processing circuit, wherein the ring oscillator is provided with a plurality of output ends of different levels, the input end of the ring oscillator is used for receiving voltage to be detected, the first input end of the sampling circuit is connected with the output end of each stage in the ring oscillator, the first input end of the processing circuit is connected with the sampling circuit, the ring oscillator is configured to generate an oscillating signal based on the voltage to be detected, and the frequency of the oscillating signal is related to the voltage to be detected; the sampling circuit is configured to sample the oscillation signal output by each stage in the ring oscillator to obtain a ring oscillator state signal and the integer times of oscillation times of the oscillation signal output by the last stage of the ring oscillator; the processing circuit is configured to derive a number of oscillations characterizing a magnitude of the voltage to be detected based on the ring oscillator status signal, the integer number of oscillations.

Description

Voltage detection circuit and method, analog-to-digital converter and SOC (system on chip)
Technical Field
The application relates to the field of electronic circuits, in particular to a voltage detection circuit and method, an analog-to-digital converter and an SOC chip.
Background
In integrated circuits, voltage fluctuations affect circuit performance, e.g., voltage fluctuations can affect jitter in high-speed analog circuits, voltage margins in logic circuits, etc. Meanwhile, the voltage is also strongly related to the performance (such as effective current, leakage current, etc.) of the MOS (Metal Oxide Semiconductor, metal-oxide-semiconductor) device, and the performance of the MOS device is also directly related to the performance of the chip, such as speed and power consumption.
Therefore, in order to optimize the performance of the integrated circuit chip, it is necessary to detect the voltage of each critical circuit module in the integrated circuit, and the accuracy of the voltage detection is high, and at the same time, the occupied area of the circuit for voltage detection needs to be reduced as much as possible.
Disclosure of Invention
The application provides a voltage detection circuit, a voltage detection method, an analog-to-digital converter and a System On Chip (SOC) Chip, so as to realize accurate detection of voltages of key circuit modules in an integrated circuit Chip.
In a first aspect, the present application provides a voltage detection circuit comprising: the device comprises a ring oscillator, a sampling circuit and a processing circuit, wherein the ring oscillator is cascaded by a plurality of unit delay units and is provided with a plurality of output ends with different levels, the input end of the ring oscillator is used for receiving a voltage to be detected, the first input end of the sampling circuit is connected with the output end of each stage of the ring oscillator, the first input end of the processing circuit is connected with the sampling circuit, the ring oscillator is configured to generate an oscillating signal based on the voltage to be detected, and the frequency of the oscillating signal is related to the voltage to be detected; the sampling circuit is configured to sample an oscillation signal output by each stage of the ring oscillator to obtain a ring oscillator state signal and an integer multiple oscillation frequency of the oscillation signal output by the last stage of the ring oscillator, wherein the ring oscillator state signal comprises a level state of the oscillation signal output by each stage of the ring oscillator, and the ring oscillator state signal is used for determining the fractional multiple oscillation frequency of the ring oscillator; the processing circuit is configured to obtain the oscillation frequency of the ring oscillator based on the ring oscillator state signal and the integer times of oscillation frequency, wherein the oscillation frequency of the ring oscillator is used for representing the voltage to be detected.
In the embodiment of the application, the ring oscillator generates the oscillation signal based on the voltage to be detected, and the frequency of the oscillation signal is related to the voltage to be detected, so that the oscillation signal output by each stage of the ring oscillator is sampled by the sampling circuit to obtain the state signal and the integer times of oscillation of the ring oscillator. And then the state signal of the ring oscillator and the integer times of oscillation are processed by the processing circuit, so that the voltage to be detected can be determined, and the voltage to be detected is accurately measured. According to the application, the voltage to be detected is obtained in an indirect measurement mode by converting the measurement of the voltage to be detected into the measurement of the oscillation frequency of the oscillation signal generated based on the voltage to be detected, so that the measurement of the voltage to be detected can be realized by adopting the structure without adopting a voltage measurement circuit with large occupied area, and the circuit area is effectively reduced.
With reference to the foregoing technical solution of the first aspect, in some possible implementation manners, the second input terminal of the sampling circuit is configured to receive a clock signal, and the sampling circuit is configured to sample, in each clock period of the clock signal, an oscillation signal output by each stage in the ring oscillator, so as to obtain a ring oscillator state signal in each clock period and an integer multiple of oscillation times in each clock period; the processing circuit is configured to determine a magnitude of the voltage to be detected based on the ring oscillator status signal per clock cycle, an integer number of oscillations per clock cycle.
In the embodiment of the application, the sampling circuit is used for sampling the oscillation signal output by each stage in the ring oscillator in each clock period, so that the processing circuit can determine the voltage to be detected in each clock period, further realize continuous detection of the voltage to be detected, and improve the application range of the scheme.
With reference to the foregoing technical solution of the first aspect, in some possible implementation manners, the processing circuit is configured to obtain a fractional oscillation number in each clock cycle based on a ring oscillator state signal in each clock cycle; based on the integer times of oscillation times and the fraction times of oscillation times in each clock period, obtaining respective corresponding oscillation times of each clock period; and determining the magnitude of the voltage to be detected based on the respective corresponding oscillation times of each clock cycle.
In the embodiment of the application, the processing circuit can determine the times of oscillation in each clock period through the state signal of the ring oscillator in each clock period, so that the precision of the times of oscillation obtained subsequently can be improved, and the finally determined voltage to be detected is more accurate.
With reference to the foregoing technical solution of the first aspect, in some possible implementation manners, the processing circuit is configured to determine the magnitude of the voltage to be detected based on respective oscillation times of at least two adjacent clock periods.
In the embodiment of the application, the magnitude of the voltage to be detected is determined through the oscillation times corresponding to at least two adjacent clock cycles, and the change condition of the voltage to be detected in different clock cycles is considered, so that the accuracy of the finally determined magnitude of the voltage to be detected can be improved.
With reference to the foregoing technical solution of the first aspect, in some possible implementation manners, the sampling circuit is further configured to continuously count an integer multiple of oscillation times in each clock cycle; the processing circuit is configured to determine the magnitude of the voltage to be detected based on a difference between respective corresponding oscillation times of two adjacent clock cycles.
In the embodiment of the application, the sampling circuit is configured to continuously count the integer times of oscillation in each clock period, so that the sampling circuit does not need to reset the integer times of oscillation recorded by the sampling circuit, and the requirement on the working capacity of the sampling circuit is reduced. And moreover, the condition of neglecting the oscillation times can be prevented when the sampling circuit resets the self-recorded integer times of oscillation times, and the accuracy of the scheme is improved.
With reference to the foregoing technical solution provided in the first aspect, in some possible implementation manners, the processing circuit includes: the encoder comprises an encoder and a difference value arithmetic unit, wherein a first input end of the encoder is connected with an output end of the sampling circuit, a second input end of the encoder is configured to receive the clock signal, a first input end of the difference value arithmetic unit is connected with an output end of the encoder, a second input end of the difference value arithmetic unit is configured to receive the clock signal, and the encoder is configured to obtain the decimal oscillation times in each clock period based on a ring oscillator state signal in each clock period; based on the integer times of oscillation times and the fraction times of oscillation times in each clock period, obtaining respective corresponding oscillation times of each clock period; the difference value arithmetic unit is configured to determine the magnitude of the voltage to be detected based on the difference between the oscillation times corresponding to two adjacent clock cycles, and store the oscillation times corresponding to the last clock cycle.
In the embodiment of the application, the oscillation times are obtained based on the state signal of the ring oscillator and the integer times of oscillation times through the encoder, and the magnitude of the voltage to be detected is determined through the difference value arithmetic unit based on the difference between the oscillation times corresponding to the clock periods of the two vectors, so that the function of the processing circuit can be realized through the encoder and the difference value arithmetic unit, and the circuit complexity of the processing circuit is reduced.
With reference to the foregoing technical solution provided by the first aspect, in some possible implementation manners, the difference value arithmetic unit includes: a memory and a subtractor, a first input of the memory being connected to an output of the encoder, a second input of the memory being configured to receive the clock signal, a first input of the subtractor being connected to an output of the encoder, a second input of the subtractor being connected to an output of the memory, the memory being configured to store the number of oscillations output by the encoder for each clock cycle of the clock cycle; the subtracter is configured to subtract the oscillation frequency corresponding to the last clock period stored in the memory from the oscillation frequency output by the encoder in each clock period of the clock signal to obtain the voltage to be detected.
In the embodiment of the application, the function of the difference value arithmetic unit is realized through the memory and the subtracter, and the circuit complexity of the difference value arithmetic unit is reduced, so that the occupied area of the voltage detection circuit can be reduced.
With reference to the foregoing technical solution provided by the first aspect, in some possible implementation manners, the encoder includes N output terminals, where N is a positive integer, and the memory includes: and N D flip-flops, wherein N D flip-flops are connected with N output ends of the encoder in a one-to-one correspondence manner, a second input end of each D flip-flop is configured to receive the clock signal, and the N D flip-flops are configured to store N-bit binary signals corresponding to the oscillation times output by the encoder on each rising edge or falling edge of the clock period.
In the embodiment of the application, N-bit binary signals output by the encoder are stored through N D flip-flops. The implementation difficulty of the memory is simplified, and the complexity of the circuit is reduced, so that the occupied area of the voltage detection circuit can be reduced.
With reference to the foregoing technical solution provided by the first aspect, in some possible implementation manners, the sampling circuit includes: the state sampling circuit is configured to sample an oscillation signal output by each stage of the ring oscillator to obtain a state signal of the ring oscillator; the first input end of the counter is connected with the output end of the last stage of the ring oscillator, and the counter is configured to count the oscillation times of the oscillation signal output by the last stage of the ring oscillator to obtain the integer times of oscillation times.
In the embodiment of the application, the state sampling circuit is used for sampling the oscillation signal output by each stage of the ring oscillator to obtain the state signal of the ring oscillator; the counter counts the oscillation times of the oscillation signals output by the last stage of the ring oscillator, so that the function of a sampling circuit is realized through the state sampling circuit and the counter, the circuit complexity is reduced, and the occupied area of the voltage detection circuit can be reduced.
In a second aspect, the present application provides an analog-to-digital converter comprising the above first aspect and/or a voltage detection circuit provided in combination with any one of the possible implementations of the above first aspect.
In a third aspect, the present application provides an SOC chip including the analog-to-digital converter provided in the second aspect.
In a fourth aspect, the present application provides an electronic device, including the SOC chip provided in the third aspect.
In a fifth aspect, the present application provides an analog-to-digital conversion method, including: acquiring an oscillation signal generated by a ring oscillator based on a voltage to be detected, wherein the frequency of the oscillation signal is related to the voltage to be detected; sampling an oscillation signal output by each stage in the ring oscillator to obtain a ring oscillator state signal and integer times of oscillation times of the oscillation signal output by the last stage of the ring oscillator, wherein the ring oscillator state signal comprises the level state of the oscillation signal output by each stage of the ring oscillator, and the ring oscillator state signal is used for determining the decimal times of oscillation times of the ring oscillator; and obtaining the oscillation times of the ring oscillator based on the ring oscillator state signal and the integer times of oscillation times, wherein the oscillation times of the ring oscillator are used for representing the voltage to be detected.
With reference to the foregoing technical solution of the second aspect, in some possible implementation manners, in each clock cycle of the clock signal, sampling an oscillation signal output by each stage in the ring oscillator to obtain a ring oscillator state signal in each clock cycle and an integer multiple of oscillation times in each clock cycle; accordingly, obtaining the oscillation frequency of the ring oscillator based on the ring oscillator state signal and the integer multiple of the oscillation frequency includes: and obtaining the oscillation times of the ring oscillator based on the state signal of the ring oscillator in each clock period and the integral multiple oscillation times in each clock period.
With reference to the foregoing second aspect of the present invention, in some possible implementation manners, the obtaining the oscillation frequency of the ring oscillator based on the state signal of the ring oscillator in each clock cycle and the integer multiple oscillation frequency in each clock cycle includes: based on the state signal of the ring oscillator in each clock period, the decimal oscillation times in each clock period are obtained; obtaining the respective corresponding oscillation times of each clock cycle based on the integer times of oscillation times and the fraction times of oscillation times in each clock cycle; and obtaining the oscillation times of the ring oscillator based on the respective oscillation times of each clock cycle.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a block diagram showing a first voltage detection circuit according to an embodiment of the present application;
FIG. 2 is a signal timing diagram of an oscillation signal output by a ring oscillator according to an embodiment of the present application;
FIG. 3 is a block diagram of a second voltage detection circuit according to an embodiment of the present application;
fig. 4 is a block diagram illustrating a third voltage detection circuit according to an embodiment of the present application;
FIG. 5 is a block diagram of a processing circuit according to an embodiment of the present application;
fig. 6 is a block diagram of a fourth voltage detection circuit according to an embodiment of the present application;
fig. 7 is a flow chart of a voltage detection method according to an embodiment of the application.
Reference numerals: 100-a voltage detection circuit; 110-a ring oscillator; a 120-sampling circuit; 121-a state sampling circuit; 122-a counter; 130-a processing circuit; 131-an encoder; 132-a difference operator; 1321-memory; 1322-subtractor.
Detailed Description
The terms "first," "second," "third," and the like are used merely for distinguishing between descriptions and not for indicating a sequence number, nor are they to be construed as indicating or implying relative importance.
In the description of the present application, unless explicitly stated and limited otherwise, the term "coupled" is to be interpreted broadly, as for example, whether fixedly coupled, detachably coupled, or integrally coupled; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements.
The technical scheme of the present application will be described in detail with reference to the accompanying drawings.
In view of the large area of the existing voltage measurement circuit (such as a voltage transformer), if the voltage of each key circuit module in the integrated circuit is detected in this way, the area of the integrated circuit is large, so that the existing voltage measurement circuit is difficult to be applied to the integrated circuit in a large scale. The present application provides a voltage detection circuit 100, which can accurately measure the voltage of each key circuit module in an integrated circuit, and does not occupy a large area.
Referring to fig. 1, fig. 1 is a block diagram illustrating a voltage detection circuit 100 according to an embodiment of the application, where the voltage detection circuit 100 includes a ring oscillator 110, a sampling circuit 120, and a processing circuit 130.
The ring oscillator 110 is cascaded by a plurality of unit delay cells (inverters) having a plurality of outputs of different levels, an input of the ring oscillator 110 for receiving a voltage to be detected, the ring oscillator 110 being configured to generate an oscillating signal based on the voltage to be detected.
The frequency of the oscillating signal is related to the voltage to be detected, and in particular, the larger the voltage to be detected is, the larger the frequency of the oscillating signal is. Because the sensor or the measuring circuit for directly measuring the voltage to be detected is usually large in size, in order to reduce the occupied area of the circuit, the voltage to be detected is converted into the oscillation frequency for generating the oscillation signal based on the voltage to be detected, and then the voltage to be detected can be obtained.
The implementation and principles of the ring oscillator 110 are well known to those skilled in the art, and are not described herein for brevity.
A first input of the sampling circuit 120 is connected to an output of each stage of the ring oscillator 110, and a first input of the processing circuit 130 is connected to the sampling circuit 120. The sampling circuit 120 and the processing circuit 130 cooperate to determine the voltage to be detected based on the oscillation signal output by the ring oscillator 110.
The sampling circuit 120 is configured to sample the oscillation signal output by each stage of the ring oscillator 110 to obtain a ring oscillator state signal and an integer multiple of the oscillation frequency of the oscillation signal output by the last stage of the ring oscillator 110, where the ring oscillator state signal includes a level state of the oscillation signal output by each stage of the ring oscillator 110. The processing circuit 130 is configured to determine the magnitude of the voltage to be detected based on the ring oscillator status signal, an integer number of oscillations.
Specifically, the processing circuit 130 obtains the number of times of oscillation based on the ring oscillator state signal, and then adds the number of times of oscillation and the number of times of oscillation to obtain the number of times of oscillation. The number of oscillations characterizes the magnitude of the voltage to be detected.
After the oscillation frequency is obtained, a voltage magnitude value corresponding to the obtained oscillation frequency can be searched through a corresponding relation (which can be a relation curve or a relation table, etc.) between the oscillation frequency and the voltage magnitude, which is established in advance.
The correspondence of the oscillation number and the voltage magnitude may be obtained by inputting a voltage of a known magnitude to the voltage detection circuit (or a ring oscillator identical to the ring oscillator in the voltage detection circuit), and recording the oscillation number corresponding to the voltage of the known magnitude. Repeatedly measuring the oscillation times corresponding to a plurality of voltages with known magnitudes to obtain the corresponding relationship between the oscillation times and the voltage magnitudes. The corresponding relation between the oscillation times and the voltage can be recorded in the form of a relation curve or a relation table.
Wherein, the ring oscillator state signal and the integer times of oscillation can be represented by serial or parallel binary signals.
In the first embodiment, the sampling circuit 120 may sample the oscillation signal output from each stage of the ring oscillator 110 only once.
When the sampling circuit 120 samples the oscillation signal output from each stage of the ring oscillator 110 only once, the processing circuit 130 determines the magnitude of the voltage to be detected based on the ring oscillator state signal output from the sampling circuit 120 and the integer times of oscillation.
Alternatively, the sampling circuit 120 may be configured to accept the control signal and, upon accepting the control signal, sample the oscillating signal output by each stage in the ring oscillator 110 once. Wherein the control signal may be sent by other devices to the sampling circuit 120, the control signal may be a signal such as a binary signal, etc., and the specific form of the control signal is not limited herein.
Alternatively, the second input of the sampling circuit 120 is configured to receive a clock signal, and the sampling circuit 120 is configured to sample the oscillation signal output by each stage of the ring oscillator 110 once based on the received clock signal.
For example, the sampling circuit 120 may be configured to sample the oscillation signal output from each stage of the ring oscillator 110 once when a preset time is reached. The preset time may be a preset number of times the clock signal oscillates.
Alternatively, the specific process of the processing circuit 130 obtaining the fractional oscillation times based on the ring oscillator status signal may be: based on the output state number before the level state of the oscillating signal corresponding to different stages in the first ring oscillator state signal changes for the first time and the total number of stages of the ring oscillator 110, the number of times of oscillation is obtained.
For ease of understanding, taking the oscillating signal shown in fig. 2 as an example, when the ring oscillator state signal includes 1110000 at time t1, since the level state of the oscillating signal corresponding to the different stage occurs at out_4 for the first time, it can be determined that there are 3 high level states before the first change, and thus, the number of times of the oscillation is 3/7.
When the ring oscillator state signal is 1100000, it can be confirmed that the level state of the oscillation signal corresponding to the different stage occurs at out_3 for the first time, and thus it can be determined that there are 2 high level states before the first change, and thus the number of times of the fractional oscillation is 2/7. Even if the level state change occurs again at out_7, the number of times of the oscillation is not affected by a small number.
In a second embodiment, the sampling circuit 120 may sample the oscillating signal output from each stage of the ring oscillator 110 multiple times.
When the oscillation signal output by each stage of the ring oscillator 110 needs to be sampled multiple times, the second input end of the sampling circuit 120 is further configured to receive a clock signal, and at this time, the sampling circuit 120 is configured to sample the oscillation signal output by each stage of the ring oscillator 110 in each clock period of the clock signal, so as to obtain the state signal of the ring oscillator in each clock period and the integer multiple oscillation times of the oscillation signal output by the last stage of the ring oscillator 110 in each clock period.
The processing circuit 130 is configured to determine the magnitude of the voltage to be detected based on the ring oscillator status signal per clock cycle, an integer number of oscillations per clock cycle.
Optionally, the processing circuit 130 is configured to obtain a fractional number of oscillations per clock cycle based on the ring oscillator status signal per clock cycle; based on the integer times of oscillation times and the decimal times of oscillation times in each clock period, obtaining the respective corresponding oscillation times of each clock period; and determining the magnitude of the voltage to be detected based on the respective corresponding oscillation times of each clock cycle.
It will be appreciated that the sampling circuit 120 samples the oscillating signal output from each stage of the ring oscillator 110 multiple times in two sampling manners:
(i) The sampling circuit samples independently in each clock period;
(ii) The sampling circuit samples continuously in each clock cycle.
The principle of the voltage detection circuit in (i) and (ii) will be described below.
In embodiment (i), the sampling circuit samples independently at each clock cycle, i.e., the sampling circuit records the number of times of integer oscillations in each clock cycle independently of the other integer times of oscillations in each clock cycle.
For example, when the integer multiple oscillation times are started at each clock cycle, the sampling circuit initializes the integer multiple oscillation times to 0, that is, the integer multiple oscillation times in each clock cycle are independently counted from 0.
For example, there are clock period a, clock period B, and clock period C, where clock period a is the first clock period, clock period B is the second clock period, clock period C is the third clock period, and the oscillating signal output from the last stage of the ring oscillator 110 oscillates X in clock period a A Once, oscillate X in clock period B B Once, oscillate X in clock cycle C C And twice. Then the integer multiple of oscillation times corresponding to clock period A is X A The integer times of oscillation corresponding to the clock period B is X B The integer times of oscillation corresponding to the clock period C is X C . The examples herein are for ease of understanding only and should not be construed as limiting the application.
Accordingly, for each clock cycle, the processing circuit 130 is configured to derive a fractional oscillation count based on the ring oscillator status signal in that clock cycle, and then add the integer and fractional oscillation counts in that clock cycle to derive the oscillation count in that clock cycle. The oscillation frequency characterizes the magnitude of the voltage to be detected in the clock period.
Alternatively, for each clock cycle, the processing circuit 130 is configured to obtain a fractional oscillation frequency based on the ring oscillator status signal in the clock cycle, and then add the integer oscillation frequency and the fractional oscillation frequency in the clock cycle to obtain the oscillation frequency corresponding to the clock cycle. And then carrying out weighted average processing on the oscillation times corresponding to the clock period and the oscillation times corresponding to a plurality of clock periods adjacent to the clock period to obtain target oscillation times, wherein the target oscillation times represent the voltage to be detected in the clock period.
The weight value of the weighted average may be set according to actual requirements, for example, the weight value of the oscillation frequency that is closer in time to the current clock cycle may be set to be larger, or the weight value corresponding to each oscillation frequency may be set to be the same (for example, all the weight values are 1), where specific selection of the weight values is not limited.
It will be appreciated that in such an embodiment, the processing circuit 130 also needs to store the number of oscillations in the plurality of clock cycles.
The specific implementation manner of obtaining the fractional oscillation times according to the ring oscillator state signal is consistent with the manner described above, and is not described herein for brevity.
The specific implementation manner of obtaining the fractional oscillation times according to the ring oscillator state signal is consistent with the manner described above, and is not described herein for brevity.
In the (ii) th embodiment, the integer multiple of oscillation times corresponding to each clock cycle is the sum of the integer multiple of oscillation times in the current clock cycle and the integer multiple of oscillation times in all previous clock cycles.
For example, there are clock period a, clock period B, and clock period C, where clock period a is the first clock period, clock period B is the second clock period, clock period C is the third clock period, and the oscillating signal output from the last stage of the ring oscillator 110 oscillates X in clock period a A Once, oscillate X in clock period B B Once, oscillate X in clock cycle C C And twice. Then the integer multiple of oscillation times corresponding to clock period A is X A Integer multiple of vibration corresponding to clock period BThe oscillating frequency is X A +X B The integer times of oscillation corresponding to the clock period C is X A +X B +X C . The examples herein are for ease of understanding only and should not be construed as limiting the application.
Accordingly, for each clock cycle, the processing circuit 130 is configured to obtain a fractional oscillation frequency based on the ring oscillator status signal in the clock cycle, and then add the integer oscillation frequency and the fractional oscillation frequency in the clock cycle to obtain the oscillation frequency corresponding to the clock cycle. And then subtracting the oscillation frequency corresponding to the clock cycle from the oscillation frequency corresponding to the previous clock cycle to obtain a target oscillation frequency, wherein the target oscillation frequency represents the magnitude of the voltage to be detected in the clock cycle.
It will be appreciated that in such an embodiment, the processing circuit 130 also needs to store the number of oscillations corresponding to the previous clock cycle.
Alternatively, as shown in fig. 3, the specific structure of the sampling circuit 120, the sampling circuit 120 includes a state sampling circuit 121 and a counter 122.
In the first embodiment, the first input terminal of the state sampling circuit 121 is connected to the output terminal of each stage of the ring oscillator 110, and the state sampling circuit 121 is configured to sample the oscillation signal output by each stage of the ring oscillator 110 to obtain the state signal of the ring oscillator in each clock cycle.
In the second embodiment, the first input terminal of the state sampling circuit 121 is connected to the output terminal of each stage of the ring oscillator 110, the second input terminal of the state sampling circuit 121 is configured to receive the clock signal, and the state sampling circuit 121 is configured to sample, in each clock period of the clock signal, the oscillation signal output by each stage of the ring oscillator 110, so as to obtain the state signal of the ring oscillator in each clock period.
Alternatively, the state sampling circuit 121 may sample the oscillation signal output from each stage of the ring oscillator 110 at a rising edge or a falling edge of a clock cycle.
The data output by the state sampling circuit 121 may be serial or parallel binary signals.
For ease of understanding, referring to fig. 2, out_1 to out_7 in fig. 2 are oscillation signals respectively output from 7 stages (but not limited thereto in practice) of the ring oscillator 110, and clk is a clock signal. As can be seen from fig. 2, when the state sampling circuit 121 samples the oscillation signal output from each stage of the ring oscillator 110 at the rising edge of the clock signal, out_1 to out_3 are at the high level at time t1, and out_4 to out_7 are at the low level at time t 1. If a high signal is characterized by a "1" and a low signal is characterized by a "0", then at time t1 the ring oscillator status signal includes 1110000. The examples herein are for ease of understanding only and should not be construed as limiting the application.
The state sampling circuit 121 may be a sampling circuit capable of sampling the level state of the oscillation signal output from each stage of the ring oscillator 110.
In the first embodiment, the first input terminal of the counter 122 is connected to the output terminal of the last stage of the ring oscillator 110, and the counter 122 is configured to count the number of oscillations of the oscillation signal output by the last stage of the ring oscillator 110, to obtain an integer multiple of the number of oscillations, and to output the integer multiple of the number of oscillations on the rising edge or the falling edge of the clock signal.
Note that the number of times of the integer multiple oscillation output by the counter 122 and the ring oscillator state signal output by the state sampling circuit 121 are the same time signal, for example, the counter 122 outputs the number of times of the integer multiple oscillation recorded at time t1, and the state sampling circuit 121 outputs the ring oscillator state signal sampled at time t 1. The examples herein are for ease of understanding only and should not be construed as limiting the application.
When the sampling circuit 120 is in the second embodiment, the first input terminal of the counter 122 is connected to the output terminal of the last stage of the ring oscillator 110, the second input terminal of the counter 122 is configured to receive the clock signal, the counter 122 is configured to count the oscillation frequency of the oscillation signal output by the last stage of the ring oscillator 110, to obtain an integer multiple of the oscillation frequency, and to output the integer multiple of the oscillation frequency on the rising edge or the falling edge of the clock signal.
The counter 122 counts the oscillation frequency of the oscillation signal output from the last stage of the ring oscillator 110, and when the oscillation signal output from the last stage of the ring oscillator 110 oscillates once, the number of times recorded by the counter 122 is increased by one.
In the above-described embodiment (i), the counter 122 is configured to zero-clear the data recorded by itself at the start of each clock cycle, and to record the number of times of oscillation of an integer multiple in each clock cycle from zero.
In the above-described embodiment (ii), the counter 122 is configured to count continuously.
Alternatively, the counter 122 outputs data recorded by itself at each rising or falling edge of the clock cycle.
Note that, in the second embodiment described above, the time at which the state sampling circuit 121 in the sampling circuit 120 samples the oscillation signal is the same as the time of the integer multiple of the oscillation times output from the counter 122.
For example, it may be set at the rising edge of each clock cycle, the state sampling circuit 121 samples the oscillation signal output from each stage in the ring oscillator 110, and the counter 122 outputs an integer multiple of the oscillation times recorded by itself. Or alternatively. The state sampling circuit 121 samples the oscillation signal output from each stage in the ring oscillator 110 at the falling edge of each clock cycle, and the counter 122 outputs an integer multiple of the oscillation times recorded by itself. The examples herein are for ease of understanding only and should not be construed as limiting the application.
The data output by the counter 122 and the state sampling circuit 121 may be serial or parallel binary signals.
The counter 122 may be any counter 122 that is currently available, and the specific implementation of the counter 122 is not limited herein.
Alternatively, in the first embodiment described above, that is, when the sampling circuit 120 samples the oscillation signal output from each stage of the ring oscillator 110 only once, the processing circuit 130 may be any electronic component having signal processing capability.
For example, the processing circuit 130 may be an encoder 131. At this time, a first input terminal of the encoder 131 is connected to an output terminal of the sampling circuit 120, and the encoder 131 is configured to obtain a fractional oscillation number based on the ring oscillator state signal; and obtaining the oscillation times based on the integer times of oscillation and the decimal times of oscillation.
Alternatively, in the above-described embodiment (i), that is, when the sampling circuit 120 samples the oscillation signal output from each stage of the ring oscillator 110 individually in each clock cycle of the clock signal, the processing circuit 130 may be any type of processor configured to implement the functions shown in the above-described processing circuit 130. For example, a central processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), or the like; but also digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field programmable gate arrays (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. Alternatively, the processing circuit 130 may include an encoder 131.
A first input of the encoder 131 is connected to an output of the sampling circuit 120, a second input of the encoder 131 is configured to receive a clock signal, and the encoder 131 is configured to obtain a fractional number of oscillations based on the ring oscillator state signal in each clock cycle of the clock signal; and obtaining the respective corresponding oscillation times of each clock cycle based on the integer times of oscillation times and the decimal times of oscillation times.
The encoder 131 obtains the number of times of oscillation based on the ring oscillator state signal; based on the integer multiple oscillation times and the fractional multiple oscillation times, the specific implementation manner and principle of the respective oscillation times of each clock cycle are the same as the corresponding contents in the processing circuit 130 described above, and are not repeated here for brevity.
The encoder 131 may be any type of encoder 131, as long as the number of oscillations obtained based on the ring oscillator status signal and the integer multiple of the number of oscillations in each clock cycle can be achieved, and the specific implementation of the encoder 131 is not limited herein.
Optionally, the processing circuit 130 may further include an average operator in addition to the encoder 131, where an input end of the average operator is connected to an output end of the encoder 131, and the average operator is configured to perform weighted average processing on the oscillation times corresponding to the current clock cycle and the oscillation times corresponding to a plurality of clock cycles adjacent to the current clock cycle, to obtain a target oscillation times, where the target oscillation times represent the magnitude of the voltage to be detected in the clock cycle.
The specific implementation and principle of the mean value operator are well known to those skilled in the art, and are not described herein for brevity.
The specific implementation and principle of the target oscillation frequency obtained by the average value arithmetic unit are consistent with those of the processing circuit 130 described above, and are not described herein for brevity.
Alternatively, in the above embodiment (ii), that is, when the sampling circuit 120 samples the oscillation signal output by each stage of the ring oscillator 110 for a plurality of clock cycles, the processing circuit 130 may be any type of processor configured to implement the functions shown in the processing circuit 130, for example, a central processing unit, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. Alternatively, the processing circuit 130 may be implemented in other manners, for example, where the processing circuit 130 may include an encoder 131 and a difference operator 132.
When the processing circuit 130 includes an encoder 131 and a difference operator 132, a first input terminal of the encoder 131 is connected to an output terminal of the sampling circuit 120, a second input terminal of the encoder 131 is configured to receive a clock signal, and the encoder 131 is configured to obtain a fractional oscillation number based on the ring oscillator state signal in each clock period of the clock signal; and obtaining the respective corresponding oscillation times of each clock cycle based on the integer times of oscillation times and the decimal times of oscillation times.
The encoder 131 obtains the number of times of oscillation based on the ring oscillator state signal; based on the integer multiple oscillation times and the fractional multiple oscillation times, the specific implementation manner and principle of the respective oscillation times of each clock cycle are the same as the corresponding contents in the processing circuit 130 described above, and are not repeated here for brevity.
The encoder 131 may be any type of encoder 131, as long as the number of oscillations obtained based on the ring oscillator status signal and the integer multiple of the number of oscillations in each clock cycle can be achieved, and the specific implementation of the encoder 131 is not limited herein.
A first input terminal of the difference operator 132 is connected to an output terminal of the encoder 131, a second input terminal of the difference operator 132 is configured to receive the clock signal, the difference operator 132 is configured to determine the magnitude of the voltage to be detected based on the respective oscillation times of the adjacent two clock cycles in each clock cycle of the clock signal, and store the oscillation times corresponding to the last clock cycle.
Optionally, the difference operator 132 is configured to determine the magnitude of the voltage to be detected based on the subtraction of the respective oscillation times of the adjacent two clock cycles.
The specific implementation manner and principle of the difference value arithmetic unit 132 for determining the magnitude of the voltage to be detected based on the oscillation times corresponding to each of the two adjacent clock cycles are consistent with the corresponding content in the processing circuit 130 described above, and are not described herein for brevity.
Alternatively, as shown in fig. 4, the specific implementation of the difference operator 132, the difference operator 132 includes a memory 1321 and a subtractor 1322. A first input of the memory 1321 is connected to an output of the encoder 131, a second input of the memory 1321 is configured to receive the clock signal, and the memory 1321 is configured to store the number of oscillations output by the encoder 131 during each clock cycle, for example, at each rising or falling edge of the clock cycle.
It is to be understood that the memory 1321 may be a memory provided outside the voltage detection circuit, and the processing circuit includes only a subtractor. Accordingly, the subtracter and the encoder communicate with the memory, respectively, to store the number of oscillations output by the encoder with the memory, and to transmit the number of oscillations stored by the memory to the subtracter. At this time, the Memory 1321 may be any type of Memory, for example, but not limited to, a random access Memory (Random Access Memory, RAM), a Read Only Memory (ROM), a programmable Read Only Memory (Programmable Read-Only Memory, PROM), an erasable Read Only Memory (Erasable Programmable Read-Only Memory, EPROM), an electrically erasable Read Only Memory (Electric Erasable Programmable Read-Only Memory, EEPROM), and the like.
Alternatively, the memory 1321 may be any type of flip-flop, latch, or the like as long as it can store the number of oscillations output by the encoder 131, and the specific type of the memory 1321 is not limited herein.
Alternatively, the encoder 131 may include N output terminals (0 to N-1 shown in fig. 5), where N is a positive integer greater than or equal to 2. At this point, one implementation of the memory 1321 may be: memory 1321 includes N D flip-flops. At this time, the processing circuit 130 has a structure as shown in fig. 5.
N D flip-flops (DFFs shown in fig. 5) are connected in one-to-one correspondence with N output terminals of the encoder 131, a second input terminal of each D flip-flop is configured to receive a clock signal, the N D flip-flops are configured to store an N-bit binary signal corresponding to the number of oscillations at each rising or falling edge of a clock period, and the encoder 131 outputs the N-bit binary signal. That is, each D flip-flop stores one bit of the N-bit binary signal output from the encoder 131.
It will be appreciated that since the number of oscillations includes a fractional part (a fractional number of oscillations), when converting the number of oscillations into a binary signal, the number of oscillations may be amplified by M (M is the number of stages of the ring oscillator 110, M is a positive integer), and then the integer number of oscillations amplified by M may be converted into the binary signal.
Correspondingly, at this time, before searching the corresponding voltage magnitude from the corresponding relation between the oscillation frequency and the voltage magnitude which are established in advance by using the oscillation frequency, converting the binary signal output by the processing circuit into the oscillation frequency which is amplified by M times, dividing the oscillation frequency which is amplified by M times to obtain the oscillation frequency, and finally searching the corresponding voltage magnitude from the corresponding relation between the oscillation frequency and the voltage magnitude which are established in advance by using the oscillation frequency. A first input terminal of a subtractor 1322 in the difference operator 132 is connected to the output terminal of the encoder 131, a second input terminal of the subtractor 1322 is connected to the output terminal of the memory 1321, and the subtractor 1322 is configured to subtract, in each clock cycle of the clock signal, the oscillation number corresponding to the last clock cycle stored in the memory 1321 from the oscillation number output by the encoder 131, to obtain the magnitude of the voltage to be detected.
The cnt_cur (N-1:0) shown in fig. 5 is an N-bit binary signal corresponding to the oscillation frequency outputted by the encoder, and cnt_last (N-1:0) is an N-bit binary signal corresponding to the oscillation frequency stored in the memory (N D flip-flops).
Alternatively, the subtractor 1322 may read the number of oscillations corresponding to the previous clock cycle from the memory 1321 at each rising edge or falling edge of the clock signal, and then subtract the number of oscillations corresponding to the previous clock cycle stored in the memory 1321 from the number of oscillations output by the encoder 131 to obtain the magnitude of the voltage to be detected.
Subtractor 1322 may be any existing subtractor 1322, so long as it can perform the above functions, and the specific type of subtractor 1322 is not limited herein.
In order to facilitate understanding of the above-mentioned voltage detection circuit 100, please refer to fig. 6, it should be noted that the voltage detection circuit 100 shown in fig. 6 is only one implementation of the voltage detection circuit 100 provided by the present application, and should not be taken as limiting the present application.
As shown in fig. 6, an input terminal of the ring oscillator 110 is used for receiving a voltage to be detected, and an output terminal of the ring oscillator 110 is connected to a state sampling circuit 120 and a counter 122, respectively.
The output terminals of the state sampling circuit 121 and the counter 122 are respectively connected to an encoder 131 of the processing circuit 130, and the output terminal of the encoder 131 is connected to the input terminal of the difference operator 132.
The specific implementation and principles of the ring oscillator 110, the state sampling circuit 121, the counter 122, the encoder 131 and the difference calculator 132 are already described above, and are not further described here for brevity.
Based on the same inventive concept, the present application also provides an analog-to-digital converter, which includes the above-mentioned voltage detection circuit 100.
The analog-to-digital converter may be a circuit or a device for converting an analog signal into a digital signal, for example, the existing voltage detection circuit 100 may be modified to further realize that the voltage to be detected is measured, and the frequency of oscillation generated by the oscillation signal based on the voltage to be detected is converted into the measurement, so as to achieve the purpose of indirectly measuring the voltage to be detected. Therefore, the voltage measurement circuit with large occupied area is not needed to be used for measurement, and the area of the analog-digital conversion circuit is effectively reduced.
The specific implementation and principle of the voltage detection circuit 100 are described in the foregoing, and are not described herein for brevity.
Based on the same inventive concept, the present application also provides an SOC chip including the above-described voltage detection circuit 100 or the above-described analog-to-digital converter. For example, the SOC chip includes the analog-to-digital converter described above.
The SOC chip may be a chip with signal processing capabilities, such as a central processing unit, network processor, digital signal processor, application specific integrated circuit, field programmable gate array, or the like.
The specific implementation and principles of the voltage detection circuit 100 and the analog-to-digital converter are described above, and are not repeated here for brevity.
Based on the same inventive concept, the present application also provides an electronic device, which includes any one of the above-mentioned voltage detection circuit 100, analog-to-digital converter, and SOC chip. For example, the electronic device includes the SOC chip described above.
The electronic devices include, but are not limited to, personal computers, servers, cell phones, vehicle-mounted devices, and the like.
The specific implementation and principles of the voltage detection circuit 100, the analog-to-digital converter, and the SOC chip are described above, and are not described here again for brevity.
Based on the same inventive concept, an embodiment of the present application provides a voltage detection method, and the steps included in the method will be described with reference to fig. 7. In some possible embodiments, the voltage detection method may be applied to the voltage detection circuit described above.
S100: and acquiring an oscillation signal generated by the ring oscillator based on the voltage to be detected, wherein the frequency of the oscillation signal is related to the voltage to be detected.
Alternatively, the above-mentioned oscillation signal generated by the ring oscillator 110 based on the voltage to be detected may be obtained, and then the oscillation signal generated by the ring oscillator 110 based on the voltage to be detected may be obtained based on the above-mentioned sampling circuit 120.
S200: and sampling the oscillation signal output by each stage in the ring oscillator to obtain the state signal of the ring oscillator and the integer times of oscillation times of the oscillation signal output by the last stage of the ring oscillator.
Wherein the ring oscillator status signal includes a level status of an oscillating signal output by each stage of the ring oscillator.
Alternatively, the sampling circuit 120 may sample the oscillation signal output by each stage of the ring oscillator 110 to obtain the state signal of the ring oscillator and the integer multiple of the oscillation frequency of the oscillation signal output by the last stage of the ring oscillator 110.
S300: and obtaining the oscillation times of the ring oscillator based on the ring oscillator state signal and the integer times of oscillation times.
Alternatively, the processing circuit 130 may obtain the oscillation frequency of the ring oscillator based on the state signal of the ring oscillator and the integer multiple of the oscillation frequency. The oscillation times of the ring oscillator are used for representing the magnitude of the voltage to be detected.
The oscillation signal output by each stage in the ring oscillator 110 is sampled in each clock cycle of the clock signal, so as to obtain a ring oscillator state signal in each clock cycle and an integer multiple of oscillation times in each clock cycle. Correspondingly, based on the state signal of the ring oscillator and the integer times of oscillation times, the specific implementation manner for obtaining the oscillation times of the ring oscillator can be as follows: and obtaining the oscillation times of the ring oscillator based on the state signal of the ring oscillator in each clock period and the integral multiple oscillation times in each clock period.
Optionally, based on the state signal of the ring oscillator in each clock cycle and the integer multiple of oscillation times in each clock cycle, a specific implementation manner of obtaining the oscillation times of the ring oscillator may be: firstly, based on a ring oscillator state signal in each clock period, obtaining a decimal oscillation frequency in each clock period, and then, based on an integer oscillation frequency and a decimal oscillation frequency in each clock period, obtaining respective corresponding oscillation frequencies of each clock period; and finally, obtaining the oscillation times of the ring oscillator based on the respective corresponding oscillation times of each clock cycle.
The voltage detection method provided in the embodiment of the present application has the same implementation principle and technical effects as those of the embodiment of the voltage detection circuit 100, and for brevity description, reference may be made to corresponding contents in the embodiment of the voltage detection circuit 100.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims (15)

1. A voltage detection circuit, comprising:
a ring oscillator cascaded by a plurality of unit delay cells, having a plurality of outputs of different levels, an input of the ring oscillator for receiving a voltage to be detected, the ring oscillator configured to generate an oscillating signal based on the voltage to be detected, the oscillating signal having a frequency related to the voltage to be detected;
the sampling circuit is configured to sample an oscillation signal output by each stage in the ring oscillator to obtain a ring oscillator state signal and integer times of oscillation times of the ring oscillator, wherein the ring oscillator state signal comprises a level state of the oscillation signal output by each stage of the ring oscillator, and the ring oscillator state signal is used for determining the fractional times of oscillation times of the ring oscillator;
the first input end of the processing circuit is connected with the sampling circuit, and the processing circuit is configured to obtain the oscillation times of the ring oscillator based on the state signal of the ring oscillator and the integer times of oscillation times, wherein the oscillation times of the ring oscillator are used for representing the voltage to be detected.
2. The voltage detection circuit of claim 1, wherein the second input of the sampling circuit is configured to receive a clock signal, the sampling circuit is configured to sample the oscillation signal output by each stage of the ring oscillator in each clock period of the clock signal to obtain a ring oscillator state signal in each clock period and an integer multiple of oscillation times in each clock period;
the processing circuit is configured to determine a magnitude of the voltage to be detected based on the ring oscillator status signal per clock cycle, an integer number of oscillations per clock cycle.
3. The voltage detection circuit of claim 2, wherein the processing circuit is configured to derive a fractional number of oscillations per clock cycle based on the ring oscillator status signal per clock cycle; based on the integer times of oscillation times and the fraction times of oscillation times in each clock period, obtaining respective corresponding oscillation times of each clock period; and determining the magnitude of the voltage to be detected based on the respective corresponding oscillation times of each clock cycle.
4. A voltage detection circuit according to claim 3, wherein the processing circuit is configured to determine the magnitude of the voltage to be detected based on the respective number of oscillations of at least two adjacent clock cycles.
5. The voltage detection circuit of claim 4, wherein the sampling circuit is further configured to continuously count an integer number of oscillations per clock cycle;
the processing circuit is configured to determine the magnitude of the voltage to be detected based on a difference between respective corresponding oscillation times of two adjacent clock cycles.
6. The voltage detection circuit of claim 4, wherein the processing circuit comprises:
the first input end of the encoder is connected with the output end of the sampling circuit, the second input end of the encoder is configured to receive the clock signal, and the encoder is configured to obtain the times of the decimal oscillation in each clock period based on the state signal of the ring oscillator in each clock period; based on the integer times of oscillation times and the fraction times of oscillation times in each clock period, obtaining respective corresponding oscillation times of each clock period;
The first input end of the difference value arithmetic unit is connected with the output end of the encoder, the second input end of the difference value arithmetic unit is configured to receive the clock signal, the difference value arithmetic unit is configured to determine the magnitude of the voltage to be detected based on the difference between the oscillation times corresponding to two adjacent clock periods, and store the oscillation times corresponding to the last clock period.
7. The voltage detection circuit of claim 6, wherein the difference operator comprises:
a memory, a first input of the memory being connected to an output of the encoder, a second input of the memory being configured to receive the clock signal, the memory being configured to store the number of oscillations output by the encoder during each of the clock cycles;
the first input end of the subtracter is connected with the output end of the encoder, the second input end of the subtracter is connected with the output end of the memory, and the subtracter is configured to subtract the oscillation frequency corresponding to the last clock cycle stored in the memory from the oscillation frequency output by the encoder in each clock cycle of the clock signal to obtain the magnitude of the voltage to be detected.
8. The voltage detection circuit of claim 7, wherein the encoder includes N outputs, N being a positive integer, the memory comprising:
and N D flip-flops, wherein N D flip-flops are connected with N output ends of the encoder in a one-to-one correspondence manner, a second input end of each D flip-flop is configured to receive the clock signal, and the N D flip-flops are configured to store N-bit binary signals corresponding to the oscillation times output by the encoder on each rising edge or falling edge of the clock period.
9. The voltage detection circuit according to any one of claims 1 to 8, wherein the sampling circuit includes:
the input end of the state sampling circuit is connected with the output end of each stage of the ring oscillator, and the state sampling circuit is configured to sample the oscillation signal output by each stage of the ring oscillator to obtain the state signal of the ring oscillator;
the first input end of the counter is connected with the output end of the last stage of the ring oscillator, and the counter is configured to count the oscillation times of the oscillation signals output by the last stage of the ring oscillator to obtain the integer times of oscillation times.
10. An analog-to-digital converter, comprising:
a voltage detection circuit according to any one of claims 1 to 9.
11. An SOC chip, comprising:
an analog to digital converter as claimed in claim 10.
12. An electronic device, comprising:
the SOC chip of claim 11.
13. A voltage detection method, comprising:
acquiring an oscillation signal generated by a ring oscillator based on a voltage to be detected, wherein the frequency of the oscillation signal is related to the voltage to be detected;
sampling an oscillation signal output by each stage in the ring oscillator to obtain a ring oscillator state signal and integer times of oscillation times of the oscillation signal output by the last stage of the ring oscillator, wherein the ring oscillator state signal comprises the level state of the oscillation signal output by each stage of the ring oscillator, and the ring oscillator state signal is used for determining the decimal times of oscillation times of the ring oscillator;
and obtaining the oscillation times of the ring oscillator based on the ring oscillator state signal and the integer times of oscillation times, wherein the oscillation times of the ring oscillator are used for representing the voltage to be detected.
14. The method of claim 13, wherein the oscillating signal output by each stage in the ring oscillator is sampled during each clock cycle of the clock signal to obtain a ring oscillator state signal during each clock cycle and an integer multiple of oscillation times during each clock cycle;
accordingly, obtaining the oscillation frequency of the ring oscillator based on the ring oscillator state signal and the integer multiple of the oscillation frequency includes:
and obtaining the oscillation times of the ring oscillator based on the state signal of the ring oscillator in each clock period and the integral multiple oscillation times in each clock period.
15. The method of claim 14, wherein the deriving the number of oscillations of the ring oscillator based on the ring oscillator status signal per clock cycle, the integer multiple of oscillations per clock cycle, comprises:
based on the state signal of the ring oscillator in each clock period, the decimal oscillation times in each clock period are obtained;
obtaining the respective corresponding oscillation times of each clock cycle based on the integer times of oscillation times and the fraction times of oscillation times in each clock cycle;
And obtaining the oscillation times of the ring oscillator based on the respective oscillation times of each clock cycle.
CN202310584662.7A 2023-05-23 2023-05-23 Voltage detection circuit and method, analog-to-digital converter and SOC (system on chip) Active CN116626361B (en)

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US11264998B1 (en) * 2020-09-24 2022-03-01 Advanced Micro Devices, Inc. Reference free and temperature independent voltage-to-digital converter
CN114414066A (en) * 2022-01-18 2022-04-29 北京大学 Infrared imaging reading special integrated circuit and infrared imager
CN116087607A (en) * 2022-12-09 2023-05-09 海光信息技术股份有限公司 Current detection device and method thereof, low-dropout linear voltage regulator and electronic equipment

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11264998B1 (en) * 2020-09-24 2022-03-01 Advanced Micro Devices, Inc. Reference free and temperature independent voltage-to-digital converter
CN114414066A (en) * 2022-01-18 2022-04-29 北京大学 Infrared imaging reading special integrated circuit and infrared imager
CN116087607A (en) * 2022-12-09 2023-05-09 海光信息技术股份有限公司 Current detection device and method thereof, low-dropout linear voltage regulator and electronic equipment

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