JP2019092073A - Time-to-digital conversion circuit - Google Patents

Abstract

To realize a time-to-digital conversion circuit with reduced accuracy degradation.SOLUTION: The time-to-digital conversion circuit (1a) includes: an oscillation circuit (2); a phase sampling circuit (3); a clock generation circuit (4a); a counter circuit (5); and a decoding circuit (6a) for outputting a digital signal indicating a time from a start signal input to a stop signal input.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a time digital conversion circuit.

  Conventionally, voltage and current signals are generally used for analog digital signal processing. Further, an AD converter circuit, a DA converter circuit, an analog filter, or the like can be given as the signal processing circuit. On the other hand, in the ultra-fine CMOS process, it is difficult to secure the dynamic range of voltage and current signals because of the low power supply voltage, and it is difficult to realize a high-performance AD converter circuit, DA converter circuit, and analog filter. However, the digital circuit can operate at high speed even under a low power supply voltage because of the benefit of miniaturization, and the time resolution of the digital circuit is improved. By using a time signal for signal processing, it is possible to perform highly accurate signal processing in an ultra-fine CMOS process, but when using a time signal for analog-digital signal processing, a time-to-digital conversion circuit is required. Also, in order to secure the dynamic range, it is essential to improve the accuracy of the time digital conversion circuit.

  There are various circuit systems in the time digital conversion circuit, but the time digital conversion circuit using the oscillation circuit is a circuit system which can realize a high dynamic range with a simple configuration.

  Patent Document 1 and Non-Patent Document 1 below propose a time-to-digital converter circuit for avoiding the problem of metastability. In Non-Patent Documents 2 and 3, in a time digital conversion circuit using an oscillation circuit, the phase output signal of the oscillation circuit is not treated as a binary digital signal of 0, 1 but as an analog signal having subdivided voltage levels Techniques have been presented that enable high precision by handling and interpreting the phase more precisely.

US Patent 2015/0077279 A1 specification (released on March 19, 2015)

Matthias Fugger, Attila Kinali, Christoph Lenzen, and Thomas Polzer, “Metastability-Aware Memory-Efficient Time-to-Digital Converters,” In IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 2017 Shingo Mandai, "A Multi-channel Digital Silicon Photomultiplier with Column-Parallel Time-to-Digital Converter and Basic Characterization", IEEE Trans. On Nuclear Science vol. 61, Browse Journals & Magazines, no. 1, Feb. 2014, page 44-52 Singo Mandai, “Multichannel Digital Silicon Photomultipliers for Time-of-Flight PET”, TU Delft Library, the Netherlands, 1, July, 2014, page 74-80, 87-92

However, in the high precision technology described in Non-Patent Document 2 and Non-Patent Document 3 as described above,
-Metastability of the latch circuit due to setup time violation-Metastability of the latch circuit due to hold time violation-Clock skew-There is a problem regarding accuracy deterioration due to the timing deviation of the digital circuit due to individual differences among elements.

  In the time-to-digital converter circuits described in Non-Patent Documents 2 and 3, no method has been proposed for avoiding the above-mentioned accuracy deterioration.

  One aspect of the present invention is made in view of the above problems, and an object of the present invention is to realize a time-to-digital conversion circuit in which accuracy deterioration is suppressed.

  In order to solve the above problems, the time-to-digital converter according to one aspect of the present invention includes an oscillation circuit that outputs a plurality of phase signals and a stop that receives the plurality of phase signals and is input after the start signal is input. A phase sampling circuit that samples each of a plurality of phase signals and outputs an output signal according to the sampling result due to the input of the signal, and one of the plurality of phase signals is input, and the input of the stop signal A clock generation circuit that latches and outputs the one phase signal, a counter circuit that counts the output of the clock generation circuit and counts the period of the oscillation circuit, and an output of the phase sampling circuit The start signal input with reference to the signal, the counter value of the counter circuit, and the output or internal state of the clock generation circuit And a decode circuit for outputting a digital signal indicating the time of Luo to the stop signal input.

  According to one aspect of the present invention, it is possible to realize a time-to-digital conversion circuit in which accuracy degradation is suppressed.

It is an example of the conventional time digital conversion circuit. It is a conventional figure which shows the look-up table for calculating | requiring the value which concerns on calculation of the output signal of a time digital-conversion circuit from the digital output of a phase sampling circuit. It is a timing diagram which shows an example of the output signal in each element or circuit. It is a timing diagram which shows an example when a metastability problem or timing gap occurs. It is the schematic which shows a time digital conversion circuit. It is a figure which shows a look-up table. It is a timing diagram which shows an example of the output signal in each element or circuit. It is a timing diagram which shows an example when a metastability problem or timing gap occurs. It is an example of composition of the 1st to 4th phase sampling circuit.

Embodiment 1
First, with reference to FIG. 1, a time-to-digital converter which is a premise of the present invention will be described.

  FIG. 1 is a schematic diagram showing a time digital conversion circuit 1 which is a premise of the present invention.

  As shown in FIG. 1, the time digital conversion circuit 1 includes an oscillation circuit 2, phase sampling circuits 3 a to 3 d, a clock generation circuit 4, a counter circuit 5, and a decoding circuit 6.

  The START signal from the START terminal 8 and the STOP signal from the STOP terminal 9 are input to the time digital conversion circuit 1, and the STOP signal is inputted from the time when the START signal changes from Low (0) to High (1). Measure the time between when it changes from Low to High.

  The oscillation circuit 2 is a ring oscillation circuit including non-inverted delay elements 21 to 24 and an inverting element 25 that inverts the output PHI 3 of the delay element 24 and feeds it back to the delay element 21.

  Each of the delay elements 21 to 24 has a digital signal input terminal, a digital signal output terminal, and an enable control terminal, and delays the digital signal input to the digital signal input terminal from the digital signal output terminal for a predetermined fixed time. It outputs as an output signal (PHI0-3). The delay elements 21 to 24 start oscillation due to the input of the START signal, and when the input from the enable control terminal is low, do not perform delay operation and output a predetermined digital value set in advance, enable When the input from the control terminal is high, the delay operation is performed. The enable control terminal is connected to a START terminal which is a time measurement start signal of the time digital conversion circuit 1.

  The oscillation circuit included in the time digital conversion circuit 1 may be an oscillation circuit that is not of a ring type and that can realize the same function or a corresponding function.

  The phase sampling circuit (group) 3 includes a first phase sampling circuit 3a, a second phase sampling circuit 3b, a third phase sampling circuit 3c, and a fourth phase sampling circuit 3d.

  The first to fourth phase sampling circuits 3a to 3d sample the phase output signals (PHI 0 to 3) from the oscillation circuit 2 as analog signals, compare them with predetermined voltage levels, and output digital values (DPHI 0 to 3). Do.

  The phase sampling circuit 3a compares a buffer circuit 31a for amplifying an output signal of the oscillation circuit 2, a capacitor 32a for sampling the output signal, and the sampled output signal with a certain reference voltage level, and The comparator circuit 33a outputs the comparison result as a digital signal, and the delay circuit 34a for operating the comparator circuit 33a after a predetermined time has elapsed immediately after sampling. The phase signal means a signal having the same waveform periodically.

  Further, as shown in FIG. 1, the second to fourth phase sampling circuits 3b to 3d also have members corresponding to the members provided in the phase sampling circuit 3a.

  The first to fourth phase sampling circuits 3a to 3d sample the voltage levels of the phase signals (PHI0 to 3) when the STOP signal, which is a time measurement stop signal, changes from low to high.

  The clock generation circuit 4 includes a latch circuit 41 and a Schmitt trigger circuit 42.

  The latch circuit 41 is a circuit that can hold a value corresponding to 1 bit of High or Low. The latch circuit 41 receives the phase output signal PHI3 of the oscillation circuit 2 and the STOP signal, and outputs the value of the phase output signal PHI3 as it is to the Schmitt trigger circuit 42 while the STOP signal is low. While High, the value of the output signal at the time when the STOP signal changes from Low to High is held.

  The Schmitt trigger circuit 42 is a circuit that can remove noise of an input signal. The Schmitt trigger circuit 42 has two large and small thresholds, and when the input signal has a value larger than the larger threshold, outputs a signal that is High, and the input signal has a smaller value than the smaller threshold. If there is, it outputs a signal that is Low. If the input signal is greater than or equal to the smaller threshold and less than or equal to the larger threshold, the immediately preceding output is continuously output.

  The Schmitt trigger circuit 42 is preferably disposed downstream of the latch circuit 41 in order to avoid the problem of metastability due to the setup / hold time violation of the latch circuit 41.

  That is, the clock generation circuit 4 includes the Schmitt trigger circuit 42, and the clock signal shaped by the Schmitt trigger circuit 42 is input to the counter circuit 5.

  By the operation of the clock generation circuit 4, the counter circuit 5 can count the oscillation cycle of the oscillation circuit 2 during the period until the START signal is set to High and the STOP signal becomes High.

  The counter circuit 5 is a ripple counter type counter composed of a plurality of flip flops, and counts falling of the input signal from high to low.

  The decoding circuit 6 decodes from the outputs DPHI 0 to 3 of the phase sampling circuits 3 a to 3 d and the digital output MSB_CNT of the counter circuit 5.

  FIG. 2 is a diagram showing a look-up table for obtaining LSB_DEC which is a value related to the calculation of the output signal DOUT of the time digital conversion circuit 1 from the digital outputs DPI0 to DPI3 of the phase sampling circuits 3a to 3d. For example, when DPHI0 = 1, DPHI1 = 1, DPHI2 = 1, and DPHI3 = 0, the value of LSB_DEC is 3 from FIG.

From the LSB_DEC and the output MSB_CNT of the counter circuit 5, the output DOUT of the decoding circuit 6 is calculated according to the following equation, and is used as the output signal of the time digital conversion circuit 1.
DOUT = LSB_DEC + MSB_CNT · 8
The high resolution time digital conversion circuit 1 which outputs a value based on the count value (MSB_CNT) from the counter circuit 5 and the output signal (DPHI 0 to 3) of the phase sampling circuit 3 by performing the above-described decoding The effect of being able to be realized is achieved.

  However, since the time-to-digital converter 1 handles signals of pico-second order, there is a secondary problem that unexpected timing deviation and metastability problems occur.

  Hereinafter, the problem of metastability will be described based on FIGS. 3 and 4.

  FIG. 3 is a timing chart showing an example of an output signal in each element or circuit.

  In FIG. 3, the START signal is set to High at timing T0 (not shown), and after PHI3 (input signal of clock generation circuit 4) has counted High to Low falling N times at Tn, then PHI3 falls. The figure shows the case where the STOP signal changes from low to high immediately before counting and at substantially the same timing TS2.

  Since PHI0 = 0, PHI1 = 0, PHI2 = 0, and PHI3 = 1 at the time of TS2 are sampled, DPHI0 = 0, DPHI1 = 0, DPHI2 = 0, and DPHI3 = 1 are output from the phase sampling circuit. Further, from FIG. 2, LSB_DEC = 7. Since the value of the ripple counter is N and MSB_CNT = N, DOUT = 7 + 8N. FIG. 3 is an ideal case where there is no problem of timing deviation or metastability.

  FIG. 4 is a timing diagram illustrating an example where a metastability problem or timing deviation occurs.

  Similarly to the case shown in FIG. 3, after the START signal is set to High at timing T0 (not shown) and N falling edges of PHI 3 are counted N times at T n, the timing is immediately before the next falling edge of PHI 3 It shows the case where the STOP signal changes from low to high at substantially the same timing TS2.

  However, unlike the case shown in FIG. 3, due to the problem of metastability of latch circuit 41 in clock generation circuit 4 or the occurrence of timing deviation, falling of PHI 3 is counted by counter circuit 5 prior to TS 2. ing.

  In the above case, since DPHI0 = 0, DPHI1 = 0, DPHI2 = 0, and DPHI3 = 1, although LSB_DEC = 7 in FIG. 2 because the count value of the counter circuit is N + 1, MSB_CNT = N + 1. , DOUT = 7 + 8 · (N + 1).

  As described above, the occurrence of metastability problems or timing deviation may cause the measurement results (DOUT) to have different values. If such a thing occurs, the accuracy of measurement will deteriorate.

  Next, the time-to-digital converter circuit 1a according to the first embodiment of the present invention will be described with reference to FIGS. The time digital conversion circuit 1a is to avoid the accuracy deterioration due to the metastability problem of the latch circuit or the timing deviation of the digital circuit.

  For the sake of convenience, the same reference numerals are appended to members having the same functions as the members in the description using the above time digital conversion circuit 1, and the description will be omitted.

FIG. 5 is a schematic diagram showing the time digital conversion circuit 1a. As shown in FIG. 5, the time digital conversion circuit 1a includes an oscillation circuit 2, a phase sampling circuit (group) 3, a clock generation circuit 4a, a counter circuit 5, and a decode circuit 6a.
The oscillation circuit 2 is a ring type oscillation circuit in which delay elements are arranged in a ring shape, and is a single end type composed of a 1 input 1 output delay element to simplify the description. It is also possible to configure a differential and ring oscillation circuit in which two-input and two-output delay elements are formed in a ring shape.

  By using a differential oscillation circuit, it is possible to realize a time-to-digital conversion circuit that is less susceptible to the effects of power supply and ground noise.

  The first to fourth phase sampling circuits 3a to 3d included in the phase sampling circuit 3 sample the phase output signals (PHI 0 to 3) from the oscillation circuit 2 as analog signals and compare them with predetermined voltage levels to obtain digital values Output DPHI 0 to 3).

  The clock generation circuit 4 a includes a Schmitt trigger circuit 42, and the clock signal shaped by the Schmitt trigger circuit 42 is input to the counter circuit 5.

  Due to metastability problems, it is possible for the latch circuit 41 to generate very short parasitic pulses. At this time, even when the correction method shown in the present invention is used, the problem of metastability can not be avoided. By providing the Schmitt trigger circuit 42, the metastability problem can be avoided more reliably.

  In addition to the digital outputs DPHI0, DPHI1, DPHI2, and DPHI3 of the phase sampling circuits 3a to 3d and the digital output MSB_CNT of the counter circuit 5, the decode circuit 6a receives the output signal CLK3 of the latch circuit 41 included in the clock generation circuit 4a. The configuration is different from that of the time digital conversion circuit 1 shown in FIG. 1 in that it is input.

  The above configuration is an example, and does not necessarily mean that the configuration must be the same as that of the time digital conversion circuit 1 a when the present invention is implemented.

  FIG. 6 is a diagram showing a look-up table.

  According to the look-up table shown in FIG. 6, LSB_DEC which is a value related to the calculation of the output signal DOUT of the time digital conversion circuit 1a from the digital outputs DPI0 to DPI3 of the phase sampling circuits 3a to 3d and the output signal of the clock generation circuit 4a. And MSB_CAL can be determined. For example, when DPHI0 = 1, DPHI1 = 1, DPHI2 = 0, DPHI3 = 0, and CLK3 = 0, as shown in FIG. 6, LSB_DEC = 2 and MSB_CAL = 0.

From the LSB_DEC, MSB_CAL, and the output signal MSB_CNT of the counter circuit 5, the output DOUT 'of the decode circuit 6a is calculated according to the following equation, and is used as the output signal of the time digital conversion circuit 1a.
DOUT '= LSB_DEC + (MSB_CAL + MSB_CNT) · 8
In the above description, the decode circuit 6a generates the LSB_DEC and the new reference signal MSB_CAL from the digital outputs DPI0 to DPI3 of the phase sampling circuits 3a to 3d, the output CLK3 of the clock generation circuit 4a, and the reference signal And the digital signal DOUT 'corresponding to the counter value MSB_CNT of the counter circuit 5 can be reworded. Further, by using the value of MSB_CAL together with the reference signal LSB_DEC for calculating the output DOUT ′ of the decoding circuit 6a, as will be described later, it is possible to correct a mismatch derived from the metastability problem or timing deviation. it can.

  By checking the value of MSB_CAL, it can be checked whether a mismatch due to metastability, clock skew or timing deviation has occurred. Specifically, when the value of MSB_CAL is 0, the above mismatch does not occur, but when the value of MSB_CAL is 1 or -1, the above mismatch occurs.

  FIG. 7 is a timing chart showing an example of an output signal in each element or circuit.

  FIG. 7 is a timing chart showing an ideal case where no metastability problem or timing deviation occurs, and the STOP signal is from Low to High when the START signal is already at High level (1). It is a timing diagram at the time of switching to.

  During a period in which the START signal is High, the oscillation circuit 2 performs an oscillation operation, and the output waveforms of the delay elements 21 to 24 become waveforms shown by PHI 0 to 3.

  The counter circuit 5 counts the falling from high to low of the output signal of the clock generation circuit 4a after the START signal becomes high, and the output is updated as 0, 1,..., N−1, N. The phase sampling circuits 3a to 3d sample the output of the delay element when the STOP signal changes to 1, and output 0 or 1 by comparing the intermediate value between the high level and the low level of the delay element. Each comparator circuit outputs a value of 0 or 1 according to the value of PHI 0 to 3 sampled at the moment when the STOP signal becomes 1 (in the present embodiment, as an example, (DPHI0, DPHI1, DPHI2, DPHI3) = (0, 0, 0, 1)). Further, in the clock generation circuit 4a, the input value from the output signal PHI3 of the oscillation circuit 2 is latched (in the present embodiment, for example, the state of CLK3 = 1 is held). From the above sampled or latched values DPHI0 to 3 and CLK3, according to FIG. 6, LSB_DEC = 7, MSB_CAL = 0, and DOUT 'becomes 7 + 8 N which is an ideal value.

  In the time-to-digital converter 1a of the present invention, even if metastability problems of the latch circuit 41 or timing deviation of the digital circuit occur, a mismatch occurs between the output of the counter circuit 5 and the outputs of the phase sampling circuits 3a to 3d. It will be explained that it is possible to avoid the problem of metastability and the problem derived from the timing deviation, without doing it.

  FIG. 8 is a timing chart showing an example when a mismatch occurs in the latch circuit 41. As shown in FIG.

  The description of signals having the same phase as in FIG. 7 will be omitted, and only differences will be described.

  FIG. 8 is a timing chart showing an example when a metastability problem or timing deviation occurs.

  As shown in FIG. 8, since the phase of the output signal CLK3 of the latch circuit 41 slightly leads the phase of the output signal PHI3 of the oscillation circuit 2 due to circuit variation or the like, when the STOP signal becomes 1, PHI3 and Since a timing shift occurs between CLK3 and CLK3 and the latch circuit 41 holds Low (0) instead of High (1), CLK3 becomes Low (0).

  In the above case, when the output of the time-to-digital converter 1a is calculated according to FIG. 2, DOUT (no correction) = 15 + 8N, and due to the timing shift, the value is settled different from DOUT (ideal). On the other hand, when calculated according to FIG. 6, DOUT '(with correction) = 7 + 8N, which is the same value as DOUT (ideal). From this, according to the correction method, even if the timing deviation occurs, the performance of the time digital conversion circuit 1a is not degraded.

  Decode circuit 6a has a configuration in which latch circuit 41 and decode circuit 6a are directly connected if output signal CLK3 from latch circuit 41, in other words, the internal state of clock generation circuit 4a can be obtained. It is not limited.

  That is, the decode circuit 6a generates the LSB_DEC and the reference signal MSB_CAL according to the output signal CLK3 or the internal state of the clock generation circuit 4a and the output signals DPHI0 to DPHI3 of the phase sampling circuits 3a to 3d, and the timing error Detect what happened.

  Thus, by using the value of the reference signal MSB_CAL together with LSB_DEC for the calculation of the output DOUT ′ of the decode circuit 6a, in other words, the clock generation circuit 4a together with the output signals DPHI0 to DPHI3 of the phase sampling circuits 3a to 3d. Can be used to calculate the output signal CLK3 or the internal state of the decoder 6a to calculate the output DOUT 'of the decoding circuit 6a, it is possible to correct the mismatch due to the metastability problem or the timing deviation.

  As described above, the time digital conversion circuit 1a receives the oscillation circuit 2 that outputs a plurality of phase signals, and the input of the stop signal that is input after the input of the start signal after the input of the plurality of phase signals. The phase sampling circuits 3a to 3d which sample each of the plurality of phase signals and output an output signal according to the sampled result, and one of the plurality of phase signals are input, and due to the input of the stop signal, The clock generation circuit 4a which latches and outputs the one phase signal, the counter circuit 5 which counts the output of the clock generation circuit 4a and counts the period of the oscillation circuit 2, and the outputs of the phase sampling circuits 3a to 3d With reference to the signal, the counter value of the counter circuit 5, and the output or internal state of the clock generation circuit 4a, And a decoding circuit 6a which outputs a digital signal indicating the time to the stop signal input.

  According to the above configuration, it is possible to realize the time digital conversion circuit 1a in which the accuracy deterioration is suppressed.

  Hereinafter, a configuration example of the phase sampling circuit 3 will be described.

  FIG. 9 is a configuration example of the first to fourth phase sampling circuits 3a to 3d.

  The phase sampling circuits 3a to 3d are disposed between the output terminal of the inverter circuit and the capacitor 32. The inverter circuit includes switching elements MN1 and MP2 arranged to transmit the input signal to the capacitor 32 and the comparator input terminal. Sampling switch SW1, a capacitor 32 for holding the sampled voltage signal, resistors R1 and R2 for generating an intermediate voltage between the power supply voltage VDD and the ground level, and the intermediate voltage level sampled And a comparator circuit 33 that compares voltage signals and outputs a signal that is High or Low as a logic level.

  The switching elements MN1 and MP2 are FETs (Field Effect Transistors), and correspond to components of the buffer circuits 31a to 31d in the first to fourth phase sampling circuits 3a to 3d.

  When the STOP signal is low, the capacitor 32 is connected to the output terminal of the inverter circuit, and the inverted signal of the output voltage of the oscillation circuit 2 is transmitted to the capacitor 32. At the moment when the STOP signal changes from low to high, the sampling switch SW1 is turned off, and the voltage value at that moment is held in the capacitor 32. After the voltage held in the capacitor 32 is stabilized, the STOP signal is transmitted to the comparator circuit 33, the voltage held in the capacitor 32 is compared with the intermediate voltage level, and the comparator circuit 33 takes a logic level. Output a signal that is High or Low.

  As described above, the phase sampling circuits 3a to 3d include an analog signal sampling circuit including the capacitor 32 and the switch SW1, and each of the sampling circuits samples the phase signal as an analog voltage signal.

  Treating each phase signal of the oscillation circuit 2 as an analog signal, comparing the voltage held in the capacitor 32 with not only one intermediate voltage level but with a plurality of reference voltage levels, or combining and comparing each phase signal Thus, the time resolution of the phase sampling circuit can be improved.

  By performing the decoding as in this embodiment, the count value (MSB_CNT) in the counter circuit 5, the phase signals (DPHI0 to 3) of the oscillation circuit 2, and the output signal from the latch circuit 41 latched by the STOP signal (CLK3 And a high resolution time digital conversion circuit 1a that outputs a value based on the above.

  In the present embodiment, to simplify the description, the input signals of phase sampling circuits 3a to 3d are the corresponding output signal 1 inputs of oscillation circuit 2, and the predetermined voltage levels to be compared in comparator circuits 33a to 33d are Although it is an intermediate value between the high level and the low level of each input signal (PHI0 to 3), the present invention is also applicable to the configurations as described in Non-Patent Documents 2 and 3. In addition, although the oscillation circuit 2 is a single-ended system in order to simplify the description here, it is easier to improve the performance by using a fully differential oscillation circuit.

[Summary]
The time-to-digital converter circuit 1a according to aspect 1 of the present invention includes the oscillation circuit 2 that outputs a plurality of phase signals, and the input of the stop signal that is input after the start of the start signal. , Phase sampling circuits 3a to 3d which sample each of the plurality of phase signals and output an output signal according to the sampled result, and one of the plurality of phase signals is input, resulting from the input of the stop signal A clock generation circuit 4a which latches and outputs the one phase signal, a counter circuit 5 which counts the output of the clock generation circuit 4a and counts the period of the oscillation circuit, and the phase sampling circuit 3a to With reference to the 3d output signal, the counter value of the counter circuit 5, and the output or internal state of the clock generation circuit 4a, From start signal input is configured to include a decoding circuit 6a which outputs a digital signal indicating the time to the stop signal input.

  According to the above configuration, it is possible to realize the time digital conversion circuit 1a in which the accuracy deterioration is suppressed.

  In the time digital conversion circuit 1a according to aspect 2 of the present invention, in the above aspect 1, the decoding circuit 6a outputs the output or the internal state of the clock generation circuit 4a and the output signals of the phase sampling circuits 3a to 3d. A configuration may be adopted in which a corresponding reference signal is generated to detect that a timing error has occurred.

  According to the above configuration, reference signals corresponding to the output CLK3 or the internal state of the clock generation circuit 4a and the output signals DPHI0 to DPHI3 of the phase sampling circuits 3a to 3d are used to calculate the output DOUT 'of the decode circuit 6a. In this way, it is possible to correct for inconsistencies due to metastability problems or timing deviations.

  In the time digital conversion circuit 1a according to aspect 3 of the present invention, in the above aspect 1 or 2, each of the phase sampling circuits 3a to 3d includes an analog signal sampling circuit composed of a capacitor 32 and a switch SW1. The sampling circuit may be configured to sample the phase signal as an analog voltage signal.

  According to the above configuration, each phase signal of oscillation circuit 2 is treated as an analog signal, and the voltage held by capacitor 32 is compared not only with the one intermediate voltage level but with a plurality of reference voltage levels, or each phase By combining and comparing the signals, it is possible to improve the time resolution of the phase sampling circuit.

  In the time-to-digital converter 1a according to aspect 4 of the present invention, in any of the above-mentioned aspects 1 to 3, the clock generation circuit 4a includes a Schmitt trigger circuit 42, and the counter circuit 5 includes the Schmitt trigger The clock signal shaped by the circuit 42 may be input.

  According to the above configuration, by providing the Schmitt trigger circuit 42, the problem of metastability can be avoided more reliably.

  According to the above configuration, there is an effect that false detection in the counter circuit 5 can be prevented.

  In the time-to-digital converter circuit 1a according to aspect 5 of the present invention, in any of the above-mentioned aspects 1 to 4, the oscillation circuit 2 is a ring type oscillation circuit, and a differential is constituted by differential type delay elements. The configuration may be an oscillator circuit.

  According to the above configuration, by using the differential oscillation circuit, it is possible to realize a time-to-digital conversion circuit that is not easily affected by the power supply and the ground noise.

  The present invention is not limited to the embodiments described above, and various modifications are possible within the scope of the claims.

DESCRIPTION OF SYMBOLS 1, 1a time digital conversion circuit 2 oscillation circuit 3, 3a-3d phase sampling circuit 4, 4a clock generation circuit 5 counter circuit 6, 6a decoding circuit 8 START terminal 9 STOP terminal 21-24 delay element 25 inversion element 31a-31d buffer Circuits 32a-32d Capacitors
33a to 33d comparator circuit 34a to 34d delay circuit 41 latch circuit 42 Schmitt trigger circuit

Claims (5)

An oscillator circuit that outputs a plurality of phase signals;
A phase sampling circuit that receives the plurality of phase signals and samples each of the plurality of phase signals due to the input of the stop signal input after the start signal is input, and outputs an output signal according to the sampled result ,
A clock generation circuit which receives one of the plurality of phase signals and latches and outputs the one phase signal due to the input of the stop signal;
A counter circuit that counts the output of the clock generation circuit and counts the period of the oscillation circuit;
Referring to the output signal of the phase sampling circuit, the counter value of the counter circuit, and the output or internal state of the clock generation circuit, a digital signal indicating the time from the start signal input to the stop signal input is output. A time-to-digital converter circuit comprising: The above decode circuit
The output or internal state of the clock generation circuit;
Generates a reference signal according to the output signal of the phase sampling circuit,
The time-to-digital converter circuit according to claim 1, which detects that a timing error has occurred. The phase sampling circuit comprises an analog signal sampling circuit composed of a capacitor and a switch,
The time-to-digital converter according to claim 1 or 2, wherein each of the sampling circuits samples a phase signal as an analog voltage signal. The clock generation circuit includes a Schmitt trigger circuit,
The above counter circuit
The time-to-digital converter circuit according to any one of claims 1 to 3, wherein a clock signal shaped by the Schmitt trigger circuit is input. The above oscillation circuit is a ring oscillation circuit,
The time-to-digital converter circuit according to any one of claims 1 to 4, which is a differential oscillation circuit constituted by differential delay elements.

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