CN114400223A - High-integration double-sided heat dissipation packaging structure with single ceramic substrate - Google Patents
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- CN114400223A CN114400223A CN202210039293.9A CN202210039293A CN114400223A CN 114400223 A CN114400223 A CN 114400223A CN 202210039293 A CN202210039293 A CN 202210039293A CN 114400223 A CN114400223 A CN 114400223A
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- 239000000758 substrate Substances 0.000 title claims abstract description 32
- 239000000919 ceramic Substances 0.000 title claims abstract description 31
- 230000017525 heat dissipation Effects 0.000 title claims abstract description 20
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 88
- 239000002184 metal Substances 0.000 claims abstract description 88
- 238000001465 metallisation Methods 0.000 claims description 51
- 239000011159 matrix material Substances 0.000 claims description 16
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 13
- 238000005245 sintering Methods 0.000 claims description 11
- 230000009466 transformation Effects 0.000 claims description 8
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 48
- 229910010271 silicon carbide Inorganic materials 0.000 description 48
- 238000004891 communication Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a high-integration single-ceramic-substrate double-sided heat dissipation packaging structure which comprises a ceramic substrate, a SiC Schottky diode of an upper bridge arm, a SiC MOSFET of an upper bridge arm, a SiC Schottky diode of a lower bridge arm, a SiC MOSFET of a lower bridge arm, a first metal terminal cover plate, a second metal terminal cover plate, a third metal terminal cover plate, a fourth metal terminal cover plate, a fifth metal terminal cover plate, a sixth metal terminal cover plate and a seventh metal terminal cover plate.
Description
Technical Field
The invention relates to a packaging structure, in particular to a high-integration double-sided heat dissipation packaging structure with a single ceramic substrate.
Background
With the rapid development of power electronic technology, AC-AC matrix converters are widely used in industry. Compared with the traditional natural conversion frequency converter, the matrix converter has the advantages of quick dynamic response, capability of realizing four-quadrant operation of the motor, controllable output power factor and continuously adjustable output voltage and frequency range.
The SiC device increasingly replaces the Si device with its advantages of low on-resistance, high breakdown voltage, high switching speed, and low switching loss, and becomes an important component of the matrix converter. This increases the power density of the matrix converter to a certain extent.
However, the current commercial matrix converter module package has the following problems: firstly, a single-sided ceramic substrate structure is adopted, the heat dissipation efficiency is low, the parasitic inductance of a plane power loop is large, all chips are integrated in one module, when a single chip is damaged, the chip cannot be flexibly replaced, the whole module is scrapped, and secondly, the cascade connection is not easy, and the flexible change of the matrix converter structure is not easy.
In order to solve the above problems, it is important to design a matrix converter sub-module with high integration level, low parasitic parameters, high heat dissipation efficiency, high power density, and convenient for cascading.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a high-integration double-sided heat dissipation packaging structure with a single ceramic substrate, which has the characteristics of high integration level, low parasitic parameter, high heat dissipation efficiency, high power density and convenience for cascading.
In order to achieve the above purpose, the highly integrated single ceramic substrate double-sided heat dissipation package structure of the invention comprises a ceramic substrate, a SiC schottky diode of an upper bridge arm, a SiC MOSFET of the upper bridge arm, a SiC schottky diode of a lower bridge arm, a SiC MOSFET of the lower bridge arm, a first metal terminal cover plate, a second metal terminal cover plate, a third metal terminal cover plate, a fourth metal terminal cover plate, a fifth metal terminal cover plate, a sixth metal terminal cover plate and a seventh metal terminal cover plate;
a first grid metalized area, a first Kelvin source metalized area, a first metalized area, a second power source (midpoint AC) metalized area, a first power source (midpoint AC) metalized area and a third grid metalized area are arranged on one side surface of the ceramic substrate;
a second gate metalized region, a second Kelvin source metalized region, a second metalized region, a fourth power source (midpoint AC) metalized region, a third power source (midpoint AC) metalized region and a fourth gate metalized region are arranged on the other side surface of the ceramic substrate;
the SiC MOSFET of the upper bridge arm is connected with a third grid metalized area and a first power source electrode (midpoint AC) metalized area, the third grid metalized area is electrically communicated with a second grid metalized area through a through hole, the second grid metalized area is connected with a fourth metal terminal cover plate, and the fourth metal terminal cover plate is a grid electrode of the SiC MOSFET of the upper bridge arm correspondingly; the first power source electrode (midpoint AC) metalized area is electrically communicated with the second Kelvin source electrode metalized area through a through hole, the second Kelvin source electrode metalized area is connected with a fifth metal terminal cover plate, and the fifth metal terminal cover plate is a Kelvin source electrode of the upper bridge arm SiC MOSFET correspondingly;
the SiC Schottky diode of the upper bridge arm is connected with a second power source electrode (midpoint AC) metalized area, the drain electrode of the SiC MOSFET of the upper bridge arm is connected with the cathode of the SiC Schottky diode of the upper bridge arm through a third metal terminal cover plate, and the third metal terminal cover plate is a DC + end corresponding to a submodule of the matrix transformation;
the second power source electrode (midpoint AC) metalized area is electrically communicated with the fourth power source electrode (midpoint AC) metalized area through a through hole, the second power source electrode (midpoint AC) metalized area is electrically communicated with the third metalized area through a through hole, a seventh metal terminal cover plate is connected with the third metalized area, and the seventh metal terminal cover plate corresponds to a midpoint AC end of a submodule of the matrix transformation;
the SiC MOSFET of the lower bridge arm is connected with a fourth grid metalized area and a third power source electrode (midpoint AC) metalized area, wherein the fourth grid metalized area is electrically communicated with the first grid metalized area through a through hole, the first grid metalized area is connected with a first metal terminal cover plate, and the first metal terminal cover plate is a grid electrode of the SiC MOSFET of the lower bridge arm correspondingly; the third power source (midpoint AC) metalized area is electrically communicated with the first Kelvin source metalized area through a through hole, the first Kelvin source metalized area is connected with a second metal terminal cover plate, and the second metal terminal cover plate is a Kelvin source electrode corresponding to the lower bridge arm SiC MOSFET;
the SiC Schottky diode of the lower bridge arm is connected with a fourth power source electrode (midpoint AC) metalized area, the drain electrode of the SiC MOSFET of the lower bridge arm is connected with the cathode of the SiC Schottky diode of the lower bridge arm through a sixth metal terminal cover plate, and the sixth metal terminal cover plate corresponds to a DC-end of a submodule of the matrix transformation.
And the SiC MOSFET of the upper bridge arm is connected with the third grid metalized region and the first power source electrode (midpoint AC) metalized region through nano silver sintering.
The SiC Schottky diode of the upper bridge arm is connected with a second power source electrode (midpoint AC) metalized area through nano-silver sintering.
And the seventh metal terminal cover plate is connected with the third metalized area through nano-silver sintering.
And the SiC MOSFET of the lower bridge arm is connected with the fourth grid metalized region and the third power source electrode (midpoint AC) metalized region through nano silver sintering.
The SiC schottky diode of the lower leg is connected to a fourth power source (midpoint AC) metallization region by nano-silver sintering.
The invention has the following beneficial effects:
the high-integration single-ceramic substrate double-side heat dissipation packaging structure disclosed by the invention is pasted in an inverted mode during specific operation, a bonding wire is not needed, the reliability of a module is greatly improved, the size is small, the power density is high, the cascade connection is convenient, and the integration level is high. In addition, the ceramic substrate is adopted, so that the heat dissipation efficiency is high, and the ceramic substrate can be used at the measurement temperature of 500 ℃. In addition, the invention adopts a double-sided arrangement mode, increases a heat dissipation path, has smaller thermal resistance and higher heat dissipation efficiency compared with the traditional single-sided module, and effectively improves high-temperature bending caused by different thermal expansion coefficients of metal and ceramic. In addition, the invention can realize the package cascade connection or the connection with other parts of the module, simultaneously realize small parasitic parameters and reduce the system loss. Meanwhile, a metal terminal cover plate is adopted for leading out, so that the adverse effects of large voltage and large current of the power loop on the control loop are eliminated.
Drawings
FIG. 1 is a schematic side view of a ceramic substrate 100;
fig. 2 is a schematic view of another side of the ceramic substrate 100;
fig. 3 is a position diagram of the SiC schottky diode 114 of the upper arm and the SiC MOSFET115 of the upper arm;
fig. 4 is a position diagram of the SiC schottky diode 116 of the lower arm and the SiC MOSFET117 of the lower arm;
fig. 5 is a position view of the first metal terminal cover 118, the second metal terminal cover 119 and the third metal terminal cover 120;
fig. 6 is a position view of the fourth metal terminal cover 121, the fifth metal terminal cover 122, the sixth metal terminal cover 123 and the seventh metal terminal cover 124;
fig. 7 is a schematic circuit diagram of the present invention.
Wherein 100 is a ceramic substrate, 101 is a first gate metallization region, 102 is a first kelvin source metallization region, 103 is a second gate metallization region, 104 is a second kelvin source metallization region, 105 is a first metallization region, 106 is a first power source (midpoint AC) region, 107 is a third gate metallization region, 108 is a second power source (midpoint AC) metallization region, 109 is a second metallization region, 110 is a third power source (midpoint AC) metallization region, 111 is a fourth gate metallization region, 112 is a fourth power source (midpoint AC) metallization region, 113 is a third metallization region, 114 is a SiC schottky diode of an upper leg, 115 is a SiC MOSFET of an upper leg, 116 is a SiC schottky diode of a lower leg, 117 is a SiC MOSFET of a lower leg, 118 is a first metal terminal cap, 119 is a second metal terminal cap, 119, and, A third metal terminal cover plate 120, a fourth metal terminal cover plate 121, a fifth metal terminal cover plate 122, a sixth metal terminal cover plate 123, and a seventh metal terminal cover plate 124.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments, and are not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
There is shown in the drawings a schematic block diagram of a disclosed embodiment in accordance with the invention. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers and their relative sizes and positional relationships shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, according to actual needs.
Referring to fig. 1 to 7, the highly integrated single ceramic substrate double-sided heat dissipation package structure of the present invention includes a ceramic substrate 100, an upper arm SiC schottky diode 114, an upper arm SiC MOSFET115, a lower arm SiC schottky diode 116, a lower arm SiC MOSFET117, a first metal terminal cover 118, a second metal terminal cover 119, a third metal terminal cover 120, a fourth metal terminal cover 121, a fifth metal terminal cover 122, a sixth metal terminal cover 123, and a seventh metal terminal cover 124;
a first gate metallization region 101, a first kelvin source metallization region 102, a first metallization region 105, a second power source (midpoint AC) metallization region 108, a first power source (midpoint AC) metallization region 106, and a third gate metallization region 107 are disposed on one side of the ceramic substrate 100;
a second gate metallization region 103, a second kelvin source metallization region 104, a second metallization region 109, a fourth power source (midpoint AC) metallization region 112, a third metallization region 113, a third power source (midpoint AC) metallization region 110, and a fourth gate metallization region 111 are disposed on the other side of the ceramic substrate 100;
the SiC MOSFET115 of the upper leg is connected to a third gate metallization region 107 and a first power source (midpoint AC) metallization region 106, the third gate metallization region 107 is in electrical communication with the second gate metallization region 103 through a via, the second gate metallization region 103 is connected to a fourth metal terminal cover 121, and the fourth metal terminal cover 121 corresponds to the gate of the SiC MOSFET of the upper leg; the first power source (midpoint AC) metalized region 106 is in electrical communication with the second kelvin source metalized region 104 through a via hole, the second kelvin source metalized region 104 is connected with a fifth metal terminal cover 122, and the fifth metal terminal cover 122 corresponds to a kelvin source of the upper arm SiC MOSFET;
the SiC schottky diode 114 of the upper arm is connected to the second power source (midpoint AC) metallization region 108, the drain of the SiC MOSFET of the upper arm is connected to the cathode of the SiC schottky diode of the upper arm through a third metal terminal cover 120, the third metal terminal cover 120 is the DC + terminal corresponding to the submodule of the matrix transformation;
the second power source (midpoint AC) metalized area 108 and the fourth power source (midpoint AC) metalized area 112 are in electrical communication through a via, the second power source (midpoint AC) metalized area 108 is in electrical communication with the third metalized area 113 through a via, the seventh metal terminal cover 124 is connected to the third metalized area 113, and the seventh metal terminal cover 124 corresponds to a midpoint AC terminal of a sub-module of the matrix transformation;
the SiC MOSFET117 of the lower leg is connected to a fourth gate metalized region 111 and a third power source (midpoint AC) metalized region 110, wherein the fourth gate metalized region 111 is in electrical communication with the first gate metalized region 101 through a via, the first gate metalized region 101 is connected to a first metal terminal cover 118, and the first metal terminal cover 118 is a gate corresponding to the SiC MOSFET of the lower leg; a third power source (midpoint AC) metalized region 110 is in electrical communication with the first kelvin source metalized region 102 through a via, the first kelvin source metalized region 102 is connected with a second metal terminal cover 119, and the second metal terminal cover 119 is a kelvin source corresponding to the lower leg SiC MOSFET;
the SiC schottky diode 116 of the lower leg is connected to the fourth power source (midpoint AC) metalized region 112, the drain of the SiC MOSFET of the lower leg is connected to the cathode of the SiC schottky diode of the lower leg through a sixth metal terminal cover 123, and the sixth metal terminal cover 123 corresponds to the DC-terminal of the sub-module of the matrix converter.
The ceramic substrate 100 uses a silicon nitride material having a suitable size because the silicon nitride material satisfies the manufacturing requirements and has a more excellent heat conductive property, and the corresponding region on the silicon nitride ceramic material is metallized and plated with gold for electrical connection, and the plated with gold is convenient for mounting the chip using a nano-silver high-temperature material and sealing the cover plate.
The silicon carbide semiconductor chip is reversely mounted on one side of the ceramic substrate through nano-silver sintering, the nano-silver material is coated on the bottom of the semiconductor chip and then placed in a corresponding metalized area, and after the silicon carbide semiconductor chip is preheated for 10 minutes, the silicon carbide semiconductor chip is sintered for 2 hours at 280 ℃ in a vacuum or nitrogen environment, so that mounting is completed.
Claims (6)
1. A high-integration single-ceramic-substrate double-sided heat dissipation packaging structure is characterized by comprising a ceramic substrate (100), an SiC Schottky diode (114) of an upper bridge arm, an SiC MOSFET (115) of the upper bridge arm, an SiC Schottky diode (116) of a lower bridge arm, an SiC MOSFET (117) of the lower bridge arm, a first metal terminal cover plate (118), a second metal terminal cover plate (119), a third metal terminal cover plate (120), a fourth metal terminal cover plate (121), a fifth metal terminal cover plate (122), a sixth metal terminal cover plate (123) and a seventh metal terminal cover plate (124);
a first gate metallization region (101), a first Kelvin source metallization region (102), a first metallization region (105), a second power source (midpoint AC) metallization region (108), a first power source (midpoint AC) metallization region (106), and a third gate metallization region (107) are arranged on one side surface of the ceramic substrate (100);
a second gate metallization region (103), a second kelvin source metallization region (104), a second metallization region (109), a fourth power source (midpoint AC) metallization region (112), a third metallization region (113), a third power source (midpoint AC) metallization region (110), and a fourth gate metallization region (111) are arranged on the other side surface of the ceramic substrate (100);
the SiC MOSFET (115) of the upper bridge arm is connected with a third grid metalized area (107) and a first power source (midpoint AC) metalized area (106), the third grid metalized area (107) is electrically communicated with a second grid metalized area (103) through a through hole, the second grid metalized area (103) is connected with a fourth metal terminal cover plate (121), and the fourth metal terminal cover plate (121) is correspondingly a grid of the SiC MOSFET of the upper bridge arm; the first power source (midpoint AC) metalized area (106) is electrically communicated with the second Kelvin source metalized area (104) through a through hole, the second Kelvin source metalized area (104) is connected with a fifth metal terminal cover plate (122), and the fifth metal terminal cover plate (122) is a Kelvin source electrode of the upper bridge arm SiC MOSFET correspondingly;
the SiC Schottky diode (114) of the upper bridge arm is connected with a second power source electrode (midpoint AC) metalized area (108), the drain electrode of the SiC MOSFET of the upper bridge arm is connected with the cathode of the SiC Schottky diode of the upper bridge arm through a third metal terminal cover plate (120), and the third metal terminal cover plate (120) is a DC + end of a submodule of the matrix transformation;
the second power source (midpoint AC) metalized area (108) is electrically communicated with the fourth power source (midpoint AC) metalized area (112) through a through hole, the second power source (midpoint AC) metalized area (108) is electrically communicated with the third metalized area (113) through a through hole, a seventh metal terminal cover plate (124) is connected with the third metalized area (113), and the seventh metal terminal cover plate (124) corresponds to a midpoint AC end of a submodule of the matrix transformation;
the SiC MOSFET (117) of the lower bridge arm is connected with a fourth gate metalized area (111) and a third power source (midpoint AC) metalized area (110), wherein the fourth gate metalized area (111) is electrically communicated with the first gate metalized area (101) through a through hole, the first gate metalized area (101) is connected with a first metal terminal cover plate (118), and the first metal terminal cover plate (118) corresponds to the gate of the SiC MOSFET of the lower bridge arm; the third power source (midpoint AC) metalized area (110) is electrically communicated with the first Kelvin source metalized area (102) through a through hole, the first Kelvin source metalized area (102) is connected with a second metal terminal cover plate (119), and the second metal terminal cover plate (119) is correspondingly used as a Kelvin source of the lower bridge arm SiC MOSFET;
the SiC Schottky diode (116) of the lower bridge arm is connected with a fourth power source electrode (midpoint AC) metalized area (112), the drain electrode of the SiC MOSFET of the lower bridge arm is connected with the cathode of the SiC Schottky diode of the lower bridge arm through a sixth metal terminal cover plate (123), and the sixth metal terminal cover plate (123) is correspondingly a DC-end of a submodule of the matrix transformation.
2. The highly integrated single ceramic substrate double-sided heat dissipation package structure of claim 1, wherein the SiC MOSFET (115) of the upper leg is connected to the third gate metallization region (107) and the first power source (midpoint AC) metallization region (106) by nano-silver sintering.
3. The highly integrated single ceramic substrate double-sided heat dissipation package structure of claim 1, wherein the SiC schottky diode (114) of the upper leg is connected to the second power source (midpoint AC) metallization region (108) by nano-silver sintering.
4. The highly integrated single ceramic substrate double-sided heat dissipation package structure of claim 1, wherein the seventh metal terminal cover plate (124) and the third metalized region (113) are connected by nano-silver sintering.
5. The highly integrated single ceramic substrate double-sided heat dissipation package structure of claim 1, wherein the SiC MOSFET (117) of the lower leg is connected to the fourth gate metallization region (111) and the third power source (midpoint AC) metallization region (110) by nano-silver sintering.
6. The highly integrated single ceramic substrate double-sided heat dissipation package structure of claim 1, wherein the SiC schottky diode (116) of the lower leg is connected to the fourth power source (midpoint AC) metallization region (112) by nano-silver sintering.
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| US20160268190A1 (en) * | 2015-03-11 | 2016-09-15 | Gan Systems Inc. | PACKAGING SOLUTIONS FOR DEVICES AND SYSTEMS COMPRISING LATERAL GaN POWER TRANSISTORS |
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| US20160268190A1 (en) * | 2015-03-11 | 2016-09-15 | Gan Systems Inc. | PACKAGING SOLUTIONS FOR DEVICES AND SYSTEMS COMPRISING LATERAL GaN POWER TRANSISTORS |
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| CN112864103A (en) * | 2020-12-31 | 2021-05-28 | 西安交通大学 | Cascadable half-bridge high-temperature packaging structure of high-power silicon carbide device |
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