CN114389608A - Analog-digital conversion circuit based on adaptive delta modulation and design method - Google Patents
Analog-digital conversion circuit based on adaptive delta modulation and design method Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0854—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of quantisation noise
Abstract
The invention relates to an analog-digital conversion circuit based on self-adaptive delta modulation and a design method thereof, wherein the circuit comprises: the summing circuit is used for comparing the input analog signal with the feedback signal and calculating the difference to obtain an error signal; a loop filter coupled to the summing circuit for receiving the error signal; a comparator connected to the loop filter, the sum of the output signals of the loop filter being decided by the comparator; the adaptive increment coder receives the judgment result of the comparator, and carries out adaptive increment coding and decoding according to the judgment result to obtain a digital signal corresponding to the input analog signal; the dynamic gain control module is connected with the self-adaptive increment encoder and used for carrying out gain adjustment on the output digital signal; and the digital-to-analog converter is connected with the dynamic gain control module and converts the gain-adjusted digital signal into an analog feedback signal, and the feedback signal is input into the summing circuit. The shaping suppression capability of quantization noise is improved.
Description
Technical Field
The invention relates to the technical field of analog-digital conversion, in particular to an analog-digital conversion circuit based on adaptive delta modulation and a design method thereof.
Background
In the above prior art, since the adaptive incremental encoder is adopted, the quantization value is adaptively adjusted according to the signal characteristic. Since the quantization gain is approximately linearly related to the quantization value in the entire feedback loop, the closed-loop gain of the system fluctuates along with the quantization value when the quantization value is adaptively adjusted.
In order to ensure that the closed loop system can still operate stably when the quantization value fluctuates in a large range, the loop gain needs to be designed conservatively, so that the system can still operate stably at the maximum quantization value. However, in normal operation, the quantization gain is often much smaller than the maximum quantization value, so a large amount of loop gain margin is wasted, and the shaping suppression efficiency of the existing scheme on quantization noise is low.
Documents of the prior art
Patent document
Patent document 1: chinese patent CN104883191B
Patent document 2: chinese patent CN104883190A
Disclosure of Invention
Problems to be solved by the invention
In order to solve the problem that the noise shaping suppression efficiency is too low due to the waste of gain margin caused by the overlarge fluctuation range of quantization noise caused by adaptive delta modulation in the existing scheme, the invention mainly aims to provide an analog-digital conversion circuit based on adaptive delta modulation and a design method thereof.
Means for solving the problems
In order to achieve the above object, the present invention provides an adaptive delta modulation based analog-to-digital conversion circuit, including:
the summing circuit is used for comparing the input analog signal with the feedback signal and calculating the difference to obtain an error signal;
a loop filter coupled to the summing circuit for receiving and filtering the error signal;
a comparator connected to the loop filter, the sum of the output signals of the loop filter being decided by the comparator;
the self-adaptive increment encoder receives the judgment result of the comparator, and performs self-adaptive increment coding and decoding according to the judgment result to obtain a digital signal corresponding to the input analog signal;
the dynamic gain control module is connected with the self-adaptive increment encoder and used for carrying out gain adjustment on the output digital signal; and
and the digital-to-analog converter is connected with the dynamic gain control module and converts the gain-adjusted digital signal into an analog feedback signal, and the feedback signal is input into the summing circuit.
Preferably, the dynamic gain control module comprises a register value characterizing a dynamic delta, wherein the gain of the dynamic gain control module is related to the dynamic delta used in the adaptive delta codec.
Preferably, the dynamic gain control module further comprises a correction gain amount for offsetting the non-linear variation of the quantization gain.
Preferably, the correction gain amount is inversely proportional to the dynamic delta.
Preferably, the dynamic gain control module further comprises a low-pass filter, and the low-pass filter is used for filtering out noise components of high-frequency fluctuation and retaining low-frequency components.
Preferably, the summing circuit includes a first resistor and a second resistor, a first end of the first resistor is connected to the input signal, a second end of the first resistor is connected to the filter circuit, a first end of the second resistor is connected to the digital-to-analog converter, and a second end of the second resistor is connected to a second end of the first resistor and the filter.
Preferably, the loop filter includes a third resistor, a fourth resistor, a first capacitor, a second capacitor, and an operational amplifier, wherein,
the first end of the third resistor is connected with the analog adder and the negative end of the operational amplifier, the second end of the third resistor is connected with the first end of the first capacitor, the second end of the first capacitor is connected with the first end of the second capacitor, the second end of the second capacitor is connected with the output end of the operational amplifier, the first end of the fourth resistor is connected with the second end of the first capacitor and the first end of the second capacitor, and the second end of the fourth resistor is grounded.
In order to achieve the above object, the present invention further provides a method for designing an analog-to-digital conversion circuit based on adaptive delta modulation, comprising the following steps:
a summing circuit is arranged and used for comparing an input analog signal with a feedback signal and calculating the difference to obtain an error signal;
setting a loop filter, connecting the loop filter with the summation circuit, for receiving and filtering the error signal;
setting a comparator, connecting the comparator with the loop filter, and judging the sum of output signals of the loop filter through the comparator;
setting a self-adaptive increment encoder, receiving a judgment result of the comparator, and carrying out self-adaptive increment encoding and decoding according to the judgment result to obtain a digital signal corresponding to an input analog signal;
setting a dynamic gain control module, connecting the dynamic gain control module with the self-adaptive incremental encoder, and performing gain adjustment on the output digital signal; and
and arranging a digital-analog converter, connecting the digital-analog converter with the dynamic gain control module, converting the gain-adjusted digital signal into an analog feedback signal, and inputting the feedback signal into the summing circuit.
The invention also provides an electronic device comprising a circuit and/or a processor, which executes the steps of implementing the above method.
ADVANTAGEOUS EFFECTS OF INVENTION
Compared with the prior art, the invention has the following beneficial effects:
the loop control gain is dynamically adjusted in the control loop according to the current quantization value, so that the nonlinear gain variation of the system caused by different quantization proportions is counteracted, the closed loop working range of the system is further increased, higher stable working closed loop bandwidth can be obtained, and the shaping and inhibiting capability of quantization noise is improved. Thereby effectively improving the signal-to-noise ratio of the modulator or expanding the effective bandwidth of the analog-digital conversion of the system.
Moreover, by using the circuit disclosed by the invention, the noise shaping efficiency of the analog-digital converter adopting the adaptive delta modulation coding and decoding can be effectively improved, the signal-to-noise ratio of the system is improved, and the sampling rate is reduced. Better performance in terms of system area, cost, power consumption, etc. may be achieved.
Drawings
Fig. 1 is a schematic configuration diagram of patent document 1 and patent document 2.
Fig. 2 is a signal flow chart of patent document 1 and patent document 2 corresponding to the schematic diagram of fig. 1.
Fig. 3 is a diagram illustrating the output equivalent gain of a specific quantizer in a prior art scheme.
Fig. 4A is a schematic block diagram of an adaptive delta modulation based analog-to-digital conversion circuit according to the present invention.
Fig. 4B is a schematic structural diagram of an analog-to-digital conversion circuit based on adaptive delta modulation according to the present invention.
Fig. 5 is a signal flow diagram corresponding to the schematic block diagram of fig. 4A according to the present invention.
Fig. 6 is a block diagram of an embodiment of an adaptive delta modulation based analog-to-digital conversion circuit according to the present invention.
Fig. 7 is a flow chart of a design method of an analog-digital conversion circuit based on adaptive delta modulation according to the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention. It should be further emphasized here that the following embodiments provide preferred embodiments, and that the various aspects (embodiments) may be used in combination or cooperation with each other.
As shown in fig. 1 and 2, a schematic block diagram and a corresponding signal flow diagram of the technical solutions disclosed in prior art patent document 1 and patent document 2 are shown.
In the prior art, an input analog signal is compared with a feedback signal and an error signal is obtained by subtracting the input analog signal from the feedback signal, where the feedback signal is an analog output of an output digital signal after passing through a digital-to-analog converter, and the error signal is judged by a comparator after passing through a loop filter. And performing adaptive incremental coding and decoding according to the judgment result to obtain a digital signal corresponding to the input analog signal, thereby completing the analog-to-digital conversion of the input signal.
The equivalent signal flow diagram in this scheme is that the input signal X is compared with the output through a summing circuit and fed to a loop filter with a transfer function h(s), and both the comparator and the adaptive delta encoder can be equivalent to a quantization error added on the basis of the input signal, namely a quantization error Eq and a coding error Ec, respectively. Wherein the quantization gain can be equivalent to a gain block with a gain Qg, and in this scheme, the output signal Y is given by the following formula:
the equivalent signal flow diagram in this scheme is that the input signal X is compared with the output through a summing circuit and fed to a loop filter with a transfer function h(s), and both the comparator and the adaptive delta encoder can be equivalent to a quantization error added on the basis of the input signal, namely a quantization error Eq and a coding error Ec, respectively. Wherein the quantization gain can be equivalent to a gain block with a gain Qg, and in this scheme, the output signal Y is given by the following formula:
by shaping the quantization noise, the signal-to-noise ratio of the system within the signal bandwidth is improved. However, the equivalent quantization gain Qg of the comparator is strongly nonlinear, and due to the adoption of the adaptive increment coding, the equivalent quantization gain can change with different sizes of specific adaptive increment values. Therefore, to ensure the stability of the closed loop system, it is necessary to ensure that the Qg has enough margin at the maximum equivalent gain. When the circuit normally works, Qg is often much smaller than the maximum equivalent gain, so that the overall loop gain is limited, and the efficiency of noise shaping is not high.
Fig. 3 is a schematic diagram showing the output equivalent gain of a specific quantizer in the conventional scheme. Because the comparator compares the input signal and quantizes it to +1 or-1, in the adaptive delta codec modulator, the output of the comparator, which is +1 or-1, corresponds to a specific adaptive delta + Qo or-Qo, as the case may be.
If the input signal amplitude is small, the quantization gain V (Qo)/V (input) is large, i.e., different input amplitudes correspond to different quantization gains. If we assume that the input signal is white noise distributed randomly, we can get the macroscopically equivalent quantization gain Qg ═ E (| in |)/E (in ^2) × Qo. Where E (| in |) is the expectation of the absolute value of the input signal, E (in ^2) is the second moment of the input signal, which can be generally assumed to be the variance of the input signal. Qo is the equivalent output value of the quantized signal in the adaptive quantizer.
As can be seen from the above Qg formula, due to the existence of the adaptive incremental codec, the equivalent Qo varies within a large range, and in a typical design example, the difference between the maximum value and the minimum value of Qo is several tens to several hundreds of times, and in an extreme case, even thousands of times.
Fig. 4A, 4B and 5 are schematic diagrams of a schematic structure, a schematic structure and a signal flow of an adaptive delta modulation based analog-to-digital conversion circuit according to the present invention.
An analog-digital conversion circuit 1 based on adaptive delta modulation of the present invention includes: a summing circuit 11, a loop filter 12, a comparator 13, an adaptive delta encoder 14, a dynamic gain control module 15, and a digital-to-analog converter (ADC)16, wherein,
the summing circuit 11 may be an analog adder, the analog adder 11 is configured to compare and subtract an input analog signal with a feedback signal to obtain an error signal, where the feedback signal is an analog output obtained by performing gain adjustment on an output digital signal through a dynamic gain control module 15 and then through a digital-to-analog converter 16, the error signal passes through a loop filter 12 and then is determined by a comparator 13, and after a determination result is input to an adaptive incremental encoder 14, the adaptive incremental encoder 14 performs adaptive incremental encoding and decoding according to the determination result of the comparator to obtain a digital signal corresponding to the input analog signal, thereby completing analog-to-digital conversion of the input signal.
The equivalent signal flow diagram in this scheme is that the input signal X is compared with the output by the summing circuit 11 and fed to the loop filter 12 with a transfer function h(s), and the comparator 11 and the adaptive incremental encoder 13 are equivalent to a quantization error added on the basis of the input signal, which is the quantization error Eq and the encoding error Ec, respectively. In this scheme, the output signal Y is given by the following equation:
compared to the prior art solutions, it can be seen that the signal transfer function ST isF(s), i.e. coefficient of X
The influence of the quantization gain is effectively removed. Meanwhile, the coding error Ec is reduced by Qg times compared with the existing scheme, and in the adaptive incremental coding and decoding, Ec is just proportional to Qn, namely proportional to Qg. On the other hand, in a closed loop system of the loop, the influence of the Qg disappears, so that the strong nonlinear influence caused by the adaptive quantization is eliminated.
In addition, because the loop gain of the system is irrelevant to Qg, the design space is larger in the stability of the loop, and dozens of times or even hundreds of times of loop gain margin does not need to be reserved, so that the noise shaping can be effectively carried out through loop suppression, and the overall performance of the system is remarkably improved.
Fig. 6 is a block diagram of an embodiment of an analog-to-digital conversion circuit based on adaptive delta modulation according to the present invention.
The input signal is connected to the negative input terminal of the operational amplifier OP1 through a resistor Ri, the digital-to-analog converter DAC converts the output digital signal into an analog signal, and the analog signal is inverted and then added to the input terminal through Rfb, so that the input signal of the operational amplifier is the input and feedback error.
That is, the analog adder 11 includes a first resistor Ri and a second resistor Rfb, the first terminal of the first resistor Ri is connected to the input signal, the second terminal of the first resistor Ri is connected to the loop filter 12, the first terminal of the second resistor Rfb is connected to the digital-to-analog converter 16, the second terminal of the second resistor Rfb is connected to the second terminal of the first resistor Ri, and the first terminal and the second terminal of the second resistor Rfb are commonly connected to the loop filter 12.
The loop filter 12 includes a third resistor Rf, a fourth resistor Rz, a first capacitor C1, a second capacitor C2, and an operational amplifier OP1, wherein the input signal is connected to the negative input terminal of the operational amplifier OP1 through a resistor Ri, the digital-to-analog converter 16 converts the output digital signal into an analog signal, and adds the analog signal to the input terminal through a second resistor Rfb after inverting, so that the input signal of the operational amplifier OP1 is the input and feedback error.
The third resistor Rf, the fourth resistor Rz, the first capacitor C1, and the second capacitor C2 form a feedback filter network, and the feedback filter network is specifically connected as follows: a first end of the third resistor Rf is connected to the analog adder and the negative end of the operational amplifier OP1, a second end of the third resistor Rf is connected to the first end of the first capacitor C1, a second end of the first capacitor C1 is connected to the first end of the second capacitor C2, a second end of the second capacitor C2 is connected to the output end of the operational amplifier OP1, a first end of the fourth resistor Rz is connected to the second end of the first capacitor C1 and the first end of the second capacitor C2, and a second end of the fourth resistor Rz is grounded.
A feedback filter network is formed by the above, thereby realizing a loop filter with a transfer function H(s) of two pairs of zero poles. Transfer function of the circuit
Wherein, C1// C2 ═ C1 ═ C2/(C1+ C2).
After the output of the loop filter 12 is compared and sampled by the comparator 13, the output of the comparator 13 passes through the adaptive incremental coding and decoding module 14, and then passes through the dynamic gain control module 15, so as to obtain a digital signal corresponding to the INPUT signal INPUT.
Wherein the gain of the dynamic gain control module 15 is related to 1/Qn, i.e. inversely proportional to Qn. Qn is the dynamic delta used in the adaptive delta codec 14. Because the adaptive incremental encoder 14 will dynamically adjust the signal amplitude Qn corresponding to the input 1 or-1 according to the input signal, a 1/Qn dynamic gain control module 15 is added, so that the gain stability of the whole loop is independent of Qn, thereby largely eliminating the nonlinearity of the loop and increasing the stability margin of the system.
Specifically, in the dynamic gain control module 15, the quantization order is dynamically adjusted according to the current signal characteristic, so that a register value Qn exists in the dynamic gain control module 15, and the register value Qn represents a dynamic quantization value. When the system works stably, the input of the quantizer is the fluctuation of a small signal, and can be equivalent to randomly distributed noise, and under the assumption of white noise, the equivalent quantization gain of the quantizer is in direct proportion to Qn.
Therefore, after the dynamic gain control module 15 completes the adaptive delta modulation of the signal, a correction gain amount 1/Qn inversely proportional to the current quantization gain Qn can be provided according to the current quantization gain Qn, so as to counteract the nonlinear change of the quantization gain, thereby keeping the loop gain stable.
In the specific implementation, because Qn is dynamically fluctuated, Qn is different in each clock sampling period and has larger fluctuation, Qn passes through a low-pass filter to filter the noise component of high-frequency fluctuation, and the low-frequency component of Qn is retained, so that the stability of loop gain can be effectively improved.
After the dynamic gain control module 15 is introduced into the system, the dependence of the loop gain on Qn is greatly reduced. Thus, the loop gain remains substantially constant under various operating conditions. Therefore, the loop gain is almost consistent with the loop gain of the maximum signal in normal operation, and the whole loop bandwidth can be kept at a larger value. Therefore, the method can be in a better quantization noise shaping and suppression state under various working conditions. Compared with the prior scheme, the signal-to-noise ratio of the system is obviously improved.
Fig. 7 is a flow chart of a method for designing an analog-to-digital conversion circuit based on adaptive delta modulation according to the present invention. The design method of the analog-digital conversion circuit comprises the following steps:
step S1: a summing circuit is arranged and used for comparing an input analog signal with a feedback signal and calculating the difference to obtain an error signal;
step S2: setting a loop filter, connecting the loop filter with the summation circuit, for receiving and filtering the error signal;
step S3: setting a comparator, connecting the comparator with the loop filter, and judging the sum of output signals of the loop filter through the comparator;
step S4: setting a self-adaptive increment encoder, receiving a judgment result of the comparator, and carrying out self-adaptive increment encoding and decoding according to the judgment result to obtain a digital signal corresponding to an input analog signal;
step S5: setting a dynamic gain control module, connecting the dynamic gain control module with the self-adaptive incremental encoder, and performing gain adjustment on the output digital signal; and
step S6: and arranging a digital-analog converter, connecting the digital-analog converter with the dynamic gain control module, converting the gain-adjusted digital signal into an analog feedback signal, and inputting the feedback signal into the summing circuit.
In summary, the adc of the present invention includes an adaptive delta modulation and employs an oversampling adc employing a noise shaping technique.
The invention dynamically adjusts the closed-loop gain according to the quantization coefficient, reduces the nonlinear degree of a feedback system, increases the stable working bandwidth of the closed-loop system, and improves the shaping and inhibiting capability of quantization noise. And the loop gain is dynamically adjusted, so that the loop gain is kept stable in a large range, loop nonlinear characteristics caused by self-adaptive delta modulation are eliminated, the loop gain under the normal working condition is improved, and the quantization noise shaping inhibition efficiency is improved. By using the method disclosed by the invention, the noise shaping efficiency of the analog-digital converter adopting the adaptive delta modulation coding and decoding can be effectively improved, the signal-to-noise ratio of the system is improved, and the sampling rate is reduced. Better performance in terms of system area, cost, power consumption, etc. may be achieved.
While the present application is described in terms of various aspects, including exemplary embodiments, the principles of the invention should not be limited to the disclosed embodiments, but are also intended to cover various modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. An adaptive delta modulation based analog-to-digital conversion circuit, comprising:
the summing circuit is used for comparing the input analog signal with the feedback signal and calculating the difference to obtain an error signal;
a loop filter coupled to the summing circuit for receiving and filtering the error signal;
a comparator connected to the loop filter, the sum of the output signals of the loop filter being decided by the comparator;
the self-adaptive increment encoder receives the judgment result of the comparator, and performs self-adaptive increment coding and decoding according to the judgment result to obtain a digital signal corresponding to the input analog signal;
the dynamic gain control module is connected with the self-adaptive increment encoder and used for carrying out gain adjustment on the output digital signal; and
and the digital-to-analog converter is connected with the dynamic gain control module and converts the gain-adjusted digital signal into an analog feedback signal, and the feedback signal is input into the summing circuit.
2. The adaptive delta modulation based analog-to-digital conversion circuit of claim 1,
the dynamic gain control module includes a register value characterizing a dynamic delta, wherein a gain of the dynamic gain control module is related to a dynamic delta used in the adaptive delta codec.
3. The adaptive delta modulation based analog-to-digital conversion circuit of claim 2,
the dynamic gain control module further includes a correction gain amount for canceling out non-linear changes in the quantization gain.
4. The adaptive delta modulation based analog-to-digital conversion circuit of claim 3,
the amount of correction gain is inversely proportional to the dynamic delta.
5. The adaptive delta modulation based analog-to-digital conversion circuit of claim 2,
the dynamic gain control module further comprises a low-pass filter, wherein the low-pass filter is used for filtering noise components of high-frequency fluctuation and keeping low-frequency components.
6. The adaptive delta modulation based analog-to-digital conversion circuit of claim 1,
the summing circuit comprises a first resistor and a second resistor, wherein the first end of the first resistor is connected with an input signal, the second end of the first resistor is connected with the filter circuit, the first end of the second resistor is connected with the digital-to-analog converter, and the second end of the second resistor is connected with the second end of the first resistor and the filter.
7. The adaptive delta modulation based analog-to-digital conversion circuit of claim 1,
the loop filter comprises a third resistor, a fourth resistor, a first capacitor, a second capacitor and an operational amplifier, wherein,
the first end of the third resistor is connected with the analog adder and the negative end of the operational amplifier, the second end of the third resistor is connected with the first end of the first capacitor, the second end of the first capacitor is connected with the first end of the second capacitor, the second end of the second capacitor is connected with the output end of the operational amplifier, the first end of the fourth resistor is connected with the second end of the first capacitor and the first end of the second capacitor, and the second end of the fourth resistor is grounded.
8. A design method of an analog-digital conversion circuit based on adaptive delta modulation is characterized by comprising the following steps:
a summing circuit is arranged and used for comparing an input analog signal with a feedback signal and calculating the difference to obtain an error signal;
setting a loop filter, connecting the loop filter with the summation circuit, for receiving and filtering the error signal;
setting a comparator, connecting the comparator with the loop filter, and judging the sum of output signals of the loop filter through the comparator;
setting a self-adaptive increment encoder, receiving a judgment result of the comparator, and carrying out self-adaptive increment encoding and decoding according to the judgment result to obtain a digital signal corresponding to an input analog signal;
setting a dynamic gain control module, connecting the dynamic gain control module with the self-adaptive incremental encoder, and performing gain adjustment on the output digital signal; and
and arranging a digital-analog converter, connecting the digital-analog converter with the dynamic gain control module, converting the gain-adjusted digital signal into an analog feedback signal, and inputting the feedback signal into the summing circuit.
9. An electronic device comprising circuitry and/or a processor, wherein the circuitry and/or the processor performs the steps of implementing the method of claim 8.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101540608A (en) * | 2008-03-20 | 2009-09-23 | 扬智科技股份有限公司 | Device and method for reducing quantization noise in mute |
| CN104883190A (en) * | 2014-02-28 | 2015-09-02 | 北京卓锐微技术有限公司 | High precision ADC with adaptive delta modulation |
| CN106551695A (en) * | 2015-09-24 | 2017-04-05 | 李福霞 | A kind of electrocardiosignal modulate circuit |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101540608A (en) * | 2008-03-20 | 2009-09-23 | 扬智科技股份有限公司 | Device and method for reducing quantization noise in mute |
| CN104883190A (en) * | 2014-02-28 | 2015-09-02 | 北京卓锐微技术有限公司 | High precision ADC with adaptive delta modulation |
| CN106551695A (en) * | 2015-09-24 | 2017-04-05 | 李福霞 | A kind of electrocardiosignal modulate circuit |
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