CN114640353A - Single-bit sigma delta DAC circuit - Google Patents
Single-bit sigma delta DAC circuit Download PDFInfo
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- CN114640353A CN114640353A CN202210398506.7A CN202210398506A CN114640353A CN 114640353 A CN114640353 A CN 114640353A CN 202210398506 A CN202210398506 A CN 202210398506A CN 114640353 A CN114640353 A CN 114640353A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/50—Digital/analogue converters using delta-sigma modulation as an intermediate step
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Abstract
The invention discloses a single-bit sigma delta DAC circuit. The high-order single-bit sigma delta modulator comprises an up-sampling filter, a high-order single-bit sigma delta modulator, a 1-bit DAC circuit and a threshold generation module, wherein the high-order single-bit sigma delta modulator comprises a noise shaping filter and a quantizer. The threshold generation module comprises a unit time signal high-low level conversion frequency statistic device, a maximum threshold limiting device and a threshold adjusting device. The high and low level conversion times counting device counts the high and low level conversion times of the quantizer output signals in unit time; a maximum threshold limiting device determines a maximum threshold based on the input signal amplitude; the threshold adjusting device receives the high-low level conversion times and the maximum threshold of the output signal of the quantizer, combines the built-in set times, and inputs the current threshold into the quantizer. The invention saves the circuit cost, avoids the introduced nonlinear error, and reduces the cost and the realization difficulty of the 1-bit DAC.
Description
Technical Field
The invention belongs to the technical field of signal processing, particularly relates to the technical field of digital-to-analog conversion circuits (DAC), and relates to a high-performance single-bit sigma delta DAC circuit with bit width modulation.
Background
A DAC converts a digital signal into an analog signal, which is a commonly used functional block in modern digital signal processing. The Sigma delta DAC is a DAC technology based on oversampling and noise shaping, and is widely applied to the field of low-speed and high-precision DACs. Sigma delta DACs are divided into single bit quantization and multi-bit quantization. Because the single-bit quantization has natural high linearity, the requirement of element matching precision is avoided, and the method becomes an important field.
The existing single-bit sigma delta DAC uses a high-order single-bit sigma delta modulator to generate 1-bit data stream, and a 1-bit DAC is connected at the rear end. To achieve the same DAC performance, a single-bit sigma delta DAC requires the use of greater oversampling than a multi-bit sigma delta DAC, thus increasing the frequency requirement for a 1-bit DAC. A multi-bit sigma delta modulator is used in series with a PWM generator to reduce the frequency requirement for a 1-bit DAC, as disclosed in US20050007266a 1. But this adds a PWM generator, which increases the cost of the circuit, while the PWM generator introduces signal errors.
Disclosure of Invention
The invention aims to provide a high-performance single-bit sigma delta DAC circuit for reducing the signal switching frequency of a 1-bit DAC, aiming at the defect that the frequency requirement of the high-performance single-bit sigma delta DAC on the 1-bit DAC is too high.
The invention comprises an UP-sampling filter UP, a high-order single-bit sigma delta modulator SDM capable of adjusting a threshold, a 1-bit DAC circuit and a threshold generation module T. The higher order single bit sigma delta modulator SDM comprises a noise shaping filter F and an adjustable threshold quantizer Q. The quantizer Q compares the output of the noise shaping filter F with a threshold value: if the output value of the noise shaping filter F is larger than the positive threshold value, the output value of the quantizer Q is 1; if the output value of the noise shaping filter F is less than the negative threshold, the output value of the quantizer Q is-1; if the output value of the noise shaping filter F is equal to or less than the positive threshold and equal to or more than the negative threshold, the output value of the quantizer Q is the output value of the last clock.
The signal input end of the sampling filter UP receives an external digital signal, the signal output end is connected with the signal input end of the noise shaping filter F, and the signal output end of the noise shaping filter F is connected with the signal input end of the quantizer Q.
The threshold generation module T comprises a unit time signal high-low level conversion frequency counting device, a maximum threshold limiting device and a threshold adjusting device. Wherein:
the input end of the unit time signal high-low level conversion frequency counting device is connected with the signal output end of the quantizer Q, and the unit time output signal high-low level conversion frequency of the quantizer Q is counted, namely the conversion frequency of the output value 1 and-1 of the quantizer Q: when the detection starts, the conversion times are 0; if the output of the quantizer Q of the current clock is different from the output of the quantizer Q of the previous clock, adding 1 to the conversion times; if the conversion times are the same, the conversion times are unchanged; the total conversion times after the unit time is the conversion times of the high and low levels of the output signal of the quantizer Q in the unit time; the output end of the unit time signal high-low level conversion frequency counting device is connected with the high-low level conversion frequency input end of the threshold adjusting device, and the unit time quantizer output signal high-low level conversion frequency is sent to the threshold adjusting device.
The input end of the maximum threshold limiting device is connected with the signal input end of the sampling filter UP, and receives the input signal of the circuit; a lookup table is arranged in the maximum threshold limiting device, and the lookup table sets maximum thresholds corresponding to different amplitude values; the maximum threshold limiting device determines a maximum threshold according to the amplitude of the input signal of each clock circuit; the output end of the maximum threshold limiting device is connected with the maximum threshold input end of the threshold adjusting device, and the maximum threshold information is sent to the threshold adjusting device.
The threshold adjusting device is internally provided with set times, receives the high-low level conversion times of the quantizer output signal in unit time and maximum threshold information: if the conversion times in the received unit time are more than or equal to the set times and the current threshold is less than the maximum threshold, the threshold adjusting device adds 1 unit to the current threshold, and if the current threshold is equal to the maximum threshold, the current threshold is kept unchanged; if the conversion times in unit time are less than the set times and the current threshold is greater than 0, the threshold adjusting device subtracts 1 unit from the current threshold, if the current threshold is equal to 0, the current threshold is kept unchanged, the initial threshold is 0, the threshold is a positive threshold, and the negative threshold is a negative threshold; the threshold output end of the threshold adjusting device is connected with the threshold input end of the quantizer Q, and the current threshold is input into the quantizer Q.
And the signal output end of the quantizer Q and the feedback input end of the noise shaping filter F are connected and then connected with the signal input end of the 1-bit DAC circuit, and the signal output end of the 1-bit DAC circuit is used as the output end of the whole circuit to output an analog signal.
Up-sampling wave filters are a well established prior art that converts low sample rate signals to high sample rate signals.
1-bit DAC circuits are mature prior art and convert digital signals to analog low and high levels.
The high-order single-bit sigma delta modulator is a mature prior art and moves the quantization noise of a low frequency band to a high frequency.
Compared with the prior art that the sigma delta modulator and the PWM generator generate 1-bit signals, the method does not need to use the PWM generator, saves the circuit cost and avoids the nonlinear error introduced by the PWM generator. Compared with the original sigma delta modulator, the invention dynamically adjusts the threshold value of the quantizer according to the output conversion times of the quantizer in unit time, and reduces the conversion times of the input signal of the 1-bit DAC in unit time, thereby reducing the requirement on the working frequency of the 1-bit DAC, reducing the physical realization requirement on the 1-bit DAC, and reducing the cost and the realization difficulty of the 1-bit DAC. The dynamic range of the DAC of the signal is reduced due to the increased quantizer threshold. The invention protects the maximum threshold of the quantizer, and avoids the defect that the dynamic range of the DAC is reduced after the quantizer introduces dynamic threshold adjustment.
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FIG. 1 is a schematic view of the structure of the present invention.
Detailed Description
The present invention will be further described with reference to the following examples. The following examples are only specific examples of the present invention, but the design concept of the present invention is not limited thereto, and any insubstantial modifications of the present invention using the design concept shall fall within the scope of the present invention.
As shown in fig. 1, a single-bit sigma delta DAC circuit includes an UP-sampling filter UP, a high-order single-bit sigma delta modulator SDM capable of adjusting a threshold, a 1-bit DAC circuit, and a threshold generation module T. The high order single bit sigma delta modulator SDM comprises a noise shaping filter F and an adjustable threshold quantizer Q. The signal input end 1 of the sampling filter UP receives an external digital signal, the signal output end 2 is connected with the signal input end 3 of the noise shaping filter F, and the signal output end 4 of the noise shaping filter F is connected with the signal input end 5 of the quantizer Q.
The UP-sampling filter UP converts the signal of low sampling rate into a signal of high sampling rate. The 1-bit DAC circuit converts the digital signal into analog low and high levels. The high-order single-bit sigma delta modulator SDM shifts the quantization noise of a low frequency band to a high frequency. Wherein the quantizer Q compares the output value of the noise shaping filter F with a threshold value: if the output value of the noise shaping filter F is larger than the positive threshold value, the output value of the quantizer Q is 1; if the output value of the noise shaping filter F is less than the negative threshold, the output value of the quantizer Q is-1; if the output value of the noise shaping filter F is equal to or less than the positive threshold and equal to or more than the negative threshold, the output value of the quantizer Q is the output value of the last clock.
The threshold generation module T comprises a unit time signal high-low level switching frequency counting device A, a maximum threshold limiting device B and a threshold adjusting device C. Wherein:
the input end 6 of the unit time signal high-low level conversion frequency counting device a is connected with the signal output end 7 of the quantizer Q, and counts the unit time output signal high-low level conversion frequency of the quantizer Q, namely the conversion frequency of the output value 1 and-1 of the quantizer Q: when the detection starts, the conversion times are 0; if the output of the quantizer Q of the current clock is different from the output of the quantizer Q of the previous clock, adding 1 to the conversion times; if the conversion times are the same, the conversion times are unchanged; the total conversion times after the unit time is the conversion times of the high and low levels of the output signal of the quantizer Q in the unit time; the output end 8 of the unit time signal high-low level conversion frequency counting device A is connected with the high-low level conversion frequency input end 9 of the threshold adjusting device C, and the unit time quantizer output signal high-low level conversion frequency is sent to the threshold adjusting device C.
The input end 10 of the maximum threshold limiting device B is connected with the signal input end 1 of the sampling filter UP and receives the input signal of the circuit; a lookup table is arranged in the maximum threshold limiting device B, and the lookup table sets maximum thresholds corresponding to different amplitude values; the maximum threshold limiting device B determines a maximum threshold according to the amplitude of the input signal of each clock circuit; the output end 11 of the maximum threshold limiting device B is connected with the maximum threshold input end 12 of the threshold adjusting device C, and the maximum threshold information is sent to the threshold adjusting device C.
The threshold adjusting device C is internally provided with set times, receives the high-low level conversion times of the quantizer output signal in unit time and maximum threshold information: if the conversion times in the received unit time are more than or equal to the set times and the current threshold is less than the maximum threshold, the threshold adjusting device adds 1 unit to the current threshold, and if the current threshold is equal to the maximum threshold, the current threshold is kept unchanged; if the conversion times in unit time are less than the set times and the current threshold is greater than 0, the threshold adjusting device subtracts 1 unit from the current threshold, if the current threshold is equal to 0, the current threshold is kept unchanged, the initial threshold is 0, the threshold is a positive threshold, and the negative threshold is a negative threshold; the threshold output terminal 13 of the threshold adjusting device is connected to the threshold input terminal 14 of the quantizer Q, and the current threshold is input to the quantizer Q.
The signal output terminal 7 of the quantizer Q and the feedback input terminal 15 of the noise shaping filter F are connected and then connected to the signal input terminal 16 of the 1-bit DAC circuit, and the signal output terminal 17 of the 1-bit DAC circuit serves as the output terminal of the entire circuit, and outputs an analog signal.
In this embodiment, the input signal is a digital signal with a sampling rate of 48KHz, the sigma delta modulator SDM operates at 12.288MHz, and the oversampling rate is 256 times. The threshold generation module T calculates the unit time of the quantizer output to be 1 mS. Without this circuit, the threshold of the quantizer is 0 and the 1-bit DAC toggles a maximum of 12288 times within 1 mS.
The number of times is 768, which means that the maximum number of times of inversion is 768 times within 1 mS.
Assuming that the initial threshold of the threshold generation module is 0; the threshold generation module has a unit of threshold variation of 1/1024. The number of changes in the quantizer output within 1mS is much higher than the set number 768. The threshold of the threshold generation module rises rapidly to rapidly reduce the number of changes in the quantizer output over a period of 1 mS. When the change times of the quantizer output within 1mS is smaller than 768, the threshold value of the threshold value generation module is reduced, so that the change times of the quantizer output within 1mS are improved. Finally, the threshold of the threshold generation module keeps fluctuating within a small range, so that the change times within 1mS output by the quantizer are stabilized at about 768 times, and are reduced by 16 times compared with the original 12288 times, the frequency requirement of the 1-bit DAC is greatly reduced, and the requirement on the physical implementation of the 1-bit DAC is reduced. The built-in lookup table of the maximum threshold limiting device B is output 1/16 when the amplitude of the input signal is greater than 0.5 or less than-0.5; when the input signal amplitude is 0.5 or less and 0.5 or more, the look-up table outputs 1/8. An excessive quantizer threshold reduces the dynamic range of the DAC. Since the number of changes in the quantizer output over a period of 1mS is inversely proportional to the absolute value of the input signal amplitude, using a smaller maximum threshold limit does not reduce the dynamic range of the DAC of the signal when the input signal amplitude is larger.
It is to be understood that the above examples are illustrative of the present invention and are not to be construed as limiting the invention, and any invention which does not depart from the spirit and scope of the invention is deemed to be within the scope and spirit of the invention.
Claims (2)
1. The single-bit sigma delta DAC circuit comprises an UP-sampling filter UP, a high-order single-bit sigma delta modulator SDM with an adjustable threshold value and a 1-bit DAC circuit, wherein the high-order single-bit sigma delta modulator SDM comprises a noise shaping filter F and a quantizer Q with an adjustable threshold value; the signal input end of the sampling filter UP is used as the input end of the whole circuit to receive external digital signals, the signal output end of the sampling filter UP is connected with the signal input end of the noise shaping filter F, and the signal output end of the noise shaping filter F is connected with the signal input end of the quantizer Q; the method is characterized in that: the device also comprises a threshold generating module T;
the threshold generation module T comprises a unit time signal high-low level conversion frequency counting device, a maximum threshold limiting device and a threshold adjusting device; wherein:
the input end of the unit time signal high-low level conversion frequency counting device is connected with the signal output end of the quantizer Q, and the unit time signal high-low level conversion frequency of the output signal of the quantizer Q is counted: the number of switching times at the start of detection is 0; if the output of the quantizer Q of the current clock is different from the output of the quantizer Q of the previous clock, adding 1 to the conversion times; if the conversion times are the same, the conversion times are unchanged; the total conversion times after the unit time is the conversion times of the high and low levels of the output signal of the quantizer Q in the unit time; the output end of the unit time signal high-low level conversion frequency counting device is connected with the high-low level conversion frequency input end of the threshold value adjusting device, and the unit time quantizer output signal high-low level conversion frequency is sent to the threshold value adjusting device;
the input end of the maximum threshold limiting device is connected with the signal input end of the sampling filter UP, and receives the input signal of the circuit; a lookup table is arranged in the maximum threshold limiting device, and the lookup table sets maximum thresholds corresponding to different amplitude values; the maximum threshold limiting device determines a maximum threshold according to the amplitude of the input signal of each clock circuit; the output end of the maximum threshold limiting device is connected with the maximum threshold input end of the threshold adjusting device, and the maximum threshold information is sent to the threshold adjusting device;
the threshold adjusting device is internally provided with set times, receives the high-low level conversion times of the quantizer output signal in unit time and maximum threshold information: if the conversion times in the received unit time are more than or equal to the set times and the current threshold is less than the maximum threshold, the threshold adjusting device adds 1 unit to the current threshold, and if the current threshold is equal to the maximum threshold, the current threshold is kept unchanged; if the conversion times in unit time are less than the set times and the current threshold is greater than 0, the threshold adjusting device subtracts 1 unit from the current threshold, if the current threshold is equal to 0, the current threshold is kept unchanged, the initial threshold is 0, the threshold is a positive threshold, and the negative threshold is a negative threshold; the threshold output end of the threshold adjusting device is connected with the threshold input end of the quantizer Q, and the current threshold is input into the quantizer Q;
and the signal output end of the quantizer Q and the feedback input end of the noise shaping filter F are connected and then connected with the signal input end of the 1-bit DAC circuit, and the signal output end of the 1-bit DAC circuit is used as the output end of the whole circuit to output an analog signal.
2. The single-bit sigma delta DAC circuit of claim 1, wherein: the quantizer Q compares the output of the noise shaping filter F with a threshold value: if the output value of the noise shaping filter F is greater than the positive threshold value, the output value of the quantizer Q is 1; if the output value of the noise shaping filter F is less than the negative threshold, the output value of the quantizer Q is-1; if the output value of the noise shaping filter F is equal to or less than the positive threshold and equal to or more than the negative threshold, the output value of the quantizer Q is the output value of the last clock.
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