WO2010046853A2

WO2010046853A2 - Sigma-delta modulator

Info

Publication number: WO2010046853A2
Application number: PCT/IB2009/054632
Authority: WO
Inventors: Lucien Johannes Breems; Robert Henrikus Margaretha Van Veldhoven; Robert Rutten
Original assignee: Nxp B.V.
Priority date: 2008-10-23
Filing date: 2009-10-21
Publication date: 2010-04-29
Also published as: WO2010046853A3

Abstract

A cascaded sigma-delta analog to digital converter (300) comprising a first sigma-delta modulator (310) having an input configured to receive an input signal, a second sigma-delta modulator (320) configured to receive an error signal from the first modulator and a noise filter (230) configured to receive an output signal from each of the first and second modulators and to provide a modulated and filtered output signal, wherein the analog to digital converter comprises an adder (216) configured to provide the error signal from the first modulator by combining an output signal from a loop filter (212) of the first modulator with the input signal.

Description

SIGMA-DELTA MODULATOR

FIELD OF THE INVENTION

The invention relates to sigma-delta (ΣΔ) modulators, and in particular to aspects of noise shaping in ΣΔ modulators.

BACKGROUND OF THE INVENTION

Sigma-delta modulators (also known as delta-sigma modulators) are well-known in certain types of analog to digital (ADC) architectures. A ΣΔ modulator exploits the effects of oversampling to shape quantization errors spectrally, allowing these errors to be effectively moved to higher frequencies where they can be more easily filtered out. An example of a ΣΔ modulator is illustrated in schematic block diagram form in Figure 1 . The modulator 100 comprises an adder 101 , a loop filter H 102, a quantizer or analog/digital converter Q 103 , and a feedback path 104 having a digital/analog converter 105. Both the quantizer 103 and the feedback loop DAC 105 operate at a sampling frequency f_s supplied by a clock signal. An input signal X(s) is converted to an output signal Y(z). The feedback path 104 allows the quantized signal Y(z) to be compared with the input signal X(s), resulting in an output signal that comprises a quantized signal overlaid with a quantisation error, which may alternatively be described as quantization noise. Such types of modulators are described in more detail by Norsworthy et al ., in 'Delta-Sigma Data Converters; Theory, Design, and Simulation', IEEE press, 1997.

Figure 1 b shows the modulator of figure 1 a with the components represented in transfer function form. The quantizer 103 is modelled by a summing node 103a where quantization noise Q is introduced . The transfer function for the modulator is then given by:

H

Y = X- -+ Q- l + H l + H Depending on the implementation of the loop filter 1 02, the quantization noise can be suppressed in a specified part of the output spectrum of Y(z). The more bits are chosen for the quantizer 103 and the feedback path 104, the lower the quantization noise in the output signal Y(z) will tend to be, because the quantization errors made will be smaller.

A ΣΔ modulator 100 can be implemented in several ways. One implementation is a fully digital ΣΔ modulator, where the input signal X is a digital signal, which is to be transformed into an output signal Y having a reduced number of bits. To do this involves rounding of the input signal by the quantizer 103, which introduces a quantization error. This error can be controlled using feedback, resulting in the output signal Y being a controlled copy of X, with a gain applied by the loop filter H.

Another implementation is a ΣΔ analog to digital converter, in which the input signal X(s) is a time-continuous analog signal, to be converted into a discrete signal Y(z) in the digital domain. This can be implemented in several ways. The loop filter 102 can be implemented with switched capacitors or continuous time filters, both of which have associated advantages and disadvantages. The quantizer 103 digitises the signal from the loop filter 102. The output signal Y(z) is fed back through a digital to analog converter 104, which converts the digital signal into an analog representation, which is then compared to the analog input signal X(s) by the adder/comparator 101. An advantage of this type of ADC is that of the noise shaping behaviour of the loop filter 102.

Several architectures are known to improve the noise-shaping characteristic of ΣΔ modulators. One of those is a multi-stage noise- shaping ADC, also known as a MASH or cascaded ΣΔ ADC, for example as disclosed by Breems, et al ., in "A Cascaded Continuous-Time ΣΔ Modulator with 67 Dynamic Range in 10MHz Bandwidth", IEEE Journal of Solid-State Circuits, Vol. 39, pp. 2152-2160, Dec. 2004. An example of such a MASH ADC 200 is illustrated in figure 2. The converter 200 consists of multiple ΣΔ modulator stages, each having an adder 211 , 221 , a loop filter 212, 222, a quantizer 213, 223 and a feedback loop having a digital to analog converter 214, 224 as in the modulator of figure 1. In the example shown in figure 2 the ADC has two stages. The first stage 210 converts the input signal Xi(s) into a digital domain signal Yi(z). The second stage 220 converts the quantization error X₂(s) of the first stage 210, amplified by amplifier 240 having a transfer function G, into a second digital domain signal Y₂(Z), which is then subtracted from Yi(z) by the noise cancellation filter 230. The noise cancellation filter 230 includes delay and filter compensation to accurately subtract the quantization error of the first stage 210 from the output Yi(z), producing a quantized signal X₁(Z). The quantization error X₂(s) of the first stage 210 is defined as the difference between the input and output signals of the quantizer 213. However, a DAC 215 is needed to convert the digital output signal Yi(z) of the quantizer 213 into an analog representation for combining at a further adder 216 to produce the input signal X₂(s) for the second stage 220. The additional DAC 215 adds to the complexity and cost of an integrated circuit incorporating the features of the ADC, as well as subjecting the error signal X₂(s) to absolute gain variations. The DAC 215 also requires close matching of analog components to function properly.

A further problem with the above mentioned implementation of a ΣΔ ADC is that the quantization error output by a conventional ΣΔ modulator is still present and therefore needs to be removed or minimised by further processing.

OBJECT OF INVENTION It is an object of the invention to address one or more of the above mentioned problems.

SUMMARY OF INVENTION

In accordance with the invention there is provided a cascaded sigma-delta analog to digital converter comprising a first sigma-delta modulator having an input configured to receive an input signal, a second sigma-delta modulator configured to receive an error signal from the first modulator and a noise filter configured to receive an output signal from each of the first and second modulators and to provide a modulated and filtered output signal, wherein the analog to digital converter comprises an error signal adder configured to provide the error signal from the first modulator by combining an output signal from a loop filter of the first modulator with the input signal.

The first modulator preferably comprises: an input adder configured to receive the input signal at a first input; the loop filter configured to receive an output signal from the input adder; a quantizer configured to receive an output signal from the loop filter and provide a quantized output signal; and a first feedback loop between the output of the quantizer and a second input of the input adder, the feedback loop comprising a digital to analog converter.

The second modulator preferably comprises: an input adder configured to receive the error signal at a first input; a loop filter configured to receive an output signal from the input adder; - a quantizer configured to receive an output signal from the loop filter and provide a quantized output signal; and a first feedback loop between the output of the quantizer and a second input of the input adder, the feedback loop comprising a digital to analog converter.

Embodiments of the invention will now be described by way of example, with reference to the appended drawings in which: figure 1 a is a block diagram of an exemplary known ΣΔ modulator; figure 1 b is a transfer function representation of the modulator of figure 1 a; figure 2 is a block diagram of a MASH ΣΔ modulator; figure 3 is a block diagram of a MASH ΣΔ modulator according to an embodiment of the invention; figure 4a is a block diagram of an alternative ΣΔ modulator; figure 4b is a transfer function representation of the modulator of figure 4a; figure 5a is a block diagram of a further alternative ΣΔ modulator; figure 5b is a transfer function representation of the modulator of figure 5a; figure 6a is a block diagram of a further alternative ΣΔ modulator; and figure 6b is a transfer function representation of the modulator of figure 6a.

SPECIFIC DESCRIPTION OF THE EMBODIMENTS

The modulators illustrated in figures 1 and 2 have already been described as part of the background to the invention above. Shown in figure 3 is a block diagram illustration of an embodiment of a cascaded sigma-delta analog to digital converter 300 according to the invention. Most of the components of the first stage 310, the second stage 320 and the noise filter 230 of the converter 300 are as previously described with reference to the converter 200 shown in figure 2. A difference between the ADC in figure 2 and the embodiment shown in figure 3 is that the DAC 215 in figure 2 that is needed to generate the quantization error has been eliminated. In place of this, one input of the summing node or adder 216 is connected to the output of the loop filter 212 of the first stage 210. The quantization error fed to the second stage 320 is derived from the difference between the input signal X1 (s) and the loop filtered signal, which incorporates a contribution from the feedback loop.

An advantage of the invention is that of being able to eliminate one of the DACs used in the ADC. This saves on the number of active components required in an integrated circuit implementation. Subtraction using the adder 216 to obtain the error signal X2(s) can also be carried out more accurately, as this does not rely on the accuracy of an additional conversion stage. An alternative modulator may retain the DAC 215 shown in figure 2 and includes further adders and a filter to the ΣΔ modulator, in order to subtract quantization noise introduced by the quantizer 403 from the signal at the input of the quantizer 403. This embodiment is illustrated in figure 4a. The modulator 400 comprises the components present in the modulator 100 shown in figure 1 , i.e. an adder 401 receiving the input signal X(s) and a signal from a feedback loop comprising DAC 404, a loop filter 402 and a quantizer 403, resulting in an output signal Y(z). The modulator 400 further includes an additional noise-shaping coder in the main loop, comprising a DAC 415, a summation node 405 and a filter 406. This additional loop feeds the quantization error back into the main loop of the modulator 400 via a further summation node 407 between the output of the loop filter 402 and the input of the quantizer 403.

A transfer function of the input signal X and the quantization error Q to the output Y can be calculated by modelling the quantizer 403 with a quantization noise source Q and a gain of 1 , with the feedback path modelled by a gain of 1 . This transfer function representation of the modulator 400 of figure 4a is illustrated in figure 4b. A first transfer function provides the output signal Y in terms of the intermediate signal E from the loop filter:

Y = E ₊ Q(I -F) (1 )

This relationship shows that the input signal E is directly transferred to the output signal Y without being filtered or changed by the second loop. The overall stability of the modulator loop is thereby not compromised. The quantization error Q is, however, modified with a factor (1-F).

A second transfer function provides the output signal in terms of the input signal X:

The original shaping behaviour of the loop filter 402, represented by function H, is unchanged and still reduces the quantization error Q by a factor of 1 -F in the part of the frequency spectrum where H has gain.

If, in the second loop, the filter 406 has a gain of 1 , the quantization error can be fully cancelled at the output Y. The filter 406 preferably has a gain of 1 in at least a part of the frequency spectrum in which quantization noise introduced by the quantizer 403 is to be suppressed. The filter 406 may have the characteristics of a low, high or bandpass transfer function. The modulator of figures 4a and 4b can be implemented in the analog, digital or mixed analog/digital domain.

An alternative modulator is shown in figure 5a, with the equivalent transfer function representation shown in figure 5b. The first input of the summing node 405, which calculates the quantization error, now receives the input signal X(s). The DAC 415 (figure 4a) is not therefore required, enabling the subtraction operation to be carried out more accurately, because the eliminated DAC is subject to absolute gain variations and requires good matching between analog components. A further filter 506, having a transfer function G, is connected between the output of DAC 404 and a third input of adder 407. The transfer function of the output signal in terms of the intermediate signal E(s) from the loop filter 402 is then given by:

Y = E ^l- + Q ^{l ~ F} + X ^{~ F} (3)

1 - F + G 1 - F + G 1 - F + G

The transfer function of the output signal in terms of the input signal in then given by:

H - F \ - F Y = X ^- - + Q — (4)

1 + H + G - F 1 + H + G - F

From equation 3 it can be seen that if G is chosen to be equal to F, the stability of the loop is still determined by the original loop filter H 402, and the stability of the modulator 500 is not compromised. The shaping of the quantization noise function Q has not changed compared to the previous embodiment shown in figures 4a and 4b and described above.

An alternative modulator to that of figures 5a and 5b is shown in figures 6a and 6b, in which the filter 506 having transfer function G is connected instead to the output of the first summing node 401 in parallel to filter 402 having transfer function H . In this way, filter 506 operates completely in the analog domain, and only 1 feedback DAC is required.

When the transfer functions F and G of filters 406, 506 are made equal, the input signal X passes through the modulator 600 with a factor of one, if H has high gain. The quantization noise Q introduced by quantizer 403 is still suppressed by filter 402 and also by filter 406 when G is close to or equal to F. If F is close to 1 , filter 506 together with loop filter 402 determines the stability of the modulator 500.

Other embod iments are intentionally within the scope of the invention as defined by the appended claims.

Claims

CLAIMS:

1. A cascaded sigma-delta analog to digital converter (300) comprising a first sigma-delta modulator (310) having an input configured to receive an input signal (Xi(s)), a second sigma-delta modulator (320) configured to receive an error signal (X2(s)) from the first modulator (210) and a noise filter (230) configured to receive an output signal from each of the first and second modulators and to provide a modulated and filtered output signal (Xi(z)), wherein the analog to digital converter (300) comprises an error signal adder (216) configured to provide the error signal (X2(s)) from the first modulator (310) by combining an output signal from a loop filter (212) of the first modulator (310) with the input signal (Xi(s)).

2. The cascaded sigma-delta analog to digital converter (300) of claim 1 wherein the first modulator (310) comprises: - an input adder (211 ) configured to receive the input signal (Xi(s)) at a first input; the loop filter (212) configured to receive an output signal from the input adder (211 ); a quantizer (213) configured to receive an output signal from the loop filter (212) and provide a quantized output signal (Yi(z)); and a feedback loop between the output of the quantizer (213) and a second input of the input adder (21 1 ), the feedback loop comprising a digital to analog converter (214).

3. The cascaded sigma-delta analog to digital converter (300) of claim 2 wherein the second modulator (320) comprises: an input adder (221 ) configured to receive the error signal (X2(s)) at a first input; a loop filter (222) configured to receive an output signal from the input adder (221 ); a quantizer (223) configured to receive an output signal from the loop filter (222) and provide a quantized output signal (Y2(z)); and - a feedback loop between the output of the quantizer (223) and a second input of the input adder (221 ), the feedback loop comprising a digital to analog converter (224).