CN114401010A - Analog-digital conversion circuit based on adaptive delta modulation and design method - Google Patents
Analog-digital conversion circuit based on adaptive delta modulation and design method Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
- H03M3/344—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing
Abstract
The invention relates to an analog-digital conversion circuit based on self-adaptive delta modulation and a design method thereof, wherein the circuit comprises: the summing circuit is used for comparing the input analog signal with the feedback signal and calculating the difference to obtain an error signal; a filter circuit comprising at least two zeros and at least two poles for receiving the error signal; the comparator is connected with the filter circuit, and the sum of the output signals of the filter circuit is judged through the comparator; the adaptive increment coder receives the judgment result of the comparator, and carries out adaptive increment coding and decoding according to the judgment result to obtain a digital signal corresponding to the input analog signal; and a digital-to-analog converter that converts the digital signal to an analog feedback signal that is input to the summing circuit. The invention introduces more zero pole pairs in the control loop, thereby improving the suppression of quantization noise. Effectively improving the signal-to-noise ratio of the modulator or expanding the effective bandwidth of the analog-digital conversion of the system.
Description
Technical Field
The invention relates to the technical field of analog-digital converters, in particular to an analog-digital conversion circuit based on adaptive delta modulation and a design method thereof.
Background
Patent document 1 discloses an analog-to-digital converter including adaptive delta modulation. The loop filter of the scheme only adopts a gain link, so that the loop does not have a shaping function on quantization noise. Although the scheme has a simple structure and is easy to implement, the overall signal-to-noise ratio is poor, and the method has many limitations in practical application and is difficult to meet the application requirement of high precision.
Patent document 2 discloses a noise shaping method using an analog-to-digital converter including adaptive delta modulation. Because the scheme introduces integration and gain links in the loop filter, the low-frequency quantization noise can be subjected to noise shaping, and the signal-to-noise ratio in the signal bandwidth is improved.
In the scheme, an integrator is mainly adopted for shaping, and the first-order integrator is insufficient in inhibiting low-frequency quantization noise, so that the improvement of the overall signal-to-noise ratio precision is limited. To improve efficiency, in high-precision application scenarios, a higher oversampling ratio is often required to achieve a better signal-to-noise ratio. For example, in a typical audio application, to achieve a signal-to-noise ratio of greater than 96dB in a 20KHz bandwidth, the sampling frequency needs to be greater than 6.4MHz to meet the application requirements.
In another embodiment disclosed in this scheme, although a second-order integrator is introduced for noise shaping, it is difficult to stabilize in the loop design because it introduces a pair of complex zeros of the same frequency. In order to stabilize the loop, the integration coefficient of the second integrator will be limited to an extremely low range, so that the noise shaping benefit brought by introducing the second-order integrator is reduced sharply, and therefore, it is difficult to generate an effective function in circuit implementation. In addition, an additional integrator is added to the circuit, which brings additional power consumption, area and cost.
Documents of the prior art
Patent document
Patent document 1: chinese patent CN104883191B
Patent document 2: chinese patent CN104883190A
Disclosure of Invention
Problems to be solved by the invention
The invention mainly aims to provide an analog-digital conversion circuit based on adaptive delta modulation and a design method thereof, so as to solve the defects that a loop filter in the existing scheme has insufficient suppression on quantization noise, the phase margin of a feedback loop is difficult to meet the stability requirement and the like. The invention provides a universal high-order loop filter, which can realize second-order, third-order, fourth-order and other high-order loop filters, thereby effectively improving the shaping efficiency of quantization noise and conveniently realizing the analog-digital conversion with high signal-to-noise ratio.
Means for solving the problems
In order to achieve the above object, the present invention provides an adaptive delta modulation based analog-to-digital conversion circuit, including:
the summing circuit is used for comparing the input analog signal with the feedback signal and calculating the difference to obtain an error signal;
a filter circuit comprising at least two zeros and at least two poles for receiving the error signal;
a comparator connected to the filter circuit, the sum of the output signals of the filter circuit being decided by the comparator;
the self-adaptive increment encoder receives the judgment result of the comparator, and performs self-adaptive increment coding and decoding according to the judgment result to obtain a digital signal corresponding to the input analog signal; and
a digital-to-analog converter that converts the digital signal to an analog feedback signal that is input to the summing circuit.
Preferably, the filter circuit has two zeros and two poles, or three zeros and three poles, or four zeros and four poles.
Preferably, the frequencies of the poles are at low frequencies, and the frequencies of the poles are all the same, or partially the same, or different from each other.
Preferably, the frequency of the pole is at 0 or at a low frequency anywhere from 0 to 1/10 of the system sampling frequency.
Preferably, the frequency of the zero is greater than the frequency of the largest pole and less than any frequency point between the closed-loop bandwidth frequencies of the system.
Preferably, the filter circuit is a ring filter having two poles and two zeros, the frequencies of the two poles are both 0, the frequencies of the two zeros are both 1/(2 pi RzC), and the closed-loop bandwidth of the system is 1.5 times to 10 times of the zero frequency.
Preferably, the filter circuit is a ring filter having three poles and three zeros, the frequencies of the three poles are all 0 or all less than 1Hz, the frequencies of the three zeros are all 1/(2 pi RzC), one of the zeros is located on the real axis, the other two zeros are located on the complex plane, and the closed-loop bandwidth of the closed-loop system is set to be between 1.5 times and 10 times the frequency of the zero.
Preferably, the summing circuit includes a first resistor and a second resistor, a first end of the first resistor is connected to the input signal, a second end of the first resistor is connected to the filter circuit, a first end of the second resistor is connected to the digital-to-analog converter, and a second end of the second resistor is connected to a second end of the first resistor and the filter.
Preferably, the filter circuit comprises a third resistor, a fourth resistor, a first capacitor, a second capacitor and an operational amplifier, wherein,
the first end of the third resistor is connected with the analog adder and the negative end of the operational amplifier, the second end of the third resistor is connected with the first end of the first capacitor, the second end of the first capacitor is connected with the first end of the second capacitor, the second end of the second capacitor is connected with the output end of the operational amplifier, the first end of the fourth resistor is connected with the second end of the first capacitor and the first end of the second capacitor, and the second end of the fourth resistor is grounded.
In order to achieve the above object, the present invention further provides a method for designing an analog-to-digital conversion circuit based on adaptive delta modulation, comprising the following steps:
a summing circuit is arranged and used for comparing an input analog signal with a feedback signal and calculating the difference to obtain an error signal;
setting a filter circuit comprising at least two zeros and at least two poles for receiving the error signal;
setting a comparator, and judging the sum of output signals of the filter circuit through the comparator;
setting a self-adaptive increment encoder, receiving a judgment result of the comparator, and carrying out self-adaptive increment encoding and decoding according to the judgment result to obtain a digital signal corresponding to an input analog signal;
a digital to analog converter is provided to convert the digital signal to an analog feedback signal that is input to the summing circuit.
ADVANTAGEOUS EFFECTS OF INVENTION
Compared with the prior art, the invention has the following beneficial effects:
the invention introduces more zero pole pairs in the control loop, thereby improving the suppression of quantization noise. Thereby effectively improving the signal-to-noise ratio of the modulator or expanding the effective bandwidth of the analog-digital conversion of the system.
Drawings
Fig. 1 is a schematic configuration diagram of patent document 1.
Fig. 2 is a signal flow chart corresponding to the schematic configuration diagram of fig. 1.
Fig. 3 is a schematic configuration diagram of patent document 2.
Fig. 4 is a signal flow diagram corresponding to the schematic block diagram of fig. 3.
Fig. 5A is a schematic diagram of the loop filter transfer function h(s) of patent document 2.
Fig. 5B is a schematic diagram of the amplitude-frequency characteristic of the noise transfer function ntf(s) corresponding to fig. 5A.
Fig. 6A and 6B are a schematic block diagram and a schematic structural diagram of an analog-to-digital conversion circuit based on adaptive delta modulation according to the present invention.
Fig. 7 is a signal flowchart corresponding to the schematic configuration diagram of fig. 6A.
Fig. 8A is a schematic diagram of the transfer function amplitude-frequency characteristic of a loop filter h(s) of the present invention having two pairs of poles-zero.
Fig. 8B is a schematic diagram of the amplitude-frequency characteristics of the noise transfer function ntf(s) corresponding to fig. 8A.
Fig. 9 is a circuit diagram of an embodiment of an adaptive delta modulation based analog-to-digital conversion circuit according to the present invention.
Fig. 10 is a flow chart of a design method of an analog-digital conversion circuit based on adaptive delta modulation according to the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention. It should be further emphasized here that the following embodiments provide preferred embodiments, and that the various aspects (embodiments) may be used in combination or cooperation with each other.
As shown in fig. 1 and 2, a schematic block diagram and a corresponding signal flow diagram of the technical solution disclosed in the prior art patent document 1 are shown.
In the technical scheme, an input analog signal is compared with a feedback signal and an error signal is obtained by calculating the difference, wherein the feedback signal is analog output of an output digital signal after passing through a digital-analog converter, and the error signal is judged by a comparator after being amplified. And performing adaptive incremental coding and decoding according to the judgment result to obtain a digital signal corresponding to the input analog signal, thereby completing the analog-to-digital conversion of the input signal.
The equivalent signal flow diagram in the scheme is that an input signal X is compared with output through a summing circuit and sent to a gain link with gain k, and a comparator and an adaptive incremental encoder can be equivalent to a quantization error added on the basis of the input signal, namely a quantization error Eq and a coding error Ec respectively. In this scheme, the output signal Y is given by the following equation (1):
namely quantization error and coding error, the k times are equivalently weakened, thereby improving the signal-to-noise ratio of the system to a certain extent.
As shown in fig. 3 and 4, a schematic block diagram and a corresponding signal flow diagram of the technical solution disclosed in prior art patent document 2 are shown.
In the technical scheme, an input analog signal and a feedback signal are compared and subjected to difference calculation to obtain an error signal, wherein the feedback signal is analog output of an output digital signal after passing through a digital-analog converter, the error signal respectively passes through a gain and integration circuit, and the sum of output signals of the error signal is judged by a comparator. And performing adaptive incremental coding and decoding according to the judgment result to obtain a digital signal corresponding to the input analog signal, thereby completing the analog-to-digital conversion of the input signal.
The equivalent signal flow diagram in the scheme is that an input signal X is compared with output through a summing circuit and respectively sent to a gain link with a gain k and an integration link with an integration constant tau, and a comparator and an adaptive incremental encoder can be equivalent to a quantization error added on the basis of the input signal, namely a quantization error Eq and a coding error Ec respectively. In this scheme, the equivalent transfer function h(s) of the loop filter is k + τ/s, and the output signal Y is given by the following equation (2):
wherein the coefficient of X
Coefficients that can be referred to as signal transfer functions, quantization noise
May be referred to as a noise transfer function. In the scheme, an integral link is introduced, so that the gain of an integrator is large at low frequency, and the loop gain is largeHigher, the suppression capability for low frequency quantization error and coding error signals is higher. Shaping of the quantization noise and coding noise is thus accomplished.
When the signal X is concentrated within the low frequency bandwidth, then the sampling rate is doubled and the equivalent signal-to-noise ratio of the signal within the bandwidth will be improved by 9 dB.
As shown in fig. 5A and 5B, the amplitude-frequency characteristics of the loop filter transfer function h(s) and the noise transfer function ntf(s) corresponding thereto in the solution disclosed in patent document 2 are respectively shown.
From the amplitude-frequency characteristic of the loop filter transfer function h(s), it can be seen that there exists a pole with frequency 0 contributed by the integrator and a zero with frequency fc, where the frequency of the zero is smaller than the loop closed-loop bandwidth fc, so as to ensure that the system closed-loop phase margin is within the stable range.
Since the low frequency gain of the loop filter h(s) is high, the low frequency noise is effectively suppressed in the noise transfer function. When the signal bandwidth Fbw is much smaller than the loop closed-loop bandwidth, the quantization noise in the signal band can be suppressed with the efficiency of 20dB per decade, thereby effectively improving the oversampling efficiency.
Fig. 6A, 6B and 7 are schematic diagrams, structural diagrams and corresponding signal flow diagrams of an adaptive delta modulation based analog-to-digital conversion circuit according to the present invention. An analog-digital conversion circuit 1 based on adaptive delta modulation of the present invention includes: a summing circuit 11, a filtering circuit 12, a comparator 13, an adaptive incremental encoder 14, and a digital-to-analog converter (ADC)15, wherein,
the summing circuit 11 may be an analog adder for comparing and subtracting an input analog signal with a feedback signal to obtain an error signal, where the feedback signal is an analog output of an output digital signal after passing through the digital-to-analog converter 15, and the filter circuit 12 is a loop filter including two or more zeros and two or more poles. After the error signal passes through the filter circuit 12 including two or more zeros and two or more poles, the sum of the output signals is determined by the comparator 13. After the decision result is input to the adaptive increment encoder 14, the adaptive increment encoder 14 performs adaptive increment encoding and decoding according to the decision result of the comparator to obtain a digital signal corresponding to the input analog signal, thereby completing the analog-to-digital conversion of the input signal. The converted digital signal is converted into an analog feedback signal by the digital-analog converter 15.
As shown in fig. 7, an equivalent signal flow diagram of an analog-to-digital conversion circuit based on adaptive delta modulation is shown, in which an input signal X is compared with an output signal by a summing circuit 11, and is respectively sent to a gain element with a gain k and an integration element with an integration constant τ, and both the comparator 13 and the adaptive delta encoder 14 can be equivalent to a quantization error added on the basis of the input signal, which is a quantization error Eq and an encoding error Ec, respectively. In this scheme, the equivalent transfer function of the loop filter 12 is:
the output signal Y is given by the following equation:
wherein the coefficient of X
Coefficients that can be referred to as signal transfer functions, quantization noise
May be referred to as a noise transfer function. In the scheme, due to the introduction of an additional integration link, the gain of an integrator is large at low frequency, and the corresponding loop gain is high, so that the suppression capability on the low-frequency quantization error and the coding error is very high. This achieves efficient shaping of the quantization noise and coding noise.
For example, if h(s) with two pairs of zero poles is used, when the signal X is concentrated within the low frequency bandwidth, the low frequency rejection rate of the noise transfer function is 40dB/Dec, the corresponding sampling rate is doubled, and the equivalent signal-to-noise ratio of the signal within the bandwidth will be increased by 15 dB; and if H(s) with three pairs of zero poles is adopted, the oversampling efficiency of the in-band signal-to-noise ratio is improved by about 21dB per-time oversampling; the h(s) of the four pairs of poles-zero can achieve 27dB per over-sampling.
As shown in fig. 8A and 8B, the amplitude-frequency characteristic of the transfer function of the loop filter h(s) with two pairs of poles-zero and the amplitude-frequency characteristic of the noise transfer function ntf(s) corresponding thereto are shown schematically.
Where h(s) has two poles at zero frequency, and two zeros at frequencies greater than the highest frequency of the poles and less than the frequency of the closed loop bandwidth Fc, where the two zeros may be of the same frequency or different frequencies. The filter network having the h(s) transfer function characteristic may be formed using an active filter network, or may be formed in a different manner as long as the input/output transfer function characteristic of the signal matches the h(s) characteristic.
In the amplitude-frequency characteristic diagram of the noise transfer function corresponding to the loop filter h(s), Fbw is the signal bandwidth, and ntf(s) rises at a rate of 40dB per decade within the signal bandwidth. Therefore, as the oversampling rate increases, the above ntf(s) corresponds to an oversampling efficiency of 15dB per oversampling.
Fig. 9 is a circuit diagram of an embodiment of an analog-to-digital conversion circuit based on adaptive delta modulation according to the present invention.
In the circuit of the present invention, the analog adder 11 includes a first resistor Ri and a second resistor Rfb, a first end of the first resistor Ri is connected to the input signal, a second end of the first resistor Ri is connected to the filter circuit 12, a first end of the second resistor Rfb is connected to the digital-to-analog converter 15, and a second end of the second resistor Rfb is connected to a second end of the first resistor Ri and is commonly connected to the filter circuit 12.
The filter circuit 12 is a loop filter having two pairs of zero poles, the filter circuit 12 includes a third resistor Rf, a fourth resistor Rz, a first capacitor C1, a second capacitor C2 and an operational amplifier OP1, wherein an input signal is connected to an input negative terminal of the operational amplifier OP1 through a resistor Ri, the digital-to-analog converter 15 converts an output digital signal into an analog signal, and the analog signal is inverted and then added to the input terminal through the second resistor Rfb, so that the input signal of the operational amplifier OP1 is an input and feedback error.
The third resistor Rf, the fourth resistor Rz, the first capacitor C1, and the second capacitor C2 form a feedback filter network, and the feedback filter network is specifically connected as follows: a first end of the third resistor Rf is connected to the analog adder and the negative end of the operational amplifier OP1, a second end of the third resistor Rf is connected to the first end of the first capacitor C1, a second end of the first capacitor C1 is connected to the first end of the second capacitor C2, a second end of the second capacitor C2 is connected to the output end of the operational amplifier OP1, a first end of the fourth resistor Rz is connected to the second end of the first capacitor C1 and the first end of the second capacitor C2, and a second end of the fourth resistor Rz is grounded.
The feedback filter network is formed by the above steps, so that a loop filter with a transfer function H(s) of two pairs of zero poles is realized. Transfer function of the circuit
Wherein, C1// C2 ═ C1 ═ C2/(C1+ C2).
The output of the loop filter is compared and sampled by a comparator CMP and then output, and the digital signal corresponding to the INPUT signal INPUT can be obtained after the output passes through the adaptive increment coding and decoding module.
Specifically, the input signal and the feedback signal are subtracted to obtain an error signal, which is then passed through a loop filter 12 having a certain number of poles and zeros. For example, there may be 2 poles and 2 zeros; or 3 poles and 3 zeros; or 4 poles and four zeros, etc. That is to say a loop filter for at least two poles and two zeros.
The pole frequency is at a low frequency, specifically, the pole frequency may be at 0 or a low frequency anywhere from 0 to 1/10 of the system sampling frequency. The plurality of pole frequencies may be all the same, some the same, or different.
The zero frequency is any frequency point between the maximum pole frequency and the closed-loop bandwidth frequency of the system. The frequencies of the plurality of zeros may all be the same, some may be the same, or may be different.
As an alternative to a specific embodiment, a loop filter with two poles and two zeros may be set, where the pole frequency fp is 0 and the zero frequency fp is 1/(2 pi RzC). Wherein the closed loop bandwidth fc of the system is between 1.5 and 10 times the zero frequency fz.
As an alternative to another specific embodiment, a loop filter with three poles and three zeros may be set, and the pole frequencies fp are all 0 or all less than 1 Hz; the zero frequencies fz are both 1/(2 π RzC), where one zero lies on the real axis and the other two zeros lie in the complex plane. The closed loop bandwidth fc of the closed loop system is set to be between 1.5 and 10 times the zero point frequency fz.
The scheme can effectively improve the noise shaping efficiency by using the loop filter 12 with a plurality of zero pole pairs, thereby improving the oversampling efficiency of the system. For example, when the loop filter 12 with two zero pole pairs is adopted, the signal-to-noise ratio in the signal band can be improved by 15dB each time the sampling rate is increased by one time; if a loop filter 12 with three zero pole pairs is used, the in-band signal-to-noise ratio can be improved by 21dB for each doubling of the sampling rate. For example, in a typical audio signal processing, compared with the existing scheme, the sampling rate of the scheme can be reduced by more than one time to obtain the same signal-to-noise ratio, and even under the condition that the sampling rate is unchanged, the signal-to-noise ratio of the scheme can be effectively improved by more than 10dB compared with the existing scheme.
As shown in fig. 10, a flow chart of a design method of an analog-to-digital conversion circuit based on adaptive delta modulation according to the present invention is shown, and the design method of the analog-to-digital conversion circuit includes the following steps:
step S1: a summing circuit is arranged and used for comparing an input analog signal with a feedback signal and calculating the difference to obtain an error signal;
step S2: setting a filter circuit comprising at least two zeros and at least two poles for receiving the error signal;
step S3: setting a comparator, and judging the sum of output signals of the filter circuit through the comparator;
step S4: setting a self-adaptive increment encoder, receiving a judgment result of the comparator, and carrying out self-adaptive increment encoding and decoding according to the judgment result to obtain a digital signal corresponding to an input analog signal;
step S5: a digital to analog converter is provided to convert the digital signal to an analog feedback signal that is input to the summing circuit.
In summary, the present invention includes an adaptive delta modulation over-sampled analog-to-digital converter that employs a noise shaping technique. The noise shaping efficiency of the analog-digital converter adopting the adaptive delta modulation coding and decoding can be effectively improved, the signal-to-noise ratio of the system is improved, and the sampling rate is reduced. Therefore, better performance can be obtained in terms of saving system area, cost, power consumption and the like.
While the present application is described in terms of various aspects, including exemplary embodiments, the principles of the invention should not be limited to the disclosed embodiments, but are also intended to cover various modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. An adaptive delta modulation based analog-to-digital conversion circuit, comprising:
the summing circuit is used for comparing the input analog signal with the feedback signal and calculating the difference to obtain an error signal;
a filter circuit comprising at least two zeros and at least two poles for receiving the error signal;
a comparator connected to the filter circuit, the sum of the output signals of the filter circuit being decided by the comparator;
the self-adaptive increment encoder receives the judgment result of the comparator, and performs self-adaptive increment coding and decoding according to the judgment result to obtain a digital signal corresponding to the input analog signal; and
a digital-to-analog converter that converts the digital signal to an analog feedback signal that is input to the summing circuit.
2. The adaptive delta modulation based analog-to-digital conversion circuit of claim 1,
the filter circuit has two zeros and two poles, or three zeros and three poles, or four zeros and four poles.
3. The adaptive delta modulation based analog-to-digital conversion circuit of claim 1,
the frequency of the poles is in a low frequency, and the frequencies of the poles are all the same, or are partially the same, or are different.
4. The adaptive delta modulation based analog-to-digital conversion circuit of claim 3,
the frequency of the pole is at 0 or a low frequency point anywhere from 0 to 1/10 of the system sampling frequency.
5. The adaptive delta modulation based analog-to-digital conversion circuit of claim 1,
the frequency of the zero is greater than the frequency of the maximum pole and less than any frequency point between the closed-loop bandwidth frequencies of the system.
6. The adaptive delta modulation based analog-to-digital conversion circuit of claim 1,
the filter circuit is a ring filter with two poles and two zeros, the frequencies of the two poles are both 0, the frequencies of the two zeros are both 1/(2 pi RzC), and the closed-loop bandwidth of the system is 1.5 times to 10 times of the zero frequency.
7. The adaptive delta modulation based analog-to-digital conversion circuit of claim 1,
the filter circuit is a ring filter with three poles and three zeros, the frequencies of the three poles are all 0 or all less than 1Hz, the frequencies of the three zeros are all 1/(2 pi RzC), one of the zeros is located on a real number axis, the other two zeros are located on a complex plane, and the closed-loop bandwidth of the closed-loop system is set to be 1.5 times to 10 times of the frequencies of the zeros.
8. The adaptive delta modulation based analog-to-digital conversion circuit of claim 1,
the summing circuit comprises a first resistor and a second resistor, wherein the first end of the first resistor is connected with an input signal, the second end of the first resistor is connected with the filter circuit, the first end of the second resistor is connected with the digital-to-analog converter, and the second end of the second resistor is connected with the second end of the first resistor and the filter.
9. The adaptive delta modulation based analog-to-digital conversion circuit of claim 1,
the filter circuit comprises a third resistor, a fourth resistor, a first capacitor, a second capacitor and an operational amplifier,
the first end of the third resistor is connected with the analog adder and the negative end of the operational amplifier, the second end of the third resistor is connected with the first end of the first capacitor, the second end of the first capacitor is connected with the first end of the second capacitor, the second end of the second capacitor is connected with the output end of the operational amplifier, the first end of the fourth resistor is connected with the second end of the first capacitor and the first end of the second capacitor, and the second end of the fourth resistor is grounded.
10. A design method of an analog-digital conversion circuit based on adaptive delta modulation is characterized by comprising the following steps:
a summing circuit is arranged and used for comparing an input analog signal with a feedback signal and calculating the difference to obtain an error signal;
setting a filter circuit comprising at least two zeros and at least two poles for receiving the error signal;
setting a comparator, and judging the sum of output signals of the filter circuit through the comparator;
setting a self-adaptive increment encoder, receiving a judgment result of the comparator, and carrying out self-adaptive increment encoding and decoding according to the judgment result to obtain a digital signal corresponding to an input analog signal;
a digital to analog converter is provided to convert the digital signal to an analog feedback signal that is input to the summing circuit.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104883190A (en) * | 2014-02-28 | 2015-09-02 | 北京卓锐微技术有限公司 | High precision ADC with adaptive delta modulation |
| CN105009458A (en) * | 2013-02-21 | 2015-10-28 | 瑞典爱立信有限公司 | A frequency selective circuit configured to convert an analog input signal to a digital output signal |
| CN106551695A (en) * | 2015-09-24 | 2017-04-05 | 李福霞 | A kind of electrocardiosignal modulate circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105009458A (en) * | 2013-02-21 | 2015-10-28 | 瑞典爱立信有限公司 | A frequency selective circuit configured to convert an analog input signal to a digital output signal |
| CN104883190A (en) * | 2014-02-28 | 2015-09-02 | 北京卓锐微技术有限公司 | High precision ADC with adaptive delta modulation |
| CN106551695A (en) * | 2015-09-24 | 2017-04-05 | 李福霞 | A kind of electrocardiosignal modulate circuit |
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