CN114386362A

CN114386362A - Pole-based PCB (printed circuit board) unit board layout method, medium and equipment

Info

Publication number: CN114386362A
Application number: CN202210045388.1A
Authority: CN
Inventors: 韩毅; 楼斌; 吕何新; 戴国勇; 潘鹏飞; 李标
Original assignee: Zhejiang Luoqi Taike Technology Co ltd; Zhejiang Shuren University
Current assignee: Zhejiang Luoqi Taike Technology Co ltd; Zhejiang Shuren University
Priority date: 2022-01-15
Filing date: 2022-01-15
Publication date: 2022-04-22

Abstract

The invention relates to a pole-based PCB unit board layout method, medium and equipment, wherein a PCB unit board is laid to a flitch, and the PCB unit board in a preset form is always laid by using a pole updated by the flitch in the layout process until the excess material corresponding to the pole in the flitch cannot be matched with any PCB unit board; the medium is stored with a pole-based PCB unit board layout program, and when the pole-based PCB unit board layout program is executed by the processor, the pole-based PCB unit board layout method is realized; the computer device comprises a memory, a processor and a computer program stored on the memory and executable on the processor, and when the program is executed, the pole-based PCB cell layout method is realized. The invention simplifies the positioning process of the PCB unit board on the flitch, can quickly remove the infeasible pole, provides the target value of each solution of the sequencing algorithm for subsequent evaluation, is easy to realize the process in software and is converted into a software product.

Description

Pole-based PCB (printed circuit board) unit board layout method, medium and equipment

Technical Field

The present invention relates to printed circuits; a housing or structural part of an electrical device; the field of electrical component assembly manufacturing technologies, and in particular, to a pole-based PCB panel layout method, medium, and apparatus.

Background

The problem of PCB board splicing of PCB unit boards is caused along with the large-scale production process of circuit boards in the electronic industry. In the early stage, the jointed boards of the PCB unit boards are mainly decided by manual experience, and the highest utilization rate of each flitch is strived to meet the customer demands by the fewest flitches. The problem of the jointed boards of the PCB unit boards is not only an important academic problem in the field of operational planning and optimization, but also a pain point and a difficulty which always troubles PCB circuit board production enterprises and needs to be solved urgently. The problem of jointed boards of PCB unit boards belongs to the NP difficult problem, foreign scholars study similar problems of jointed boards from 1939, and until now, the business industry and the academic community still devote themselves to searching for effective mathematical models and feasible optimization methods of jointed boards of PCB unit boards.

The main situation generally faced by the PCB electronic industry is the orthogonal splicing problem of the rectangular unit boards, and how to select the positions of the small rectangular unit boards on the rectangular flitch (when the small unit boards are placed, the two sides of the rectangular unit boards are parallel to the corresponding sides of the rectangular big flitch) is considered, so that the big flitch can be fully utilized, and the most unit boards are spliced out simultaneously. At present, the mathematical model of the related research considers the utilization rate of the flitch or considers the maximum number of the spliced unit boards as the objective function value, and the research methods of the problem include but are not limited to a banding method, a simple method, a dynamic programming method, a two-stage method, a three-stage method, a four-rectangle method, a heuristic algorithm and the like. However, regardless of the method in which the problem is solved, both the positioning and sequencing processes need to be performed. The sequencing process is not obvious for partial algorithm, but if the intelligent optimization algorithm is adopted, the sequencing operation is obvious; the positioning method is the important duplication of the layout problem, and the performance of the sequencing method is completely limited by the selection of the positioning rule.

In the prior art, the positioning method mainly includes a residual rectangle method, a lower left principle, and the like. The principle of the remaining rectangle method is to consider that after a PCB unit board is put on a flitch, the remaining part of the flitch forms 4 rectangle areas, and the next PCB unit board needs to select one of the remaining 4 rectangle areas for continuous putting, as shown in FIG. 1, wherein w is_iAnd h_iIs the width and height of PCB unit board, W and H are the width and height of flitch, corresponding to (0, y)_i+h_i)、(x_i,H)、(x_i,y_i)、(x_i+w_i,0)、(W,y_i) And (0,0) and (W, H) are coordinates of each corresponding clipping point and angular point; the lower-left principle and the lower-left principle respectively represent that when the unit boards are placed, the lowest leftmost point or the leftmost lowest point of the large material board is taken as the lower left corner point of the rectangle, which is essentially based on the residual rectangle method, and the reason that the residual rectangle method is not convenient is that the determination process of the feasible residual rectangle becomes more complex with the increase of the split unit boards; the lower-left principle, as shown in fig. 2, is to consider the position of the upper right corner of the flitch as the initial entering position of a rectangular block (e.g. No. 4 PCB unit board), then continuously try down the proper position, if it can not continue to try down, try left again, if it can not continue to try left again, until it can not continue the circulation process, while the lower-left principle is as shown in fig. 3, similar to the lower-left principle, or take No. 4 PCB unit board as an example, only that each try is to find the proper position left again, and then try until it can not go around, the operation of the lower-left principle and the lower-left principle should be learned by combining the theory of line coincidence or rectangular area intersection of the calculation geometric theory, and how to select the step length of each movement is not easy.

Disclosure of Invention

The invention solves the problems in the prior art, provides an optimized pole-based PCB unit board layout method, medium and equipment, can simplify the unit board arrangement position determination process, and quickly evaluate the feasible solution of the sorting algorithm.

The technical scheme adopted by the invention is that the method for arranging the PCB unit boards based on the poles is characterized in that the PCB unit boards are arranged to a flitch, and the PCB unit boards in a preset form are arranged at the poles updated by the flitch all the time in the arranging process until the excess materials corresponding to the poles in the flitch cannot be matched with any PCB unit board.

Preferably, the method comprises the steps of:

step 1: initializing a flitch and all PCB unit boards to be distributed;

step 2: confirming a layout starting point on the flitch, and taking the layout starting point as a pole;

and step 3: aligning and laying out corresponding corner points and poles of the PCB unit board in the first preset form, and taking the laid PCB unit board as a mask;

and 4, step 4: updating the pole of the flitch and confirming the priority of the pole;

and 5: if no PCB unit board which is not laid out exists, performing the step 8, otherwise, updating the current PCB unit board allowance M, and enabling i =0 to perform the next step;

step 6: laying out corresponding corner points of the PCB unit boards in the preset shapes on the flitch according to the pole priority, if the excess material of the current flitch meets the laying-out requirement, taking the laid-out PCB unit boards as a new mask, returning to the step 4, and if the excess material of the current flitch meets the laying-out requirement, i = i +1, and carrying out the next step;

and 7: if i = M, performing the step 8, otherwise, replacing the PCB unit board in the preset form which is not laid out, and returning to the step 6;

and 8: and finishing the layout, obtaining a layout scheme, and recovering all the masked PCB unit boards to a display state.

Preferably, in step 1, any one of the material plates is placed under an XOY coordinate system, and the length and width of the PCB unit board are obtained.

Preferably, in step 2, the starting point of the layout is one of four corner points of the flitch.

Preferably, in the method, the preset configuration of the PCB unit board includes a horizontal configuration and a vertical configuration.

Preferably, in the method, the training of the preset configuration of the PCB unit board includes the following steps:

step S.1: setting a random probability p corresponding to each PCB unit board, wherein p belongs to (0,1);

step S.2: confirming the preset form of the PCB unit board based on the random probability p, and making the identification of the transversely arranged PCB unit board 1 and the identification of the vertically arranged PCB unit board 0;

step S.3: constructing a data set based on the identification of all PCB unit boards, searching other data sets corresponding to the area of the current flitch in a database, storing one data set with more set elements in the two data sets, if the number of the set elements is the same, reserving the stored data set, and adding 1 to the training times corresponding to the area of the current flitch;

step S.4: and if the training times do not reach the preset upper limit value under the condition that the areas of the flitches are the same, returning to the step S.2, otherwise, selecting the stored corresponding data set, and directly establishing the preset form of the PCB unit board by using the identification of the PCB unit board.

Preferably, in the method, after the mask is confirmed, a minimum square is constructed by the shortest side length w in all the PCB unit boards, and if the minimum square is placed at any updated pole and will exceed the boundary of the updated flitch, the updated pole is an infeasible pole, and the pole is cancelled.

Preferably, in step 4, after the infeasible poles are cancelled, the poles are sorted by priority in the order of all the poles from top to bottom or from bottom to top.

A computer-readable storage medium having stored thereon a pole-based PCB panel layout program, which when executed by a processor implements the pole-based PCB panel layout method.

A computer device comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein when the processor executes the program, the pole-based PCB unit board layout method is realized.

The invention relates to an optimized pole-based PCB unit board layout method, medium and equipment, wherein a PCB unit board is laid to a flitch, and the PCB unit board in a preset form is always laid at the pole updated by the flitch in the layout process until the excess material corresponding to the pole in the flitch cannot be matched with any PCB unit board; the medium is stored with a pole-based PCB unit board layout program, and when the pole-based PCB unit board layout program is executed by the processor, the pole-based PCB unit board layout method is realized; the computer device comprises a memory, a processor and a computer program stored on the memory and executable on the processor, and when the program is executed, the pole-based PCB cell layout method is realized.

The invention has the beneficial effects that:

(1) the positioning process of the PCB unit board on the material plate is simplified;

(2) the infeasible pole can be removed quickly, and the target value of each solution of the sequencing algorithm is provided for subsequent evaluation;

(3) the method is easy to realize in the software and can be converted into software products.

Drawings

FIG. 1 is a schematic diagram of a prior art residual rectangle method;

FIG. 2 is a schematic view of the lower left principle of the prior art;

FIG. 3 is a schematic diagram of the lower left principle of the prior art;

FIG. 4 is a diagram illustrating a comparison between the pole method and the corner method;

FIG. 5 is a flow chart of a method of the present invention;

FIG. 6 is a schematic diagram of an embodiment of the present invention.

Detailed Description

The present invention is described in further detail with reference to the following examples, but the scope of the present invention is not limited thereto.

The invention relates to a pole-based PCB unit board layout method, which is used for laying a PCB unit board to a flitch, wherein the PCB unit board in a preset form is always laid at the pole updated by the flitch in the layout process until the excess material corresponding to the pole in the flitch cannot be matched with any PCB unit board.

In the invention, firstly, the concept of 'pole' needs to be clarified, and when any PCB unit board is not laid on the flitch, the pole can be regarded as not existing or as a starting point of the layout; after a PCB unit board is arranged on a flitch, more poles begin to exist, at least including an upper left corner point, an upper right corner point and a lower right corner point of the PCB unit board, in a partial mode, a layout starting point can also be counted as a pole but is invalid, after the poles are determined, other factors are not considered in fact, only the feasible pole is selected, a corresponding corner point of a next object is arranged at the feasible pole, and then a new pole is generated and repeated until no more PCB unit boards are laid.

In the invention, it is noted that the poles are different from the angular points, and the poles are the folding points of the outer contour lines of all the PCB unit boards on the current flitch; as shown in fig. 4, fig. 4(a) is a selectable pole constructed under a pole-based layout method, and fig. 4(b) is a selectable pole constructed under an angular point-based layout method, taking the number 11 PCB unit board as an example, possible placement positions of rectangles (spaces surrounded by the

number

2, 1, 6, and 8 PCB unit boards) are easily ignored with respect to the angular point method, and the error rate of placing PCB units based on poles is lower and simpler.

As shown in fig. 5, the method comprises the steps of:

step 1: initializing a flitch and all PCB unit boards to be distributed;

in the step 1, any material plate is placed under an XOY coordinate system to obtain the length and the width of the PCB unit plate.

in the step 2, the starting point of the layout is one of four corner points of the flitch.

In the invention, the lower left corner of the flitch is taken as a layout starting point in general.

in the method, the preset forms of the PCB unit boards comprise horizontal arrangement and vertical arrangement.

In the method, the training of the preset shape of the PCB unit board comprises the following steps:

In the invention, the mask is only an operation mode, and in order to better represent the excess material of the current flitch and the corresponding pole, in the actual operation, the mask is not used, and only the pole is identified.

In the invention, the training of the preset form of the PCB unit board can be realized by adopting various algorithms, for example, the PCB unit board is prefabricated in transverse arrangement and vertical arrangement by random probability, each solution is obtained, and the optimal solution is stored, wherein the solution refers to the number (more aggregation elements) of the PCB unit boards which can be distributed under a flitch with a certain area or length and width value; the iteration maximum value is set for training, and the maximum number of the PCB unit boards can be ensured to be the largest under the flitch with the same area corresponding to the process of layout every time to a certain extent.

in the method, after a mask is confirmed, a minimum square is constructed by the shortest side length w in all the PCB unit boards, if the minimum square is placed at any updated pole and exceeds the boundary of the updated flitch, the updated pole is an infeasible pole, and the pole is cancelled.

In the step 4, after the infeasible poles are cancelled, the order of all the poles from top to bottom or from bottom to top is used as the order of the pole priorities.

In the invention, after the poles are determined, the operation process can be greatly reduced by judging the feasibility of the poles, specifically, a minimum square is constructed by the shortest side length, and the placement logic of the minimum square is set, and conventionally, each pole is judged based on the corner point of the minimum square facing to the starting point of the layout.

In the invention, for example, when the left lower corner point of the flitch is taken as a layout starting point, the order of all the current poles from bottom to top is taken as the order of the pole priorities.

in the present invention, the number of times of trial layout is identified by i is initialized to 0.

in the invention, after any PCB unit board cannot be laid out, 1 is added to the mark until the mark is the same as the M value, which indicates that a new PCB unit board cannot be added.

In the present invention, an embodiment is given:

the material plate size is L =150, W =100, the PCB unit plate size is No. 1 plate 40X 60, No. 2 plate 75X 35, No. 3 plate 70X 30, No. 4 plate 30X 25; smallest square W, size 25 x 25;

assuming that the placement order of the PCB panels is 1-2-3-4, the 1 st PCB panel is placed as shown in fig. 6(a), resulting in 3 new poles (0,60), (40,0) and (40,60), which are added to the pole set, e.g., EP = [ (0,60), (40,0), (40,60) ];

selecting the leftmost and lowermost poles (0,60) to place the No. 2 PCB unit board, as shown in FIG. 6(b), updating the new poles, and eliminating the infeasible poles (0,60), (40,60), (0,95), (40,95) and (75,95) by using the smallest square W;

sorting EP = [ (40,0), (75,0), (75,60) ], selecting the leftmost and lowermost pole (40,0) to place PCB panel No. 3, as shown in fig. 6(c), adding new poles EP = [ (40,0), (75,0), (75,60), (0,30), (40,30), (75,30), (110,0), (110,30) ], eliminating the infeasible poles (0,30), (40,0) and (75,0) with small squares W;

sorting EP = [ (40,30), (75,30), (75,60), (110,0), (110,30) ], selecting the leftmost and lowermost pole to place PCB panel No. 4, as shown in fig. 6(d), adding the new pole, eliminating the infeasible poles (0,55), (40,30), (40,55), (70,0) and (70,55) with small squares W;

on the basis, the subsequent PCB unit boards can be continuously arranged.

In order to implement the above embodiments, an embodiment of the present invention provides a computer-readable storage medium, on which a pole-based PCB panel layout program is stored, which, when executed by a processor, implements the pole-based PCB panel layout method.

According to the computer-readable storage medium of the embodiment of the invention, the pole-based PCB unit board layout program is used, so that the processor can realize the pole-based PCB unit board layout method when executing the pole-based PCB unit board layout program, thereby realizing a feasible and concise two-dimensional PCB jointed board problem pole generation and feasibility identification method, simplifying the process of determining the placement position of the PCB unit board, and quickly evaluating the feasible solution of the sorting algorithm.

In order to implement the above embodiments, the present invention provides a computer device, which includes a memory, a processor, and a computer program stored in the memory and operable on the processor, wherein when the processor executes the program, the pole-based PCB unit board layout method is implemented, so that a feasible and concise two-dimensional PCB makeup problem pole generation and feasibility identification method is implemented, a PCB unit board placement position determination process is simplified, and a feasible solution of a ranking algorithm is quickly evaluated.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A pole-based PCB unit board layout method is characterized in that: according to the method, the PCB unit boards are distributed to the flitch, the PCB unit boards in the preset form are distributed at the pole after the flitch is updated in the distribution process all the time until the excess material corresponding to the pole in the flitch cannot be matched with any PCB unit board.

2. The pole-based PCB panel layout method of claim 1, wherein: the method comprises the following steps:

step 1: initializing a flitch and all PCB unit boards to be distributed;

3. The pole-based PCB panel layout method of claim 2, wherein: in the step 1, any material plate is placed under an XOY coordinate system to obtain the length and the width of the PCB unit plate.

4. The pole-based PCB panel layout method of claim 2, wherein: in the step 2, the starting point of the layout is one of four corner points of the flitch.

5. The pole-based PCB panel layout method of claim 2, wherein: in the method, the preset forms of the PCB unit boards comprise horizontal arrangement and vertical arrangement.

6. The pole-based PCB cell board layout method of claim 5, wherein: in the method, the training of the preset shape of the PCB unit board comprises the following steps:

7. The pole-based PCB panel layout method of claim 2, wherein: in the method, after a mask is confirmed, a minimum square is constructed by the shortest side length w in all the PCB unit boards, if the minimum square is placed at any updated pole and exceeds the boundary of the updated flitch, the updated pole is an infeasible pole, and the pole is cancelled.

8. The pole-based PCB panel layout method of claim 7, wherein: in the step 4, after the infeasible poles are cancelled, the order of all the poles from top to bottom or from bottom to top is used as the order of the pole priorities.

9. A computer-readable storage medium, having stored thereon a pole-based PCB panel layout program, which when executed by a processor implements the pole-based PCB panel layout method of any of claims 1-8.

10. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor, when executing the program, implements the pole-based PCB cell board layout method according to any of claims 1-8.