CN114372439A

CN114372439A - Minimum allowance layout method, medium and equipment for isomorphic jointed boards of PCB (printed circuit board)

Info

Publication number: CN114372439A
Application number: CN202210045383.9A
Authority: CN
Inventors: 韩毅; 楼斌; 吕何新; 潘鹏飞; 戴国勇; 李标
Original assignee: Zhejiang Luoqi Taike Technology Co ltd; Zhejiang Shuren University
Current assignee: Zhejiang Luoqi Taike Technology Co ltd; Zhejiang Shuren University
Priority date: 2022-01-15
Filing date: 2022-01-15
Publication date: 2022-04-19

Abstract

The invention relates to a minimum allowance layout method, medium and equipment for a PCB isomorphic jointed board, which are used for laying out a single-size PCB unit board to a flitch; in the layout process, a plurality of PCB unit boards are arranged on a flitch along the edge in a strip mode, a scheme with the minimum waste material in the current layout is selected, and the layout is repeatedly carried out on the excess material of the flitch until no more PCB unit boards can be placed; the medium stores a minimum allowance layout program of the PCB isomorphic jointed board, and the minimum allowance layout program realizes the minimum allowance layout method of the PCB isomorphic jointed board when being executed by the processor; the computer equipment comprises a memory, a processor and a computer program which is stored on the memory and can run on the processor, and when the computer program is executed, the minimum margin layout method of the PCB isomorphic jointed boards is realized. The invention has clear rules and clear process, quickly and effectively provides a satisfactory scheme of problems, is convenient for industrial processing and cutting, is easy to realize the process in software and converts the process into a software product.

Description

Minimum allowance layout method, medium and equipment for isomorphic jointed boards of PCB (printed circuit board)

Technical Field

The present invention relates to printed circuits; a housing or structural part of an electrical device; the technical field of manufacturing of electrical component assemblies, in particular to a minimum margin layout method, medium and equipment for a PCB isomorphic jointed board.

Background

The PCB splicing problem is accompanied with the large-scale production process of circuit boards in the electronic industry. In the early stage, the PCB jointed board mainly depends on manual experience to make a decision, and the highest utilization rate of each flitch is strived to meet the customer demands by the fewest flitches. The isomorphic jointed board of the PCB refers to the jointed board problem of the unit board with single size of the PCB, and not only is the important academic problem in the field of operational optimization, but also is a pain point and a difficulty point which always troubles PCB circuit board production enterprises and needs to be solved urgently. The problem of jointed boards of PCB unit boards belongs to the NP difficult problem, foreign scholars study similar problems of jointed boards from 1939, and until now, the business industry and the academic community still devote themselves to searching for effective mathematical models and feasible optimization methods of jointed boards of PCB unit boards.

For enterprises, how to reasonably plan the splicing positions of the PCB unit boards on the flitch is mainly considered, so that the number of the PCB unit boards spliced on the flitch is the largest. At present, most of mathematical models in related researches consider the number of unit boards to be put together as an objective function value, and the solving method of the problem comprises a simplex method, a dynamic programming method, a two-stage method, a three-stage method, a four-rectangle method, an intelligent optimization algorithm and the like.

The 'strip splicing' principle is often combined with other algorithms to determine a final splicing scheme, after the placement position and the placement mode of the PCB unit board are considered to be determined, a strip is spliced on a material board at one time along the transverse direction of the uppermost edge of the PCB unit board or the longitudinal direction of the rightmost edge of the rectangle, and a plurality of unit boards are closely arranged on the strip. On the basis, the dynamic planning algorithm takes the number of the PCB unit boards contained in a certain strip to be spliced and the number of the PCB unit boards capable of being spliced and placed on the rest material plates as comprehensive consideration, and iterates and backtracks to finally generate a splicing scheme. The two-stage, three-stage and four-rectangle methods are indirectly combined with a 'strip splicing' principle and a greedy algorithm, firstly, a potential main dividing line position of an X axis or a Y axis is selected, then a secondary dividing line position of the Y axis or the X axis is selected, after a material plate is divided into a plurality of parts, the optimal strip is spliced according to the size of each part and a greedy rule, and therefore a satisfactory scheme is searched.

In summary, the algorithm of the 'strip splicing' principle, the dynamic programming and the like has the advantages that the method of 'firstly setting the splicing sequence of the unit boards and then selecting the splicing positions' can be eliminated, and the sequencing and positioning processes are directly integrated to obtain a satisfactory blanking scheme. However, the dynamic programming algorithm for the problem of the jointed boards of the unit boards with the single size is an accurate algorithm and has the characteristics of stable solution and high speed, but the dynamic programming algorithm needs to make up for the comprehensiveness of situation judgment, and the 'strip splicing' principle is that strips are selected according to the number of the jointed boards of the unit boards, so that the process is simple, and the utilization rate of the jointed boards is reduced when excess materials are left.

Disclosure of Invention

The invention solves the problems in the prior art, provides an optimized minimum margin layout method, medium and equipment for the isomorphic jointed boards of the PCB, and combines the advantages of a dynamic programming algorithm and a strip splicing mode to quickly and effectively obtain a satisfactory scheme of the problems.

The invention adopts the technical scheme that a minimum allowance layout method of a PCB isomorphic jointed board is characterized in that a PCB unit board with a single size is arranged on a material board; in the layout process, a plurality of PCB unit boards are arranged on the flitch along the edge in a strip mode, the scheme with the minimum waste material in the current layout is selected, and the layout is repeatedly carried out on the excess material of the flitch until more PCB unit boards cannot be placed.

Preferably, the method comprises the steps of:

step 1: acquiring the length L and the width W of the flitch, and enabling the long edge and the wide edge to respectively correspond to an X axis and a Y axis;

step 2: determining the length l and the width w of the single-size PCB unit board;

and step 3: determining a current processing pole EP of the flitch;

and 4, step 4: arranging a plurality of PCB unit boards on a flitch along the edge in a strip mode, and selecting a scheme with minimum waste under the current arrangement;

and 5: using a plurality of PCB unit boards corresponding to the selected scheme and corresponding waste material areas as masks;

step 6: if the excess material can be provided with at least 1 PCB unit board, updating a processing pole EP by taking the current excess material as a new material board to be processed, returning to the step 4, and otherwise, performing the next step;

and 7: and finishing the layout, obtaining a layout scheme, and recovering all the masked PCB unit boards to a display state.

Preferably, in step 3, (0,0) is used as the initialization coordinate of the processing pole EP.

Preferably, in the step 4, the edgewise layout includes:

horizontally placing the PCB unit boards along the long edge of the flitch;

horizontally placing the PCB unit board along the wide edge of the material plate;

vertically placing the PCB unit boards along the long edge of the flitch;

and vertically placing the PCB unit boards along the wide edge of the flitch.

Preferably, in the step 4, if there are at least two kinds of edgewise layouts and the areas of the wastes are the same, the number a of the PCB unit boards that can be laid out in the remainders of the blanking plates in the two kinds of layouts is calculated, and a layout scheme in which the sum of the number of the PCB unit boards in the edgewise layout and the a is large is selected.

A computer readable storage medium having stored thereon a minimum margin layout program of a PCB isomorphic panel, the minimum margin layout program of the PCB isomorphic panel when executed by a processor implementing the minimum margin layout method of the PCB isomorphic panel.

A computer device comprises a memory, a processor and a computer program which is stored on the memory and can run on the processor, wherein when the processor executes the program, the minimum margin layout method of the PCB isomorphic jigsaw is realized.

The invention relates to a minimum allowance layout method, medium and equipment of an optimized isomorphic jointed board of a PCB (printed Circuit Board), wherein a single-size PCB unit board is arranged on a flitch; in the layout process, a plurality of PCB unit boards are arranged on a flitch along the edge in a strip mode, a scheme with the minimum waste material in the current layout is selected, and the layout is repeatedly carried out on the excess material of the flitch until no more PCB unit boards can be placed; the medium stores a minimum allowance layout program of the PCB isomorphic jointed board, and the minimum allowance layout program realizes the minimum allowance layout method of the PCB isomorphic jointed board when being executed by the processor; the computer equipment comprises a memory, a processor and a computer program which is stored on the memory and can run on the processor, and when the computer program is executed, the minimum margin layout method of the PCB isomorphic jointed boards is realized.

The invention has the beneficial effects that:

(1) the rule is clear, and the process is clear;

(2) a satisfactory scheme of the problem is quickly and effectively provided;

(3) is convenient for industrial treatment and cutting;

(4) the method is easy to realize in the software and can be converted into software products.

Drawings

FIG. 1 is a schematic diagram of step 4 of the present invention;

FIG. 2 is a schematic diagram of the process of the present invention;

fig. 3 is a schematic view of embodiment 1 of the present invention.

Detailed Description

The present invention is described in further detail with reference to the following examples, but the scope of the present invention is not limited thereto.

The invention relates to a minimum allowance layout method for a PCB isomorphic jointed board, which is used for laying out a PCB unit board with a single size to a flitch; in the layout process, a plurality of PCB unit boards are arranged on the flitch along the edge in a strip mode, the scheme with the minimum waste material in the current layout is selected, and the layout is repeatedly carried out on the excess material of the flitch until more PCB unit boards cannot be placed.

In the invention, firstly, the concept of 'pole' needs to be clarified, and when any PCB unit board is not laid on the flitch, the pole can be regarded as not existing or as a starting point of the layout; when a PCB unit board is arranged on a flitch, more poles begin to exist, and the poles at least comprise an upper left angular point, an upper right angular point and a lower right angular point of the PCB unit board; the extreme point applied in the invention is generally the leftmost lower point of the residual material of the current flitch.

In the present invention, it is also clear that the "single-size" PCB unit boards all refer to single-size, rectangular, homogeneous jointed boards of PCB.

As shown in fig. 2, the method comprises the steps of:

and step 3: determining a current processing pole EP of the flitch;

in step 3, (0,0) is used as the initialization coordinate of the processing pole EP.

in step 4, the edgewise layout includes:

horizontally placing the PCB unit boards along the long edge of the flitch, as shown in figure 1 (a);

horizontally placing the PCB unit boards along the wide edge of the flitch, as shown in FIG. 1 (b);

vertically placing the PCB unit boards along the long edge of the flitch, as shown in figure 1 (c);

the PCB unit boards are vertically placed along the wide edge of the flitch as shown in fig. 1 (d).

In the step 4, if there are at least two kinds of edgewise layouts with the same waste area, the number a of the PCB unit boards capable of being laid out in the excess material of the blanking plates in the two kinds of layouts is calculated, and a layout scheme with a larger sum of the number of the PCB unit boards in the edgewise layout and the number a is selected.

In the present invention, in fact, in actual operation, the minimum margin may be the minimum remaining length or the minimum remaining area.

The steps of the present invention will be described with reference to examples.

Example 1

Flitch size is L =31, W =27, small rectangle size L =7, W = 5;

let EP = [ (0,0) ];

starting from the first point of EP, 4 kinds of strip splicing modes are checked according to the method shown in FIG. 1, and a scheme with the minimum residual length on the L or W edge is selected for strip splicing, as shown in FIG. 3 (a);

updating EP = [ (0,7) ], and continuing the operation can obtain the effect as shown in fig. 3 (b);

according to the scheme shown in fig. 3(B), EP = [ (21,7) ] is updated, when the operation is continued, two cases that the remaining minimum lengths are the same occur, that is, the margins in fig. 3(c) and fig. 3(d) are 0, at this time, a dynamic programming algorithm is called to calculate the number of the unit boards in the a remainder and the B remainder respectively, and after calculation, the sum of 4 and the number of the PCB unit boards that can be cut out from the a remainder is found to be smaller than the sum of 2 and the number of the PCB unit boards that are cut out from the B remainder, so that the cutting-out scheme is shown in fig. 3 (e);

updating EP = [ (21,14) ], and continuing to operate, wherein the final putting scheme is shown in FIG. 3 (f);

based on a theoretical value, the maximum theoretical number of the unit plates of the material plate is 23.91, and the layout scheme is reasonable.

In embodiment 1, the result obtained by using the minimum remaining length or the minimum remaining area as the minimum margin is the same, and is not described in detail, but for example, when the material plate size is 31 × 26, when the same PCB unit board is set, the remaining area of the vertical arrangement scheme is smaller when the remaining length of the vertical arrangement is the same as the remaining length of the horizontal arrangement, so that the vertical arrangement scheme can be preferentially selected as the placement scheme.

In order to implement the foregoing embodiments, the present invention provides a computer-readable storage medium, on which a minimum margin layout program of a PCB isomorphic patch is stored, wherein the minimum margin layout program of the PCB isomorphic patch realizes the minimum margin layout method of the PCB isomorphic patch when being executed by a processor.

According to the computer-readable storage medium of the embodiment of the invention, the minimum allowance layout program of the PCB isomorphic jointed board is used for realizing the minimum allowance layout method of the PCB isomorphic jointed board when a processor executes the minimum allowance layout program of the PCB isomorphic jointed board, so that a feasible and concise solution method for solving the problem of the single-size unit board jointed board considering the allowance is realized, a dynamic programming algorithm is repaired, the size of the residual materials after the strips are cut off is used as a splicing standard during strip splicing, if the residual amounts of the strips are the same, the splicing number of each residual material board is respectively calculated by adopting the dynamic programming method, and if the residual splicing number of the residual material boards is the same, the number of the unit boards in the strips is used as the standard to select the strips, so that a satisfactory scheme of the problem is finally and quickly and effectively obtained.

In order to implement the above embodiments, the present invention provides a computer device, which includes a memory, a processor, and a computer program stored in the memory and operable on the processor, wherein when the processor executes the program, the minimum margin layout method of the homogeneous jointed boards of the PCB is implemented, so as to implement a feasible and concise solution method for solving the problem of jointed boards of single-size unit boards considering margins, a dynamic programming algorithm is repaired, the size of the remaining material after a strip is cut off is used as a splicing standard in the process of splicing the strip, if the remaining amount of the strip is the same, the splicing number of each remaining material board is respectively calculated by using the dynamic programming method, and if the splicing number of the remaining material boards is the same, the number of unit boards in the strip is used as a standard to select the strip, so as to finally obtain a satisfactory scheme of the problem quickly and effectively.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A minimum margin layout method for a PCB isomorphic jointed board is characterized by comprising the following steps: the method arranges the PCB unit boards with single size to a flitch; in the layout process, a plurality of PCB unit boards are arranged on the flitch along the edge in a strip mode, the scheme with the minimum waste material in the current layout is selected, and the layout is repeatedly carried out on the excess material of the flitch until more PCB unit boards cannot be placed.

2. The method as claimed in claim 1, wherein the minimum margin layout method comprises: the method comprises the following steps:

and step 3: determining a current processing pole EP of the flitch;

3. The method as claimed in claim 2, wherein the minimum margin layout method of the isomorphic jointed boards of the PCB comprises: in step 3, (0,0) is used as the initialization coordinate of the processing pole EP.

4. The method as claimed in claim 2, wherein the minimum margin layout method of the isomorphic jointed boards of the PCB comprises: in step 4, the edgewise layout includes:

horizontally placing the PCB unit boards along the long edge of the flitch;

vertically placing the PCB unit boards along the long edge of the flitch;

and vertically placing the PCB unit boards along the wide edge of the flitch.

5. The method as claimed in claim 2, wherein the minimum margin layout method of the isomorphic jointed boards of the PCB comprises: in the step 4, if there are at least two kinds of edgewise layouts with the same waste area, the number a of the PCB unit boards capable of being laid out in the excess material of the blanking plates in the two kinds of layouts is calculated, and a layout scheme with a larger sum of the number of the PCB unit boards in the edgewise layout and the number a is selected.

6. A computer-readable storage medium, having stored thereon a minimum margin layout program of a PCB isomorphic panel, which when executed by a processor implements the minimum margin layout method of a PCB isomorphic panel as defined in any one of claims 1-5.

7. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor when executing the program implements the minimum margin layout method for a PCB isomorphic tile according to any of claims 1-5.