CN112668276A - Layout planning method based on hierarchical division - Google Patents
Layout planning method based on hierarchical division Download PDFInfo
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Abstract
The invention relates to a layout planning method based on hierarchical division, which comprises the following steps: step 1, generating a group of subproblems which only contain one module to construct an initial layout by using a module rough arrangement method and carrying out recursive division on an original problem; step 2, aiming at two illegal factors of module overlapping and module exceeding of circuit board construction potential energy function of layout, optimizing the potential energy function by using a quasi-Newton method for restricting variables with upper and lower boundaries to convert the initial layout into a legal layout; if the legalization fails, fixing the large module on the circuit board, placing the rest small modules on the circuit board, and adjusting the layout to be legal by using a layout legalization tool; step 4, outputting a final layout result; the invention provides a layout algorithm with smaller connecting line length for the two-dimensional layout planning problem.
Description
Technical Field
The invention belongs to the technical field of integrated circuit electronic automation design (VLSI EDA), and particularly relates to a layout planning method based on hierarchical division.
Background
The electronic automation design of integrated circuits adopts a hierarchical structure, and sequentially performs structure, function, logic and circuit design and physical design, wherein the physical design of the last step needs to convert the circuit representation of elements into geometric representation and convert the wire network for connecting the elements into geometric wire connection patterns. Floorplanning (Floorplanning) is a core step of physical design, abstracts elements into a layout with geometric modules not embedded into a chip, and optimizes chip area, wire length, energy consumption and the like. The layout planning is in an early stage of physical design, on one hand, feedback data of the early stage can be provided to guide adjustment of a system architecture, on the other hand, requirements of a subsequent wiring stage can be considered in the layout process, preliminary optimization is carried out on congestion and delay targets in wiring while module layout is optimized, and it can be seen that the layout planning plays a very critical step in the whole EDA design flow while guaranteeing legal placement of modules.
Because the floorplanning problem is an NP-hard problem, when the scale of the problem reaches more than one hundred levels, the precise algorithm cannot be solved in an effective time, and therefore, the current solution to the problem mainly adopts a heuristic solving algorithm. Current research methods can be divided into three categories as a whole: metaheuristic methods based on simulated annealing and inheritance, graph-based segmentation methods, and force-guided based methods. The method based on the meta-heuristic method has the problem of low solving speed, and when the module scale reaches hundreds, the solving quality is poor; the current method based on graph segmentation only performs segmentation on problems with fewer levels, does not consider the connection relation among whole modules in the segmentation, and cannot exert the capability of a graph segmentation algorithm to the maximum extent. The current performance optimization is based on force-guided methods.
In view of the above technical problems, it is desirable to improve.
Disclosure of Invention
Based on the above-mentioned shortcomings in the prior art, the present invention provides a floor planning method QinFer based on hierarchical partitioning.
In order to achieve the above purposes, the technical scheme adopted by the invention is as follows: a floor planning method based on hierarchical division is characterized in that: the method comprises the following steps:
step 1: roughly arranging modules; the method comprises the following steps of carrying out hierarchical division on an original problem, dividing a module into two parts by using a graph division method in each division so as to reduce the connection of the module between the two parts as much as possible, and dividing the circuit board according to the area ratio of the two parts of the module in parallel to the short edge of the circuit board; performing iterative division until each subproblem only comprises one module, placing each module on the corresponding sub circuit board, and generating an initialization layout in which all the modules are uniformly placed on the circuit board, but the modules may overlap or exceed the circuit board;
step 2: layout legalization adjustment; constructing a potential energy function based on the size of the overlapping area between the modules and the degree of the modules exceeding the circuit board, optimizing the potential energy function by adopting an L-BFGS-B, and when the potential energy function can be reduced to zero, legalization adjustment is successful, and skipping to the step 4; when legalization identification is carried out, if the step 3 is not called in the earlier stage, jumping to the step 3, otherwise, jumping to the step 4;
and step 3: finely arranging the modules; combining the initial layout generated in the step 1, fixing the oversized modules in the problem on the circuit board, and then uniformly distributing the rest non-oversized modules into the rest space on the circuit board in a problem hierarchical division manner, so as to generate an initial layout with more uniform module arrangement; skipping to the step 2;
and 4, step 4: outputting a layout; and outputting the calculated layout.
As a preferred embodiment of the present invention, in the step 2, the layout legalization adjustment specifically includes the following steps:
step 2.1; searching a module with an overlapping relation; the method adopts a quadtree mode to search all overlaps; in the construction of the Quadtree, each vertex corresponds to a sub-circuit board and all modules overlapped by the sub-circuit board, an initial root node corresponds to the initial circuit board and all modules, and then iterative four-division is carried out; for each module, traversing and searching all leaf nodes containing the module, and performing overlap check on all modules in the corresponding leaf nodes to find out all modules with overlap;
step 2.2; calculating the total potential energy of the layout; the invention provides concepts of horizontal/vertical embedding depth and horizontal/vertical exceeding amplitude, and provides a potential energy function for evaluating the overlapping degree of the module and the exceeding degree of the module on the circuit board based on the two concepts;
step 2.3; and performing gradient descent optimization on the potential energy function by using an L-BFGS-B algorithm.
As a preferred scheme of the present invention, in the step 3, the modules are finely arranged, and the method specifically includes the following steps:
step 3.1; fixing the super-large module; based on the leaf problem generated by the division in the step 1, each oversized module is allocated with a sub-circuit board, and the area corresponding to the sub-circuit board is used as a fixed area of the sub-circuit board; selecting a module to be fixed according to the area of the module and the characteristics of the corresponding fixed area edge, then selecting a corner of the fixed area corresponding to the module to be fixed according to the characteristics of the edge, and placing the selected oversized module to the corresponding corner;
step 3.2; non-oversized module arrangement; the non-oversized module arrangement adopts a problem iteration bipartition strategy until each sub-problem generated by division only contains one module, and the modules are placed in the corresponding distributed areas to generate an initial layout; in the problem dividing process, if the circuit board in the current problem is not a regular rectangle because the oversized module is fixed, the circuit board is not divided into fixed modules firstly and then is divided; according to the outline of the space on the circuit board, the circuit board with two sub-problems generated by division is considered to have no narrow space as much as possible, so that the modules are not easy to place, and the sequence of the modules and the circuit board division is dynamically judged.
As a preferred scheme of the present invention, in the step 3.2, the non-oversized module arrangement specifically includes the following steps:
step 3.2.1, putting the problem formed by the non-oversized module and the circuit board after the oversized module is fixed into a problem queue;
step 3.2.2, taking out a problem from the queue, and determining the cutting line of the circuit board in the problem according to the candidate cutting line, the cutting coefficient, the cutting line distance and the cutting distance;
step 3.2.3: dividing the circuit board into two parts by using the cutting line selected in the step 3.2.2;
step 3.2.4: the module is divided into two parts of fixed area proportion. Using hMetis to distribute the fixed area proportion of the modules through the automatic setting of UBfactor parameters and the setting of virtual modules in the hMeits segmentation tool;
step 3.2.5: dividing the problem into sub-problems in a mode of firstly dividing the module and then dividing the circuit board;
step 3.2.6: and (3) aiming at all the sub-problems which are generated in the step (3.2.2) and only comprise one module, placing the module in the sub-problems on the corresponding sub-circuit board, and generating an initialization layout.
The invention has the beneficial effects that:
the layout planning method framework based on hierarchical division can exert the capacity of graph division to the maximum extent, and simultaneously fully considers the connection relation of the whole module in each division in the hierarchical division process, thereby optimizing the length of the connecting line to the maximum extent. The fine module arrangement and layout legal adjustment provided by the invention can ensure that legal layout can be obtained under the hierarchical division framework; in conclusion, the layout planning method of the invention can provide the layout result with smaller network connection length in effective calculation time on the basis of ensuring the legal formation power of the layout.
Drawings
FIG. 1 is an example of the QinFier method in an embodiment of the present invention;
FIG. 2 is an illustration of a hypergraph configuration in an embodiment of the invention;
FIG. 3 is an example of a quad-Tree configuration in an embodiment of the invention;
FIG. 4 is an example of module horizontal and vertical embedding depths in an embodiment of the present invention;
FIG. 5 is an example of a module horizontal and vertical overrun amplitude in an embodiment of the present invention;
FIG. 6 is an example of a very large module securing area in an embodiment of the present invention;
FIG. 7 is a circuit board cutting line selection example in the embodiment of the present invention;
FIG. 8 is an example of the experimental results of the QinFiter method on the IBM-HB algorithm in an embodiment of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The invention solves the problems that the shape of a circuit board is fixed, the module to be placed simultaneously comprises a soft module and a hard module, and the layout planning problem is also known as a group of networks, and each network needs to be connected with a plurality of modules. The goal is to determine the shape of all the soft modules and the placement direction (horizontal/vertical) of the hard modules, place all the modules on the circuit board without overlap, while minimizing the wire length of all the nets. The invention provides a hierarchical division method (QinFier) based on graph division, which carries out maximum hierarchical division on the original problem so as to fully play the role of graph division, and simultaneously fully considers the connection relation among all modules in each division in the hierarchical division process, so the method can solve the problems existing in the current method based on graph division. The innovation of the invention can be summarized as the following points:
1. a layout planning method framework based on hierarchical division is designed, the framework can exert the graph division capability to the maximum extent, and meanwhile, the connection relation among all modules is fully considered in each division in the hierarchical division process, so that the connection line length is optimized to the maximum extent.
2. A module fine arrangement method is designed, and under the condition that a super-large module exists, a layout pattern with modules uniformly placed on a circuit board can be generated by the method through a graph segmentation technology.
3. The layout legalization adjusting method is designed, and the positions of all modules and the shapes of the soft modules can be automatically adjusted by the method, so that the goal of layout legalization adjustment is achieved.
Test results show that compared with the current graph segmentation-based method and the force guidance-based method, the method can solve the problem of obtaining the layout with shorter connecting line length. Therefore, the method can be used in the design of EDA enterprises to improve the performance of the designed integrated circuit.
The specific embodiment is as follows: a floor planning method QinFire based on hierarchical division comprises the following steps:
step 1: roughly arranging modules; the original problem is divided in a layering mode, a module is divided into two parts by using a graph dividing method firstly in each division, so that the connection of the module between the two parts is reduced as much as possible, and then the circuit board is divided in parallel to the short edge of the circuit board according to the area ratio of the module of the two parts. And (4) performing iterative division until each subproblem only comprises one module, placing each module on the corresponding daughter circuit board, and generating an initialization layout in which all the modules are uniformly placed on the circuit board, but the modules may overlap or exceed the circuit board. And skipping to the step 2.
Step 2: layout legalization adjustment; and (4) constructing a potential energy function based on the size of the overlapping area between the modules and the degree of the modules exceeding the circuit board, optimizing the potential energy function by adopting the L-BFGS-B, and when the potential energy function can be reduced to zero, legalization adjustment is successful, and skipping to the step 4. And (4) during legalization identification, if the step (3) is not called in the earlier stage, skipping to the step (3), otherwise, skipping to the step (4).
And step 3: finely arranging the modules; and (3) combining the initial layout generated in the step (1), fixing the modules with the oversize size in the problem on the circuit board, and then uniformly distributing the rest non-oversize modules into the rest space on the circuit board in a problem hierarchical division mode, so that the initial layout with more uniform module distribution is generated. And skipping to the step 2.
And 4, step 4: outputting a layout; and outputting the calculated layout.
Fig. 1 is a diagram illustrating an embodiment of the present invention.
In particular, the method comprises the following steps of,
step 1.1: the initial floorplan problem is placed in a queue.
Step 1.2: and if the queue is empty-jumped to the step 1.4, taking out a problem from the queue, if the taken-out problem only comprises one module, jumping to the step 1.2, if the taken-out problem comprises two or more modules, constructing a corresponding hypergraph, and dividing the hypergraph into two parts by using a hypergraph division algorithm hMetis so as to divide the module into two parts and jump to the step 1.3.
In the constructed hypergraph, each module in the current problem corresponds to a node, and each network corresponds to a hyper-edge. Because not only the module in the current problem but also the connection condition of the module in the current problem and the modules in other sub-problems need to be considered in the dividing process, before the hypergraph construction, the cutting direction of the circuit board in the current problem is determined, if the cutting direction is vertical, two virtual nodes R and L are constructed to be added into the hypergraph, if the cutting direction is horizontal, two virtual nodes B and U are constructed to be added into the hypergraph, and R, L, B and U are strictly limited not to be divided together in the hypergraph dividing process. Then, the invention traverses all networks containing the module in the current problem, if one network only contains the module in the current problem, a super edge is correspondingly constructed to include all the modules. If a network contains modules which are not in the current problem, the relative position relation between the positions of the modules which are not in the current problem and the cutting line (the initial default cutting line passes through the central point of the current circuit board) is judged, and then the virtual modules are used for replacing the modules which are not in the current problem. When the current cutting line is vertical, when the non-current problem module is positioned at the left side of the cutting line, the non-current problem module is replaced by a virtual node L, and when the non-current problem module is positioned at the right side of the cutting line, the non-current problem module is replaced by a virtual node R; the current cutting line is horizontal, when the module which is not in current problem is positioned above the cutting line, the module is replaced by the virtual node U, and when the module which is not in current problem is positioned below the cutting line, the module is replaced by the virtual node B.
Fig. 2 shows an example of a hypergraph configuration. The current problem includes four modules a, B, C and D, and since the cutting direction of the current circuit board is vertical, two dummy modules L and R are constructed first in the super-map construction. The original problem comprises four networks of the modules in the current problem, wherein the networks { A, D } only comprise the modules in the current problem, and corresponding super edges are directly constructed; a non-current problem module E in the network { A, B, E } is positioned at the left side of the cutting line, and replaces E with L to construct a super edge containing A, B and L; the non-current problem module in the network { C, D, F } is positioned at the right side of the cutting line, F is replaced by R, and a super edge containing C, D and R is constructed; and the non-current problem modules E and G in the network { B, E and G } are respectively positioned at the left side and the right side of the cutting line, and are respectively replaced by L and R to construct a super edge containing B, L and R.
Step 1.3: and (3) dividing the corresponding circuit board into two parts parallel to the short edge of the corresponding circuit board, so that the area ratio of the two parts is equal to that of the two parts of modules generated in the step 1.2, generating two sub-problems, and adding the two sub-problems into a queue. Jump to step 1.2.
Step 1.4: and (3) aiming at all the sub-problems which are generated in the steps 1.2 and 1.3 and only comprise one module, placing the module in the sub-problems onto the corresponding sub-circuit board, and generating an initialization layout. When the module is placed, the shape of the module is matched with the corresponding sub circuit board to the maximum extent by rotating the hard module or adjusting the shape of the soft module.
Step 2.1: modules with overlapping relationships are found.
For any two modules, whether the distance between the horizontal center point and the longitudinal center point of the two modules is respectively smaller than the half of the sum of the horizontal side length and the half of the sum of the longitudinal side length of the two modules at the same time or not is judged, if the conditions are met, the modules are overlapped, otherwise, the modules are not overlapped; to find all the modules with overlap, the general method would go through all the module pairs to make the above determination, but the computational complexity O (n) of the method is2) The calculation overhead is large. The invention uses the way of quadtree to look for all overlaps. In the construction of the Quadtree, each vertex corresponds to a sub-circuit board and all modules overlapped by the sub-circuit board, an initial root node corresponds to the initial circuit board and all modules, and then, four divisions are performed iteratively. The circuit board in the current node is divided into four parts in a cross division mode in each division, whether modules in the current node are overlapped with four sub circuit boards generated by division or not is judged, if the modules are overlapped, the modules are added into corresponding sub nodes (the modules may be simultaneously arranged in a plurality of sub nodes), when the number of the modules contained in one leaf node is smaller than tau, the division of the node is stopped, and the iterative division is carried out until all the leaf nodes are not divisible. For each module, traversing and searching all leaf nodes containing the module, and performing overlap check with all modules in the corresponding leaf nodes to find out all modules with overlap. The time complexity of the method employed in the present invention is O (nlogn)
FIG. 3 is an example of a quadtree structure, an initial problem includes 9 modules, four child nodes each including 3 modules are generated through cross division, if τ is set to be 3, the four nodes are divided again, module data included in each generated leaf node is less than 3, and division is stopped. For each module, all the child nodes containing the module are linked, and each module only carries out overlap detection with the modules in the linked child nodes, so that all the overlapped modules can be found out.
And 2.2, calculating the total potential energy of the layout.
Two factors can contribute to the potentialEnergy is generated, one is overlap between modules and one is module beyond the circuit board. For any module m in a layouti，aiIndicates its area, (x)i1,yi1) And (x)i2,yi2) Respectively its lower left and upper right corner coordinates, wiIndicating its width.
For any two modules mi and mj, the invention proposes a horizontal embedding depth
And vertical depth of insertion
Concepts, their formula is defined as follows:
fig. 4 gives examples of horizontal and vertical embedding depths in a module overlap scenario.
For module m beyond the circuit boardiThe invention proposes the concepts of horizontal excess amplitude and vertical excess amplitude, and their formulas are defined as follows:
where W and H represent the width and height of the circuit board, respectively, FIG. 5 gives an example of the horizontal and vertical excess in the case of a module excess circuit board.
Based on the above definitions of embedding depth and excess amplitude. The present invention provides the following potential energy function definitions for estimating the total module overlap and the extent of module out of board in the layout.
Where δ is a set parameter, set to 1.5 in the experiment.
And 2.3, performing gradient descent optimization on the potential energy function by using an L-BFGS-B algorithm.
For each module mi in the layout, using (xi, yi) to represent its center coordinates, xi1, yi1, xi2, and yi2 in equation (5) can be replaced with variables xi, yi, and wi, where xi and yi are unconstrained variables, constant variables for hard modules wi, and one has upper and lower bounds, respectively, for soft modules wi
And
with constrained variables. And the L-BFGS-B is used for optimizing potential energy functions of the upper and lower bound constraints of partial variables.
And step 3: the fine module arrangement includes the following steps.
And 3.1, fixing the oversized module.
The super large module in the present invention is defined as follows: suppose amaxIs the area corresponding to the largest module in the given module, if module miCorresponding area ai≥amaxω, then miAre oversized modules. Where ω is a set parameter, set to 4 in the present invention.
In the process of fixing the oversized modules, in order to control the number of the oversized modules, the upper limit of the number of the oversized modules is set to be one fourth of the total number of the modules. Based on the leaf problem generated by the division in the step 1, each oversized module is allocated with a sub-circuit board, and the area corresponding to the sub-circuit board is used as the fixed area of the sub-circuit board. In order to determine the fixed position of each oversized module within its fixed area, the edges of the fixed area are divided into three categories:
(1) fixing the edge: if an edge is part of a known initial circuit board edge, it is a fixed edge.
(2) And stabilizing the edge: when one side of one fixing area is partially or completely overlapped with the side of the other fixing area, and the oversized module corresponding to the other fixing area is fixed, the side of the fixing area is a stable side.
(3) Generally, the following steps are carried out: the remaining edges are generic except for the definition of the fixed and stable edges.
FIG. 6 is an example of the fixed area, and shows a layout obtained in step 1, in which two oversized modules are placed in the upper left corner, and their corresponding fixed areas are marked with dotted lines. The left side and the upper side of the upper fixing area are fixing edges, and the left side of the lower fixing area is a fixing edge. The upper side of the lower anchor region is initially the normal side, but if the oversized module of the upper anchor region is anchored, it becomes the stable side.
Based on the definitions of the fixed edge, the stable edge and the general edge, in the fixing of the super-large module, the module to be fixed is selected according to the area of the module and the characteristics of the corresponding fixed area edge each time, then a corner of the fixed area corresponding to the module to be fixed is selected according to the characteristics of the edge, and the selected super-large module is placed at the corresponding corner. When all the super large modules are fixed, whether the super large modules overlap or exceed the circuit board is detected, if the super large modules overlap, the overlapping is eliminated through the transverse translation and the longitudinal translation of the modules alternately, and the super large modules are completely moved onto the circuit board.
And 3.2, non-oversized module arrangement.
The non-oversized module arrangement adopts a problem iteration bipartition strategy until each sub-problem generated by division only contains one module, and the modules are placed in the corresponding distributed areas to generate an initial layout. The initial problem is the residual space on all the circuit boards after the non-oversized modules and the oversized modules are fixed, and in the problem dividing process, if the circuit board in the current problem is not a regular rectangle because the oversized modules are fixed, the fixed sequence of firstly dividing the modules and then dividing the circuit board is not needed in the problem dividing process. According to the outline of the space on the circuit board, the circuit board with two sub-problems generated by division is considered to have no narrow space as much as possible, so that the modules are not easy to place, and the sequence of the modules and the circuit board division is dynamically judged.
Step 3.1 fixing the oversized module comprises the following steps.
Step 3.1.1 selection of fixed modules: if all the super-large modules are fixed, skipping to step 3.1.4, otherwise, according to the dictionary sequence < the area of the modules, the number of the fixed edges of the corresponding fixed area of the modules, the number of the stable edges of the corresponding fixed area of the modules, preferentially selecting the unfixed super-large module with a large corresponding value as the module to be fixed.
Step 3.1.2 selection of fixed position: according to the priority of the < fixed edge, stable edge and general edge >, the edges in the vertical direction and the horizontal direction are selected, and the angle formed by the two selected edges is used as a fixed position.
Step 3.1.3 Place the oversized module: and (3) rotating the super-large hard module or adjusting the super-large soft module to enable the shape of the super-large module to be matched with the shape of the corresponding fixed area to the maximum extent, and then placing one corner of the super-large module at the placing position selected in the step (3.1.2). Jump to step 3.1.1
Step 3.1.4 layout legalization adjustment of the super-large module: when the overlaping or oversized circuit board exists in the oversized module, the oversized module exceeding the circuit board is firstly horizontally and vertically translated to enable the oversized module to be exactly (the edge of the outer side is overlapped with the circuit board) and completely positioned on the circuit board. Then, any two modules which are overlapped are searched from top to bottom in the horizontal direction, and the overlapped parts are sequentially moved away by moving the modules below. If the overlap still exists after the horizontal movement, any two overlapped modules are searched from left to right, and the overlap is moved away in sequence by moving the module on the right. The above movement actions are performed alternately, and the legalization adjustment is ended when all overlaps are eliminated, or when none of the overlaps are removed by the continuous horizontal and vertical movements.
Step 3.2 non-oversized module arrangement comprises the following steps.
And 3.2.1, putting the problem formed by the non-oversized module and the circuit board after the oversized module is fixed into a problem queue.
3.2.2 if the queue is empty jump to 3.2.5, taking out a problem from the queue, if the taken-out problem only contains one module, jumping to 3.2.2, otherwise, dividing the problem, and firstly determining the cutting line of the circuit board in the current problem. The following definitions of candidate cutting lines, cutting coefficients, cutting line distances and cutting distance concepts used in the determination of the cutting lines are given, and the four concepts are all proposed by the present invention.
(1) Candidate cut lines: and taking the direction of the short side of the current circuit board as the direction of the candidate cutting line according to the size of the current circuit board. The extension lines of the outer edge outlines of the current circuit board empty spaces in the direction of the candidate cutting lines constitute all the candidate cutting lines.
(2) Cutting coefficient: for a candidate cutting line, if the candidate cutting line is used for cutting, the ratio of the small area to the large area in the two generated sub circuit boards is the cutting coefficient.
(3) Cut line distance (Li to Lj): each candidate cut line may be divided into a number of real line segments, which are line segments that overlap with the edges of the white space outline or that pass through the module, and a number of imaginary line segments, which are otherwise dashed. If the Li to Lj direction is vertical and the projection of the imaginary line segment on Li onto Lj overlaps the solid line segment on Lj, the distance is equal to | xi-xjElse the distance, etc. is equal to the width of the circuit board. If the Li to Lj direction is horizontal and the projection of the imaginary line segment on Li onto Lj overlaps the solid line segment on Lj, then the distance is equal to | yi-yjElse the distance is equal to the height of the circuit board.
(4) Cutting distance: taking the minimum distance from one candidate cutting line to all other cutting lines as the cutting distance
Based on the above definition, the cutting line determination method of the present invention first determines all candidate cutting lines according to the circuit board size of the current problem. And then, the candidate cutting line with the cutting coefficient smaller than ξ (which is set as 1/4 in the invention) is excluded, if the number of the remaining candidate cutting lines after exclusion is zero, the step 3.2.5 is skipped, and otherwise, the remaining candidate cutting line with the largest cutting distance is selected as the final cutting line.
Fig. 7 is a circuit board cut line selection example, and there are 6 candidate cut lines, of which L0, L4, and L5 are excluded first because their cut coefficients are small. The cutting distance of L3 is equal to the distance between L3 and L4, the cutting distance of L1 is equal to the distance between L1 and L2, and the cutting distance of L2 is equal to the distance between L2 and L4, and is selected as the final cut line because the cutting distance of L2 is the largest.
Step 3.2.3: the circuit board is divided into two parts using the cutting lines selected in step 3.2.2.
Step 3.2.4: the module is divided into two parts of fixed area proportion. Suppose the blank areas of the two daughter circuit boards generated in step 3.2.3 are respectively
And
the goal of this step is to divide the modules in question into two sets C1 faces C2 so that their areas are
And
the following constraints are satisfied:
the bias is a set parameter used for controlling the matching error between the area of the two divided modules and the area of the circuit board.
The hypergraph (Module) segmentation hMeits method adopted in step 1.2 divides the Module into two parts so that the area between the two parts
And
the difference satisfies the following constraints:
wherein UBfactor is a setting parameter. The hypergraph segmentation method can only ensure that the difference value of the area of the two divided parts is smaller than a certain interval, and the hypergraph segmentation algorithm cannot be directly used for achieving the purpose in the formula (6).
The original problem can be recursively cut using hmis for the purpose of equation (6), i.e., when
When the area allocated to the modules in set C2 is out of expectations, the partial modules are split from C2 using hMetis and allocated to C1; when in use
When the area allocated to modules in set C1 is out of expectations, partial modules are allocated to C2 using hMetis to split from C1. The recursive partitioning adjusts the area of the blocks in C1 and C2 until equation (6) is satisfied. In the above conventional segmentation using hmis, the fixed UBfactor setting needs to call hmis for segmentation many times, and the final optimization effect is not good enough. The invention adopts dynamic UBfactor setting, and can greatly optimize the effect of hypergraph segmentation with fixed proportion.
Step 3.2.5: the way of splitting the module first and then splitting the circuit board splits the problem into sub-problems, the same as in step 1.2.
Step 3.2.6: and (3) aiming at all the sub-problems which are generated in the step (3.2.2) and only comprise one module, placing the module in the sub-problems on the corresponding sub-circuit board, and generating an initialization layout. When the module is placed, the shape of the module is matched with the corresponding sub circuit board to the maximum extent by rotating the hard module or adjusting the shape of the soft module.
Step 3.2.4: dividing the module into two parts of fixed area ratio includes the following steps.
Suppose that the blank areas of the two sub-circuit boards are respectively
And
cu denotes unassigned modules, and C1 and C2 are the two sets of modules that the final partition generates. Cu is initially C and C1 and C2 are initially empty, and the method employed in this patent is to recursively assign the modules in Cu to C1 and C2 so that their areas are such that
And
the constraint in equation (6) is satisfied.
The method adopted is to recursively combine CuModule of (1) is assigned to C1And C2So that their area
The blank areas of the two sub circuit boards are respectively
And
the goal of this step is to divide the set of modules C in question into two sets C1 and C2, such that their areas are
And
equation (6) is satisfied. Cu indicates that unassigned modules are initially C, and C1 and C2 are initially empty. The scheme adopts the method of recursively allocating modules in Cu to C1 and C2 so that the areas of the modules are equal to the area of the modules
Step 3.2.4.1: UBfactor parameters and virtual module settings. Assume that A1 and A2 are the two sets into which Cu is expected to be dividedArea of (i) i
If A1≥A2Setting an area of (A)1-A2) The virtual module of/2 (without network connection with other modules) is fixed on the Cu2 side; if A1＜A2Setting an area of (A)2-A1) A/2 dummy module and fixed to the Cu1 side. UBfactor is set to 50 × (A)1-A2)/(3A1+A2)。
Step 3.2.4.2: and (5) dividing the hypergraph. Use of CuConstructing a hypergraph by using the modules in (1), and setting the UBfactor parameters and the virtual modules in the step (3.2.4.1) and C by using the hMetisuIs divided into Cu1And Cu2Two parts. If it is
C is to beu1And Cu2Are respectively assigned to C1And C2. If it is
Then C will beu1Is assigned to C1And C isu2Is given to CuAnd skipping to step 3.2.4.1. If it is
Then C will beu2Is assigned to C2And C isu1Is given to CuAnd skipping to step 3.2.4.1.
And 4, step 4: and (6) layout output. And outputting the calculated layout.
FIG. 8 is the experimental results of the inventive method QinFire on the IBM-HB calculation example, showing that the inventive method improves wiring optimization by 7.3% and 2.1% over the graph partitioning based method DeFer and the force guidance based method F-FM, respectively.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention; thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (4)
1. A floor planning method based on hierarchical division is characterized in that: the method comprises the following steps:
step 1: roughly arranging modules; the method comprises the following steps of carrying out hierarchical division on an original problem, dividing a module into two parts by using a graph division method in each division so as to reduce the connection of the module between the two parts as much as possible, and dividing the circuit board according to the area ratio of the two parts of the module in parallel to the short edge of the circuit board; performing iterative division until each subproblem only comprises one module, placing each module on the corresponding sub circuit board, and generating an initialization layout in which all the modules are uniformly placed on the circuit board, but the modules may overlap or exceed the circuit board;
step 2: layout legalization adjustment; constructing a potential energy function based on the size of the overlapping area between the modules and the degree of the modules exceeding the circuit board, optimizing the potential energy function by adopting an L-BFGS-B, and when the potential energy function can be reduced to zero, legalization adjustment is successful, and skipping to the step 4; when legalization identification is carried out, if the step 3 is not called in the earlier stage, jumping to the step 3, otherwise, jumping to the step 4;
and step 3: finely arranging the modules; combining the initial layout generated in the step 1, fixing the oversized modules in the problem on the circuit board, and then uniformly distributing the rest non-oversized modules into the rest space on the circuit board in a problem hierarchical division manner, so as to generate an initial layout with more uniform module arrangement; skipping to the step 2;
and 4, step 4: outputting a layout; and outputting the calculated layout.
2. The floorplanning method based on hierarchical partitioning as claimed in claim 1, wherein the legalization adjustment of the floorplanning in the step 2 specifically includes the following steps:
step 2.1; searching a module with an overlapping relation; the method adopts a quadtree mode to search all overlaps; in the construction of the Quadtree, each vertex corresponds to a sub-circuit board and all modules overlapped by the sub-circuit board, an initial root node corresponds to the initial circuit board and all modules, and then iterative four-division is carried out; for each module, traversing and searching all leaf nodes containing the module, and performing overlap check on all modules in the corresponding leaf nodes to find out all modules with overlap;
step 2.2; calculating the total potential energy of the layout; the invention provides concepts of horizontal/vertical embedding depth and horizontal/vertical exceeding amplitude, and provides a potential energy function for evaluating the overlapping degree of the module and the exceeding degree of the module on the circuit board based on the two concepts;
step 2.3; and performing gradient descent optimization on the potential energy function by using an L-BFGS-B algorithm.
3. The floorplanning method based on hierarchical partitioning as claimed in claim 1, wherein in the step 3, the module fine-layout specifically includes the following steps:
step 3.1; fixing the super-large module; based on the leaf problem generated by the division in the step 1, each oversized module is allocated with a sub-circuit board, and the area corresponding to the sub-circuit board is used as a fixed area of the sub-circuit board; selecting a module to be fixed according to the area of the module and the characteristics of the corresponding fixed area edge, then selecting a corner of the fixed area corresponding to the module to be fixed according to the characteristics of the edge, and placing the selected oversized module to the corresponding corner;
step 3.2; non-oversized module arrangement; the non-oversized module arrangement adopts a problem iteration bipartition strategy until each sub-problem generated by division only contains one module, and the modules are placed in the corresponding distributed areas to generate an initial layout; in the problem dividing process, if the circuit board in the current problem is not a regular rectangle because the oversized module is fixed, the circuit board is not divided into fixed modules firstly and then is divided; according to the outline of the space on the circuit board, the circuit board with two sub-problems generated by division is considered to have no narrow space as much as possible, so that the modules are not easy to place, and the sequence of the modules and the circuit board division is dynamically judged.
4. The floorplanning method based on hierarchical partitioning as claimed in claim 1, wherein the step 3.2 of non-oversized module arrangement specifically includes the following steps:
step 3.2.1, putting the problem formed by the non-oversized module and the circuit board after the oversized module is fixed into a problem queue;
step 3.2.2, taking out a problem from the queue, and determining the cutting line of the circuit board in the problem according to the candidate cutting line, the cutting coefficient, the cutting line distance and the cutting distance;
step 3.2.3: dividing the circuit board into two parts by using the cutting line selected in the step 3.2.2;
step 3.2.4: the module is divided into two parts of fixed area proportion. Using hMetis to distribute the fixed area proportion of the modules through the automatic setting of UBfactor parameters and the setting of virtual modules in the hMeits segmentation tool;
step 3.2.5: dividing the problem into sub-problems in a mode of firstly dividing the module and then dividing the circuit board;
step 3.2.6: and (3) aiming at all the sub-problems which are generated in the step (3.2.2) and only comprise one module, placing the module in the sub-problems on the corresponding sub-circuit board, and generating an initialization layout.
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