CN114384969A - High-speed true random number generation system - Google Patents
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Abstract
The invention discloses a high-speed true random number generation system, which comprises a true random number generation module and a processor; the true random number generation module is configured to generate an N-way true random number sequence; the processor is configured to control a rate of the N-way true random number module sequence; the process of the processor controlling the speed of the plurality of groups of true random number module sequences is as follows: the processor outputs an I/O port, controls an enabling pin of a physical noise chip by outputting high and low levels, controls random number output by chip selection, enables a true random number module sequence to reach the true random number sequence rate required by a system and shifts the true random number sequence, and serially outputs a high-speed random bit stream. The invention generates a true random number sequence through the true random number generation module, controls the speed of the true random number sequence through the FPGA processor to enable the true random number sequence to serially output a high-speed random bit stream, improves the security of the secret key in the transmission process, and simultaneously improves the QKD problem of the distribution speed of the system secret key.
Description
Technical Field
The invention relates to the field of quantum random numbers, in particular to a high-speed true random number generation system.
Background
True random number generators are widely used in various fields in the information traffic society nowadays, especially in occasions where security is important. The true random number generator is not only an important component of modern communication, but the generation of random numbers is rather a building of a safe foundation.
In modern communications, people mainly encrypt, decrypt, authenticate, and the like information by random numbers. The upper limit of the random number rate generated by the true random number generator is determined by the characteristics of the entropy source, and although the random number generating chip has achieved a certain achievement in recent years, the rate of the random number generating chip does not meet the requirement of a random system. The random numbers are mainly generated by a true random number generator and a pseudo random number generator. The former is a true random number generated by a physical chip, has non-speculativity and independence and achieves true randomness, but the main problem is that the rate of generating a random sequence cannot meet the requirements of modern communication. The latter is by means of an encryption algorithm, such as: symmetric encryption, asymmetric encryption, hash algorithm and the like, and the true randomness is realized through software operation. However, since the algorithm and the seed are fixed and regularly circulated, the random number is predictable and reproducible, so that the random number is called a pseudo-random number, and cannot satisfy a high-performance encryption system. Such as: a quantum key distribution system. Therefore, there is a need to improve the prior art to propose random numbers with better accuracy.
The existing random number generator mainly realizes true random by a method of generating a pseudo random number through an algorithm, and has the defect that the algorithm has no random statement once being decoded. The other method is that the noise source random number generates true random, and the defect is that the rate is too low to meet the encryption service requirement of the system.
Therefore, there is a need for further improvement of the conventional random number generator, which is a high-speed, high-quality random number generator with simple and reliable circuit, easy implementation, low cost and embeddable in other applications.
Disclosure of Invention
In order to solve the technical problem, an embeddable random number system which has better precision and ensures the system safety is provided.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows: a high-speed true random number generation system is characterized by comprising a true random number generation module and a processor;
the true random number generation module is configured to generate an N-way parallel true random number sequence;
the processor is configured to control the rate at which the N-way parallel true random number sequence is generated;
the process of controlling the speed of generating the N paths of parallel true random number sequences by the processor is as follows:
step 1: the processor outputs high and low levels through an output I/O port to control an enable pin of the physical noise chip, and random number output is controlled through chip selection;
step 2: the processor controls the N paths of parallel true random number sequences to reach the rate of the true random number sequences, then the N paths of parallel true random number sequences are subjected to shift processing, and high-rate random bit streams are serially output;
the high rate refers to a random data stream with a rate of more than 50 MHZ;
the processor shifts the N paths of parallel true random number sequences to process the shift frequency F according to the following calculation formula:
f is F X, where F is the transmission rate of the random sequence and X is the bit width of the shift.
Preferably, the true random number generation module comprises a physical noise chip for generating a true random number module sequence.
Preferably, the physical noise chip is a digital physical noise source chip, and the digital physical noise source chip is provided with N groups, which are respectively a first noise source chip, a second noise source chip, a third noise source chip, and … … nth noise source chip.
Preferably, the N digital physical noise source chips convert randomly generated jitter noise into random numbers by an internal oscillation sampling method, and a plurality of groups of random numbers form a random number sequence.
Preferably, the processor is an FPGA processor.
Preferably, the digital physical noise source chip outputs a signal to the FPGA processor, and internal delay of the output signal is performed by the FPGA processor, so that delay generated in circuit transmission of data and clock data is eliminated.
Preferably, the delay value and the delay amount are determined according to an input data period T;
the T is divided into 64 taps, the delay step length of each step tap is T/64, and the maximum delay step length is 32 taps.
Preferably, the processor comprises a shift trigger clock, and the shift trigger clock outputs a high-frequency clock signal through a PLL frequency multiplier circuit by an internal or external clock generating circuit.
Preferably, the shift trigger clock performs sampling shift on the N-path parallel true random number sequence by using the generated high-frequency clock signal, and outputs the multiple paths of low-speed parallel random sequences to the serial random sequence through the shift.
Preferably, the shift processing is performed by a shift register in which the number of bits to be shifted is X bits.
The invention has the beneficial technical effects that: the invention generates a true random number sequence through the true random number generation module, controls the speed of the true random number sequence through the FPGA processor to enable the true random number sequence to serially output a high-speed random bit stream, improves the security of the secret key in the transmission process, and simultaneously improves the QKD problem of the distribution speed of the system secret key.
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FIG. 1 is a block diagram of the overall structure of the present invention;
fig. 2 is a block diagram showing the overall structure of the trigger signal synchronizing circuit according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments, but the scope of the present invention is not limited to the following embodiments.
As shown in fig. 1-2, a system for generating high-speed true random numbers includes a true random number generating module and a processor, wherein the processor employs an FPGA processor;
the true random number generation module is configured to generate an N-way parallel true random number sequence;
the FPGA processor is configured to control the rate of generating the N-path parallel true random number sequences;
the FPGA processor controls the process of generating the N-path parallel true random number sequence rate as follows:
the FPGA processor outputs an I/O port, controls an enabling pin of a physical noise chip by outputting high and low levels, controls random number output by chip selection, enables a true random number sequence to reach the true random number sequence rate required by a system, shifts the true random number sequence, and serially outputs a high-speed random bit stream.
The true random number generation module comprises WNG series physical noise chips, and generates a true random number module sequence through the physical noise chips.
Specifically, the physical noise chip adopts a digital physical noise source chip, the digital physical noise source chip has N pieces, namely a first noise source chip #1, a second noise source chip #2, third noise source chips #3 and … …, an nth noise source chip # N and the like, and the N pieces of digital physical noise source chips generate physical noise and output an N-path parallel true random number sequence.
Specifically, the output N-path parallel true random number sequence is a physical noise chip that converts generated jitter noise into a random number by using an internal oscillation sampling method, and the jitter noise is random in the process, that is, the generated random sequence also meets the random characteristics, and the random sequence meets the true random characteristics, but the rate of the random number is not high, so that the rate of the random number needs to be improved by an FPGA processor.
The main control chip of the FPGA processor adopts an Intel EP4CGX series chip, and the main control chip processes the random sequence output by each path so as to improve the rate of random numbers.
The FPGA processor processing process and the method are as follows: the N digital physical noise source chips output random number signals to the FPGA processor, Idelay delay inside the processor main control chip is used for eliminating delay generated by data and clock data in circuit transmission, and strict synchronization of the data is guaranteed.
The Idelay delay process can be implemented by manual debugging setting or by an automatic algorithm, and the delay value and the delay amount of the Idelay delay process are determined according to the input data period T. Dividing T into 64 taps, setting the delay step of each tap to be T/64 and the maximum delay step to be 32 taps, and setting the delay amount according to the transmission performance of the circuit so as to achieve the effect of synchronization. And simultaneously, N paths of low-input random numbers are used for sampling and shifting input data by using an internal high-speed clock and an N-bit shift register, and finally a serial random sequence is output (the shifting is to output the serial random sequence by shifting a plurality of paths of low-speed parallel random sequences).
The shift rate is determined according to the internal configuration clock trigger signal. The frequency configuration requirement is satisfied: f ═ F × X. Where f is the transmission rate of the random sequence and X is the shift bit width. The shift trigger clock can output a high-frequency clock signal through the PLL frequency multiplier circuit through an internal or external clock generating circuit. The random number rate generated after the shift processing reaches the level of the rate of the high-frequency clock signal, so that a high-speed random number bit stream is serially output, and the practical problem of low true random number rate is solved.
Variations and modifications to the above-described embodiments may occur to those skilled in the art, which fall within the scope and spirit of the above description. Therefore, the present invention is not limited to the specific embodiments disclosed and described above, and some modifications and variations of the present invention should fall within the scope of the claims of the present invention. Furthermore, although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.
Claims (10)
1. A high-speed true random number generation system is characterized by comprising a true random number generation module and a processor;
the true random number generation module is configured to generate an N-way parallel true random number sequence;
the processor is configured to control the rate at which the N-way parallel true random number sequence is generated;
the process of controlling the speed of generating the N paths of parallel true random number sequences by the processor is as follows:
step 1: the processor outputs high and low levels through an output I/O port to control an enable pin of the physical noise chip, and random number output is controlled through chip selection;
step 2: the processor controls the N paths of parallel true random number sequences to reach the rate of the true random number sequences, then the N paths of parallel true random number sequences are subjected to shift processing, and high-rate random bit streams are serially output;
the high rate refers to a random data stream with a rate of more than 50 MHZ;
the processor shifts the N paths of parallel true random number sequences to process the shift frequency F according to the following calculation formula:
f is F X, where F is the transmission rate of the random sequence and X is the bit width of the shift.
2. A high speed true random number generation system as recited in claim 1 wherein said true random number generation module comprises a physical noise chip for generating a sequence of true random number modules.
3. The system for generating high-speed true random numbers according to claim 2, wherein the physical noise chips are digital physical noise source chips, and the digital physical noise source chips are provided with N groups, namely a first noise source chip, a second noise source chip, a third noise source chip and an … … N noise source chip.
4. A high-speed true random number generating system as claimed in claim 3, wherein N of said digital physical noise source chips convert randomly generated dither noise into random numbers by means of internal oscillation sampling, and a plurality of groups of random numbers form a random number sequence.
5. A high speed true random number generation system as recited in claim 3 wherein said processor is an FPGA processor.
6. The system for generating high speed true random numbers according to claim 4, wherein the digital physical noise source chip outputs signals to the FPGA processor, and internal delay of the output signals is performed by the FPGA processor, so that delay generated in circuit transmission by data and clock data is eliminated.
7. A high-speed true random number generation system as recited in claim 6, wherein said delay value and amount are determined based on an input data period T;
the period T is divided into 64 taps, the delay step of each step tap is T/64, and the maximum delay step is 32 taps.
8. The system for generating high speed true random numbers of claim 7 wherein the processor includes a shift trigger clock, the shift trigger clock outputting the high frequency clock signal via the PLL multiplier circuit via an internal or external clock generating circuit.
9. The system for generating high speed true random numbers according to claim 7, wherein the shift trigger clock samples and shifts the N-way parallel true random number sequence by the generated high frequency clock signal, and outputs the multiple low speed parallel random sequences as serial random sequences by shifting.
10. The system for generating high speed true random numbers of claim 8, wherein the shifting process is performed by shifting a shift register having X bits.
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| CN107608657A (en) * | 2017-08-17 | 2018-01-19 | 华南师范大学 | It is a kind of based on when width conversion adjustable true random number generation system |
| CN109271136A (en) * | 2018-08-06 | 2019-01-25 | 上海交通大学 | Real random number generator and method for generation based on FPGA |
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2021
- 2021-12-28 CN CN202111630135.2A patent/CN114384969B/en active Active
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|---|---|---|---|---|
| JPH0736673A (en) * | 1993-07-20 | 1995-02-07 | Canon Inc | Random-number generator, communication system using the same and device therefor |
| KR19990076323A (en) * | 1998-03-31 | 1999-10-15 | 윤종용 | Boundary scan standard interface circuit for microprocessor emulation mode |
| CN103019648A (en) * | 2012-11-27 | 2013-04-03 | 天津大学 | True random number generator with digital post-processing circuit |
| CN103188075A (en) * | 2013-02-01 | 2013-07-03 | 广州大学 | Secret key and true random number generator and method for generating secret key and true random number |
| US20140056425A1 (en) * | 2013-03-07 | 2014-02-27 | David M. Hutchinson | One Pad Communications |
| CN104516715A (en) * | 2014-12-29 | 2015-04-15 | 太原理工大学 | Tbps all-optical parallel true random number generator with extra-strong scalability |
| CN105955707A (en) * | 2016-04-27 | 2016-09-21 | 太原理工大学 | Oversampling high-speed real-time optical true random number generator |
| CN107608657A (en) * | 2017-08-17 | 2018-01-19 | 华南师范大学 | It is a kind of based on when width conversion adjustable true random number generation system |
| CN109271136A (en) * | 2018-08-06 | 2019-01-25 | 上海交通大学 | Real random number generator and method for generation based on FPGA |
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