CN114384400A - Positioning system and positioning method for chip abnormal signals - Google Patents
Positioning system and positioning method for chip abnormal signals Download PDFInfo
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Abstract
The present disclosure relates to electronic technologies, and in particular, to a system and a method for positioning abnormal signals on a chip. According to the method, a positioning system composed of a chip, an editable logic device and a logic analyzer is firstly established, then serial sampling is carried out on a preset number of parallel signals according to a preset sampling frequency according to a clock signal based on a parallel-serial signal converter arranged in the chip, and at least one serial signal obtained by serial sampling and the clock signal are output from an output port of the chip in a one-to-one correspondence mode; secondly, receiving at least one serial signal and a clock signal output by an output port by using an editable logic device, restoring the at least one serial signal into parallel signals with preset quantity according to the clock signal and sampling frequency, and outputting the restored parallel signals to a logic analyzer; and finally, positioning the abnormal signals of the received parallel signals by using a logic analyzer. The positioning system and the positioning method provided by the application can be used for quickly positioning the abnormal signals in the chip.
Description
Technical Field
The present disclosure relates to electronic technologies, and in particular, to a system and a method for positioning abnormal signals on a chip.
Background
With the development of science and technology, chips have been applied to various industries, and the reliability of chip functions directly affects whether the system in which the chip is located can safely and stably operate. Therefore, when a problem occurs in debugging or use before the chip is put into operation, an abnormal signal in a plurality of signals inside the chip needs to be accurately located, so that a logic function corresponding to the abnormal signal is debugged.
Generally, in order to locate an abnormal signal of a chip, a plurality of signals inside the chip need to be mapped to a plurality of output ports of the chip in a one-to-one correspondence manner, the plurality of signals inside the chip are transmitted to a logic analyzer in parallel through the respective output ports, and the logic analyzer analyzes the received signals, so as to determine the abnormal signal in the plurality of signals. However, as the chip size is continuously reduced, the functions are more and more, and accordingly, the chip internal signals to be analyzed in the debugging process are more and more. However, due to the reduction of the size, the output ports reserved for debugging the chip are fewer and fewer, and are usually less than the number of signals to be analyzed, so that in the debugging process, the output signals corresponding to the output ports need to be frequently switched to find the abnormal signals, and thus, a large amount of time is required to locate the abnormal signals.
Therefore, a system and a method for locating abnormal signals on a chip are needed to solve the above problems.
Disclosure of Invention
The application provides a positioning system and a positioning method for abnormal signals of a chip, which can quickly position the abnormal signals in the chip.
In a first aspect, an embodiment of the present application provides a system for locating a chip abnormal signal, including: the device comprises a chip to be tested, an editable logic device and a logic analyzer;
the chip to be tested is based on an internally arranged parallel-serial signal converter, serial sampling is carried out on a preset number of parallel signals according to a clock signal and a preset sampling frequency, and at least one serial signal obtained by serial sampling and the clock signal are output from an output port of the chip to be tested in a one-to-one correspondence mode;
the editable logic device is in communication connection with the output port of the chip to be tested and the logic analyzer, and is configured to receive the at least one serial signal and the clock signal output by the output port, restore the at least one serial signal into the parallel signals of the preset number according to the clock signal and the sampling frequency, and output the restored parallel signals to the logic analyzer;
and the logic analyzer is used for positioning the abnormal signals of the received parallel signals.
In a possible design, when performing the serial sampling of a preset number of parallel signals according to a preset sampling frequency according to a clock signal, the parallel-to-serial signal converter specifically includes:
determining at least one parallel signal corresponding to each serial signal required to be output;
and for each serial signal required to be output, carrying out serial sampling on at least one parallel signal corresponding to the serial signal required to be output according to a clock signal and a preset sampling frequency to obtain the serial signal.
In a possible design, the serially sampling at least one parallel signal corresponding to the serial signal according to a clock signal at a preset sampling frequency includes:
if the number of the parallel signals corresponding to the serial signal to be output is one, outputting the parallel signal as the serial signal;
if the number of the parallel signals corresponding to the serial signal to be output is more than two, sequencing the more than two parallel signals, sequentially and circularly sampling the more than two parallel signals according to the sequencing and the sampling frequency, and serially connecting the signals obtained by sampling into one serial signal.
In a possible design, when the programmable logic device performs the restoring of the at least one serial signal into the preset number of parallel signals according to the clock signal and the sampling frequency, the method specifically includes:
for each of the received at least one serial signal, performing:
determining the number of parallel signals corresponding to the serial signals;
if the number is one, determining the serial signal as a corresponding parallel signal;
if the number is more than two, extracting a signal segment corresponding to each of the more than two parallel signals from the serial signal according to the clock signal, the sampling frequency and the sampling sequence of the more than two parallel signals, and generating a corresponding new parallel signal according to the extracted signal segment.
In one possible design, the generating a corresponding new parallel signal from the extracted signal segments includes:
and aiming at each parallel signal in the more than two parallel signals, sequencing the signal sections corresponding to the parallel signals according to the time sequence to obtain a new parallel signal corresponding to the parallel signal.
In one possible design, the generating a corresponding new parallel signal from the extracted signal segments includes:
determining a signal period of the parallel signal for each of the two or more parallel signals; determining the position of each signal segment corresponding to the parallel signal in a signal period; each signal segment is placed within a signal period according to its position on the signal period, resulting in a new parallel signal with a complete signal period.
In one possible design, the number of serial signals obtained by serial sampling is one;
and/or the presence of a gas in the gas,
the editable logic device is an FPGA;
and/or the presence of a gas in the gas,
the sampling frequency of the clock signal is 27 MHZ.
In a second aspect, an embodiment of the present application provides a method for positioning an abnormal chip signal, where the method is applied to a system for positioning an abnormal chip signal to be detected, and the method includes:
based on a parallel-serial signal converter arranged in the chip to be tested, serial sampling is carried out on a preset number of parallel signals according to a clock signal and a preset sampling frequency, and at least one serial signal obtained by serial sampling and the clock signal are output from an output port of the chip to be tested in a one-to-one correspondence manner;
receiving the at least one serial signal and the clock signal output by the output port by using the editable logic device, restoring the at least one serial signal into the parallel signals with the preset number according to the clock signal and the sampling frequency, and outputting the restored parallel signals to the logic analyzer;
and positioning the abnormal signals of the received parallel signals by using the logic analyzer.
In a possible design, when performing the serial sampling of a preset number of parallel signals according to a preset sampling frequency according to a clock signal, the parallel-to-serial signal converter specifically includes:
determining at least one parallel signal corresponding to each serial signal required to be output;
and for each serial signal required to be output, carrying out serial sampling on at least one parallel signal corresponding to the serial signal required to be output according to a clock signal and a preset sampling frequency to obtain the serial signal.
In a possible design, when the chip to be tested is used to perform serial sampling on a preset number of parallel signals according to a clock signal and a preset sampling frequency, the method specifically includes:
sequencing the preset number of parallel signals;
and sampling all the parallel signals in sequence and in a circulating mode according to the sequence and the sampling frequency, and connecting the sampled signals in series to form a serial signal.
In a possible design, the serially sampling at least one parallel signal corresponding to the serial signal according to a clock signal at a preset sampling frequency includes:
if the number of the parallel signals corresponding to the serial signal to be output is one, outputting the parallel signal as the serial signal;
if the number of the parallel signals corresponding to the serial signal to be output is more than two, sequencing the more than two parallel signals, sequentially and circularly sampling the more than two parallel signals according to the sequencing and the sampling frequency, and serially connecting the signals obtained by sampling into one serial signal.
Firstly, a positioning system consisting of a chip to be tested, an editable logic device and a logic analyzer is built, then serial sampling is carried out on a preset number of parallel signals according to a clock signal and a preset sampling frequency on the basis of a parallel-serial signal converter arranged in the chip to be tested, and at least one serial signal and the clock signal obtained by the serial sampling are output from an output port of the chip to be tested in a one-to-one correspondence manner; secondly, receiving at least one serial signal and a clock signal output by an output port by using an editable logic device, restoring the at least one serial signal into parallel signals with preset quantity according to the clock signal and sampling frequency, and outputting the restored parallel signals to a logic analyzer; and finally, positioning the abnormal signals of the received parallel signals by using a logic analyzer.
Therefore, the positioning system and the positioning method for the chip abnormal signal provided by the invention can quickly position the abnormal signal in the chip to be detected.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic diagram of a system for locating a chip abnormal signal according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a method for locating a chip abnormal signal according to an embodiment of the present invention.
Detailed Description
The present application will be described in detail below with reference to the drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In the description of the embodiments of the present application, the terms "first", "second", and the like, unless expressly specified or limited otherwise, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance; the term "plurality" means two or more unless specified or indicated otherwise; the terms "connected," "fixed," and the like are to be construed broadly and may, for example, be fixedly connected, detachably connected, integrally connected, or electrically connected; may be directly connected or indirectly connected through an intermediate. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In the description of the present application, it should be understood that the terms "upper" and "lower" used in the description of the embodiments of the present application are used in a descriptive sense only and not for purposes of limitation. In addition, in this context, it will also be understood that when an element is referred to as being "on" or "under" another element, it can be directly on "or" under "the other element or be indirectly on" or "under" the other element via an intermediate element.
As described above, in the prior art, fewer output ports are reserved for debugging the chip, and the number of the output ports is usually less than the number of signals to be analyzed, so that in the debugging process, the output signals corresponding to the output ports need to be frequently switched to find the abnormal signals, and thus a large amount of time is required to locate the abnormal signals.
In order to solve the technical problem, it is considered that a plurality of parallel signals are converted into serial signals so as to transmit the plurality of signals to the logic analyzer at the same time, thereby realizing the rapid positioning of the abnormal signals.
As shown in fig. 1, an embodiment of the present invention provides a system for locating a chip abnormal signal, where the system includes: the device comprises a chip to be tested, an editable logic device and a logic analyzer;
the chip to be tested is based on an internally arranged parallel-serial signal converter, serial sampling is carried out on a preset number of parallel signals according to a clock signal and a preset sampling frequency, and at least one serial signal and the clock signal obtained by serial sampling are output from the output port of the chip to be tested in a one-to-one correspondence mode;
the editable logic device is in communication connection with the output port of the chip to be tested and the logic analyzer and is used for receiving at least one serial signal and a clock signal output by the output port, restoring the at least one serial signal into parallel signals with preset quantity according to the clock signal and sampling frequency and outputting the restored parallel signals to the logic analyzer;
and the logic analyzer is used for positioning the abnormal signals of the received parallel signals.
In the embodiment, a positioning system composed of a chip to be tested, an editable logic device and a logic analyzer is firstly established, then based on a parallel-serial signal converter arranged in the chip to be tested, serial sampling is carried out on a preset number of parallel signals according to a clock signal and a preset sampling frequency, and at least one serial signal and the clock signal obtained by the serial sampling are output from an output port of the chip to be tested in a one-to-one correspondence manner; secondly, receiving at least one serial signal and a clock signal output by an output port by using an editable logic device, restoring the at least one serial signal into parallel signals with preset quantity according to the clock signal and sampling frequency, and outputting the restored parallel signals to a logic analyzer; and finally, positioning the abnormal signals of the received parallel signals by using a logic analyzer. The positioning system for the chip abnormal signal provided by the embodiment can quickly position the abnormal signal in the chip to be detected.
The following describes the respective implementations of the components shown in fig. 1.
First, a chip will be explained.
A chip is an integrated circuit that is made up of a large number of transistors. As mentioned above, the functions of the chip are more and more, but the chip size is less and less, so in order to reduce the number of the general output ports of the chip, save the chip volume, and reduce the production cost and the production cycle of the chip, in an embodiment, a parallel-serial signal converter may be disposed inside the chip, and the parallel-serial signal converter is used to perform serial sampling on a preset number of parallel signals according to a preset sampling frequency according to a clock signal, which specifically includes:
determining at least one parallel signal corresponding to each serial signal required to be output;
if the number of the parallel signals corresponding to the serial signal to be output is one, outputting the parallel signal as the serial signal; this is suitable for use when there are more chip output ports or fewer signals to be detected.
If the number of the parallel signals corresponding to the serial signal to be output is more than two, sequencing the more than two parallel signals, sequentially and circularly sampling the more than two parallel signals according to the sequencing and the sampling frequency, and serially connecting the signals obtained by sampling into one serial signal. This situation is applicable to the case where there are fewer chip output ports and more signals to be detected.
It should be noted that each parallel-serial signal converter can only perform serial sampling on a preset parallel signal, and therefore, when there are a plurality of serial signals, the same number of parallel-serial signal converters needs to be matched.
The following describes a process of serial sampling a preset number of parallel signals by a parallel-to-serial signal converter in a specific embodiment:
setting the number of the parallel signals to be N, and sequencing the N parallel signals according to 1, 2 and 3 … … N, wherein N times of sampling is a cycle, and N is greater than 1;
setting the signal period of the clock signal as T, and taking the sampling frequency f as 1/T, then iN a section of sampling interval, sequentially collecting the 1 st parallel signal at the corresponding moment on the 1 st, N +1, 2N +1, 3N +1 … … iN +1 rising edges of another clock signal; sequentially collecting the 2 nd parallel signal at corresponding time on the 2 nd, N +2, 2N +2 and 3N +2 … … iN +2 nd rising edges of the clock signal; by analogy, the Nth, 2N, 3N and 4N … … iN rising edges of the clock signal sequentially acquire the Nth parallel signal at the corresponding moment, and sequentially and circularly sample each parallel signal to finish the conversion of the N parallel signals into a serial signal; wherein i is a natural number greater than 1.
After the signal period of the clock signal is determined, a user may determine a sampling frequency according to test requirements, for example, the sampling frequency f may be 1/T, or the sampling frequency f may also be 1/2T, which is not limited in this application; in addition, signals can be acquired at the rising edge and the falling edge of the clock signal, and the signals can be acquired according to a certain rule, so that the method is not particularly limited in the application.
Next, a programmable logic device will be explained.
The programmable logic device is a general-purpose integrated circuit, and the logic function of the programmable logic device can be determined according to the programming of a user on the device, so that in order to obtain parallel signals, the programmable logic device can be used for converting serial signals into new parallel models.
In an embodiment, when the programmable logic device performs restoring at least one serial signal to a preset number of parallel signals according to a clock signal and a sampling frequency, the method specifically includes:
for each of the received at least one serial signal, performing:
determining the number of parallel signals corresponding to the serial signals;
if the number is one, determining the serial signal as a corresponding parallel signal;
if the number is two or more, a signal segment corresponding to each of the two or more parallel signals is extracted from the serial signal according to the clock signal, the sampling frequency, and the sampling order of the two or more parallel signals, and a corresponding new parallel signal is generated from the extracted signal segment.
In this case, generating a corresponding new parallel signal from the extracted signal segments comprises: and aiming at each parallel signal in the more than two parallel signals, sequencing the signal sections corresponding to the parallel signals according to the time sequence to obtain a new parallel signal corresponding to the parallel signal.
The following describes a specific process of converting a serial signal into a new parallel signal in this embodiment by using a specific embodiment:
determining the number of parallel signals corresponding to a certain serial signal to be N, wherein the serial signal comprises 80N signal segments;
then according to the clock signal and the sampling frequency of the chip to be tested, taking the 1 st, N +1 st, 2N +1 st, 3N +1 st 1 … … 79N +1 st signal segment of the 80N signal segments as the 1 st new parallel signal according to the sampling sequence of the N parallel signals; taking the 2 nd, N +2, 2N +2, 3N +2 … … 79N +2 signal segments in the 80N signal segments as the 2 nd new parallel signal; taking the 3 rd, N +3, 2N +3, 3N +3 … … 79N +3 signal segments in the 80N signal segments as the 3 rd new parallel signal; and by analogy, the nth, 2N, 3N, 4N … … 80 nth signal segments in the 80N signal segments are used as nth new parallel signals, so that the serial signals can be converted into N new parallel signals for subsequent positioning of abnormal signals.
In addition, generating a corresponding new parallel signal according to the extracted signal segment may further include, in some embodiments:
determining a signal period of the parallel signal for each of the two or more parallel signals; determining the position of each signal segment corresponding to the parallel signal in a signal period; each signal segment is placed within a signal period according to its position on the signal period, resulting in a new parallel signal with a complete signal period.
In order to save the output port of the chip to the maximum extent and reduce the size of the chip, in some embodiments, the number of serial signals obtained by serial sampling is one;
in addition, to improve the functionality and versatility of the system, in some embodiments, the editable logic device is an FPGA; the sampling frequency of the clock signal is 27 MHZ. The FPGA can not only solve the defect of a customized circuit, but also overcome the defect of limited gate circuits of the original programmable device, and the system is simple and the manufacturing cost is low by using the FPGA; and 27MHZ is a common sampling frequency with which no further development costs need to be invested in the clock signal. It should be noted that, it is preferable to select the sampling frequency of the FPGA and the 27MHZ, in other embodiments, the editable logic device may also select the CPLD, and the sampling frequency may also be other frequencies, which is not limited in this application.
Finally, the logic analyzer will be explained.
The logic analyzer is an instrument for analyzing the logic relation of a digital system, is an instrument for collecting and displaying digital signals from test equipment by using a clock, and is mainly used for timing judgment. According to the method, the logic analyzer is used for receiving the parallel signals transmitted by the editable logic device, then the received signals are compared with the preset threshold level, and finally the abnormal signals are located according to the comparison result, so that the specific implementation process of the logic analyzer is not repeated in the method.
As shown in fig. 2, an embodiment of the present invention further provides a method for positioning an abnormal chip signal, where the method is applied to the system for positioning an abnormal chip signal, and the method includes:
step 100: based on a parallel-serial signal converter arranged in a chip to be tested, serial sampling is carried out on a preset number of parallel signals according to a clock signal and a preset sampling frequency, and at least one serial signal and the clock signal obtained by serial sampling are output from an output port of the chip to be tested in a one-to-one correspondence manner;
step 102: receiving at least one serial signal and a clock signal output by an output port by using an editable logic device, restoring the at least one serial signal into parallel signals with preset number according to the clock signal and sampling frequency, and outputting the restored parallel signals to a logic analyzer;
step 104: and carrying out abnormal signal positioning on the received parallel signals by using a logic analyzer.
In the embodiment, firstly, based on a parallel-serial signal converter arranged in a chip to be tested, serial sampling is carried out on a preset number of parallel signals according to a clock signal and a preset sampling frequency, and at least one serial signal obtained by the serial sampling and the clock signal are output from an output port of the chip to be tested in a one-to-one correspondence manner; then, receiving at least one serial signal and a clock signal output by an output port by using an editable logic device, restoring the at least one serial signal into parallel signals with preset quantity according to the clock signal and sampling frequency, and outputting the restored parallel signals to a logic analyzer; and finally, positioning the abnormal signals of the received parallel signals by using a logic analyzer. The chip abnormal signal positioning method provided by the embodiment can be used for quickly positioning the abnormal signal in the chip to be detected.
In one embodiment, for step 100, when performing serial sampling on a preset number of parallel signals according to a preset sampling frequency according to a clock signal by using a parallel-to-serial signal converter, the method specifically includes:
step A1: determining at least one parallel signal corresponding to each serial signal required to be output;
step A2: and for each serial signal required to be output, carrying out serial sampling on at least one parallel signal corresponding to the serial signal required to be output according to a clock signal and a preset sampling frequency to obtain the serial signal.
With respect to step a2, in one embodiment, the method comprises:
if the number of the parallel signals corresponding to the serial signal to be output is one, outputting the parallel signal as the serial signal;
if the number of the parallel signals corresponding to the serial signal to be output is more than two, sequencing the more than two parallel signals, sequentially and circularly sampling the more than two parallel signals according to the sequencing and the sampling frequency, and serially connecting the signals obtained by sampling into one serial signal.
Since the chip abnormal signal positioning method is based on the same concept as the positioning system embodiment of the present invention, specific contents can be referred to the description in the positioning system embodiment of the present invention, and are not described herein again.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an …" does not exclude the presence of other similar elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A positioning system for chip abnormal signals is characterized by comprising a chip to be tested, an editable logic device and a logic analyzer;
the chip to be tested is based on an internally arranged parallel-serial signal converter, serial sampling is carried out on a preset number of parallel signals according to a clock signal and a preset sampling frequency, and at least one serial signal obtained by serial sampling and the clock signal are output from an output port of the chip to be tested in a one-to-one correspondence mode;
the editable logic device is in communication connection with the output port of the chip to be tested and the logic analyzer, and is configured to receive the at least one serial signal and the clock signal output by the output port, restore the at least one serial signal into the parallel signals of the preset number according to the clock signal and the sampling frequency, and output the restored parallel signals to the logic analyzer;
and the logic analyzer is used for positioning the abnormal signals of the received parallel signals.
2. The system according to claim 1, wherein the parallel-to-serial signal converter, when performing the serial sampling of a preset number of parallel signals according to a preset sampling frequency according to a clock signal, specifically comprises:
determining at least one parallel signal corresponding to each serial signal required to be output;
and for each serial signal required to be output, carrying out serial sampling on at least one parallel signal corresponding to the serial signal required to be output according to a clock signal and a preset sampling frequency to obtain the serial signal.
3. The system according to claim 2, wherein the serially sampling the at least one parallel signal corresponding to the serial signal according to the clock signal and the preset sampling frequency comprises:
if the number of the parallel signals corresponding to the serial signal to be output is one, outputting the parallel signal as the serial signal;
if the number of the parallel signals corresponding to the serial signal to be output is more than two, sequencing the more than two parallel signals, sequentially and circularly sampling the more than two parallel signals according to the sequencing and the sampling frequency, and serially connecting the signals obtained by sampling into one serial signal.
4. The system according to claim 3, wherein the programmable logic device, when executing the recovering of the at least one serial signal into the preset number of parallel signals according to the clock signal and the sampling frequency, specifically comprises:
for each of the received at least one serial signal, performing:
determining the number of parallel signals corresponding to the serial signals;
if the number is one, determining the serial signal as a corresponding parallel signal;
if the number is more than two, extracting a signal segment corresponding to each of the more than two parallel signals from the serial signal according to the clock signal, the sampling frequency and the sampling sequence of the more than two parallel signals, and generating a corresponding new parallel signal according to the extracted signal segment.
5. The system of claim 4, wherein the generating of the corresponding new parallel signal from the extracted signal segments comprises:
and aiming at each parallel signal in the more than two parallel signals, sequencing the signal sections corresponding to the parallel signals according to the time sequence to obtain a new parallel signal corresponding to the parallel signal.
6. The system of claim 4, wherein the generating of the corresponding new parallel signal from the extracted signal segments comprises:
determining a signal period of the parallel signal for each of the two or more parallel signals; determining the position of each signal segment corresponding to the parallel signal in a signal period; each signal segment is placed within a signal period according to its position on the signal period, resulting in a new parallel signal with a complete signal period.
7. The system according to any one of claims 1-6,
the number of the serial signals obtained by the serial sampling is one;
and/or the presence of a gas in the gas,
the editable logic device is an FPGA;
and/or the presence of a gas in the gas,
the sampling frequency of the clock signal is 27 MHZ.
8. A method for positioning abnormal signals of a chip, the method being applied to the system for positioning abnormal signals of a chip to be tested according to any one of claims 1 to 7, wherein:
based on a parallel-serial signal converter arranged in the chip to be tested, serial sampling is carried out on a preset number of parallel signals according to a clock signal and a preset sampling frequency, and at least one serial signal obtained by serial sampling and the clock signal are output from an output port of the chip to be tested in a one-to-one correspondence manner;
receiving the at least one serial signal and the clock signal output by the output port by using the editable logic device, restoring the at least one serial signal into the parallel signals with the preset number according to the clock signal and the sampling frequency, and outputting the restored parallel signals to the logic analyzer;
and positioning the abnormal signals of the received parallel signals by using the logic analyzer.
9. The method according to claim 8, wherein the performing, by the parallel-to-serial converter, the serial sampling of the parallel signals of the preset number according to the clock signal and the preset sampling frequency specifically includes:
determining at least one parallel signal corresponding to each serial signal required to be output;
and for each serial signal required to be output, carrying out serial sampling on at least one parallel signal corresponding to the serial signal required to be output according to a clock signal and a preset sampling frequency to obtain the serial signal.
10. The method of claim 9, wherein the serially sampling at least one parallel signal corresponding to the serial signal according to the clock signal and the preset sampling frequency comprises:
if the number of the parallel signals corresponding to the serial signal to be output is one, outputting the parallel signal as the serial signal;
if the number of the parallel signals corresponding to the serial signal to be output is more than two, sequencing the more than two parallel signals, sequentially and circularly sampling the more than two parallel signals according to the sequencing and the sampling frequency, and serially connecting the signals obtained by sampling into one serial signal.
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