CN101191818A - Chip test method, system and apparatus - Google Patents
Chip test method, system and apparatus Download PDFInfo
- Publication number
- CN101191818A CN101191818A CNA2007101793231A CN200710179323A CN101191818A CN 101191818 A CN101191818 A CN 101191818A CN A2007101793231 A CNA2007101793231 A CN A2007101793231A CN 200710179323 A CN200710179323 A CN 200710179323A CN 101191818 A CN101191818 A CN 101191818A
- Authority
- CN
- China
- Prior art keywords
- test
- functional module
- tested
- chip
- testing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010998 test method Methods 0.000 title 1
- 238000012360 testing method Methods 0.000 claims abstract description 227
- 238000000034 method Methods 0.000 claims abstract description 23
- 239000004973 liquid crystal related substance Substances 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 7
- 238000012795 verification Methods 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000013522 software testing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a method for testing chips which comprises the following steps of: preestimating the possible errors in a functional module to be tested of a chip to be tested; setting the test logic for testing the errors and arranging the test logic in a test device arranged outside the chip to be tested. The method also comprises the following steps that: the test device is used to test the functional module by means of the test logic and converts the test result into one of the two states which respectively indicate that errors exist in the functional module and that errors do not exist in the functional module. The invention also discloses a chip testing system and the test device. With the invention, the test logic can be changed according to new test proposal, thereby increasing the test speed.
Description
Technical Field
The present invention relates to testing technologies, and in particular, to a method and a system for testing a chip, and a testing apparatus.
Background
Currently, verification testing and debugging of a chip takes more than 70% of the time in the whole development process of the chip. Generally, there are two main methods for testing chips. The first is software testing, i.e. various test stimuli are generated for the chip under test by computer programming. Therefore, the functions of the chip to be tested can be verified by comparing the results generated by various test excitations with the results generated by the expected chip to be tested. The second is hardware test, that is, the actual working environment of the chip to be tested is approximated by building a hardware test platform. Thus, the function of the chip can be verified more truly. The second method of the prior art is described below for verifying and testing a chip under test.
Referring to fig. 1, fig. 1 is a diagram illustrating a structure of a chip to be tested in the prior art. As shown in fig. 1, the structure mainly includes: the device comprises a chip to be tested 101, an auxiliary verification daughter board 102 and a signal analyzer 103.
The chip 101 to be tested mainly includes a functional module 1011 to be tested, a test port 1012 and a functional port 1013. Usually, there is at least one functional module 1011 to be tested on the chip 101 to be tested. For simplicity, the number of functional modules 1011 to be tested is assumed to be one. In fig. 1, the testing module 1014 tests the chip 101 under test, that is, tests the functional module 1011 to be tested on the chip 101 under test. In some exceptional cases, the signal generated by the functional module 1011 to be tested is complex, and it cannot be easily and intuitively confirmed whether an error occurs by observing from the signal analyzer 103, which requires adding some extra test logic inside the chip 101 to be tested to analyze the signal generated by the functional module 1011 to be tested, and then sending the signal which passes through the test logic and is easy to observe and analyze to the signal analyzer 103. Thus, the chip under test should also include a test module 1014 inside.
Normally, the test module 1014 cannot test the functional module 1011 on the chip 101 under test alone, which requires the auxiliary verification daughter board 102 to assist in completing the test.
The auxiliary verification daughter board 102 is connected to the functional module 1011 to be tested through the functional port 1013 to assist the functional module 1011 to be tested to execute its corresponding function. The test module 1014 tests a function to be performed by the functional module 1011 and connects a test signal to the signal analyzer 103 through the test port 1012.
In general, the signal analyzer 103 may be an oscilloscope or a logic analyzer. The signal analyzer 103 is used to observe and analyze the test signal generated by the test module 1014. Thus, it is possible to determine whether there is an error in the functional module 1011 to be tested by the display result on the signal analyzer 103. Moreover, when the functional module 1011 to be tested generates an error, the signal analyzer 103 may also display the error to deduce the cause of the error generated by the functional module 1011 to be tested, and debug the functional module 1011 to be tested, so as to clear the error generated by the functional module 1011 to be tested.
Therefore, according to the scheme, the functional module to be tested in the chip to be tested can be tested through the test module in the chip to be tested, the generated test signal is observed and analyzed through the logic analyzer or the oscilloscope, the functional module to be tested is debugged, and the error source is found out. However, this method requires a logic module or a test module with function test to be added to the chip, which increases the chip area, and the test module needs to be fixed first when performing the test function. Thus, the test logic cannot be modified according to a new debugging scheme either during the development of the chip or after the chip is manufactured, thereby affecting the test speed.
Disclosure of Invention
Embodiments of the present invention provide a method, a system, and a device for testing a chip, which can modify a test logic according to a new debug scheme, thereby increasing a test speed.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
a chip testing method includes predicting errors which can occur in a functional module to be tested on a chip to be tested; setting a test logic for testing the error, and setting the test logic in test equipment positioned outside a chip to be tested; the method comprises the following steps:
the test equipment tests the functional module through the test logic;
and converting the obtained test result into one of two opposite states, wherein the two opposite states respectively indicate whether the functional module has errors.
Preferably, the method further comprises: and displaying one of the states through a Light Emitting Diode (LED) display lamp or a Liquid Crystal Display (LCD).
Preferably, the one of the states is displayed by the LED display lamp as:
when one of the states indicates that the functional module has an error, an LED display lamp is turned on; otherwise, the LED display lamp is turned off.
Preferably, the method further comprises: and when one of the states indicates that the functional module has an error, debugging the functional module with the error.
A system for testing a chip comprises a chip to be tested and test equipment; wherein,
the chip to be tested comprises a functional module to be tested;
the test equipment is provided with test logic for testing a functional module to be tested on an external chip to be tested, the test logic is used for testing errors which can occur in the functional module and converting a test result into one of two opposite states, and the two opposite states respectively indicate whether the functional module has errors or not.
Preferably, the system further comprises: a display device, wherein the display device is disposed on the test device or is independent of the test device;
the display device is used for displaying one of the states.
Preferably, the system further comprises:
and the debugging equipment is used for debugging the functional module with the error when one of the states displayed by the display equipment indicates that the functional module has the error.
A test apparatus, comprising: a receiving unit and a testing unit; wherein,
the receiving unit is used for receiving a signal of a functional module to be tested in a chip to be tested outside the testing equipment and sending the signal to the testing unit;
the test unit is used for testing the functional module to be tested through the test logic arranged in the test unit, and converting a test result into one of two opposite states, wherein the two opposite states respectively indicate whether the functional module has errors.
Preferably, the apparatus further comprises: a display unit;
the display unit is used for displaying one of the states.
Preferably, the display unit is a Light Emitting Diode (LED) display lamp or a Liquid Crystal Display (LCD).
Preferably, the display unit is an LED display lamp, and the LED display lamp is turned on when one of the states indicates that the functional module has an error; otherwise, the lamp goes out.
Preferably, the test unit is implemented by a programmable logic device.
According to the technical scheme, the method, the system and the equipment for testing the chip have the following advantages:
firstly, the method comprises the following steps: in the invention, the test equipment can be a programmable logic device such as a field programmable gate array FPGA; or for a complex programmable logic device CPLD. Thus, the cost of the test device can be reduced to mass-produce the test device. In addition, the test equipment is arranged outside the chip to be tested, and the test logic can be modified or increased or decreased according to the debugging scheme at any time, so that the test function of the test equipment can be conveniently and flexibly realized, and the test speed is improved.
Secondly, the method comprises the following steps: according to the invention, the test logic is written into the test equipment arranged outside the chip to be tested, so that a test module in the chip to be tested in the prior art can be omitted, the area of the chip to be tested is reduced, and the cost of the core piece is further reduced.
Thirdly, the method comprises the following steps: the invention can allow the chip to be tested under the condition of no oscilloscope or logic analyzer, thereby reducing the cost for testing the chip to be tested.
Drawings
FIG. 1 is a diagram illustrating the structure of a test chip in the prior art;
FIG. 2 is a flowchart of a chip testing method according to an embodiment of the present invention;
FIG. 3 is a diagram of a system for testing chips according to an embodiment of the present invention;
FIG. 4 is a block diagram of a test apparatus according to an embodiment of the present invention;
FIG. 5 is a block diagram of a test apparatus for different errors according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and examples.
Different from the prior art, the embodiment of the invention firstly estimates the error which can occur in the functional module to be tested on the chip to be tested; and setting a test logic for testing the error, and setting the test logic in test equipment positioned outside the chip to be tested. Thus, the method for testing the chip to be tested in the embodiment of the invention mainly comprises the following steps: the test equipment tests the functional module through the test logic; and converting the obtained test result into one of two opposite states, wherein the two opposite states respectively indicate whether the functional module has errors or not, so that the test logic can be modified according to a new debugging scheme, and the test speed is improved.
Referring to fig. 2, fig. 2 is a flowchart of a chip testing method according to an embodiment of the present invention. In fig. 2, the process includes:
In this step, there may be a plurality of functional modules to be tested, and in this embodiment, the description is simple, and it is assumed that there is one functional module to be tested.
The test port is used for connecting the functional module to be tested and the test equipment and sending the signal generated by the corresponding functional module to be tested to the test equipment.
The test device in this embodiment may be implemented by a programmable logic device such as an FPGA, a CPLD, or the like. In this step, the testing of the functional module to be tested by the testing device specifically includes: the test equipment tests the predicted error which may be generated by the functional module to be tested through the test logic which is not arranged in the test equipment.
If the predicted possible error of the functional module to be tested is error a, the test logic in the test equipment in this step is the test logic for correspondingly testing the error a. That is, in this step, the test equipment tests the functional module to be tested through the test logic corresponding to the error a.
In this step, two opposite states respectively indicate whether the functional module has an error. For the test logic of the test error A, if one of two opposite states of the test result conversion indicates that the functional module has an error, the functional module to be tested has the error A; otherwise, the functional module to be tested may have no errors, or the error that occurs is not error a.
And then, when the error A occurs, debugging the functional module with the error A.
Generally, the error of the function module to be tested may be estimated to be multiple. Thus, when the error a is removed by debugging, the operation of testing other errors of the functional module to be tested can be continuously executed. Of course, the debugging may be performed after all the errors of the functional module to be tested are tested.
In this embodiment, if more than 1 functional module to be tested in the chip to be tested and the same error may occur in each functional module, in order to increase the testing speed, a plurality of testing logics corresponding to the same error of different functional modules may be simultaneously set in the testing equipment. Similarly, in this embodiment, if the estimated error that may be generated by the functional module to be tested is more than 1, in order to increase the testing speed, a plurality of test logics respectively corresponding to different errors may be simultaneously set in the testing apparatus for the functional module. This requires a case specific analysis.
In order to facilitate the user to intuitively find the error source, the present embodiment may Display one of the above states through a Light-Emitting Diode (LED) Display lamp or a Liquid Crystal Display (LCD).
If one of the states is displayed through the LED display lamp, the LED display lamp is turned on when the one of the states indicates that the functional module to be tested has errors, the user can further debug the functional module with errors until the generated errors are removed through debugging, otherwise, the LED display lamp is turned off, and the functional module to be tested is determined not to have errors corresponding to the test logic.
The system for testing a chip provided by the embodiment of the invention is described below.
Referring to fig. 3, fig. 3 is a system diagram of chip testing according to an embodiment of the present invention. As shown in fig. 3, the system mainly includes: a chip 301 to be tested and a test device 302.
The chip 301 to be tested includes a functional module 3011 to be tested.
In application, the chip 301 under test may further include a test port 3012 for connecting the test equipment 302.
The test equipment 302 is provided with a test logic for testing the functional module to be tested 3011 on the external chip to be tested, wherein the test logic is configured to test a possible error of the functional module to be tested and convert a test result into one of two opposite states, where the two opposite states respectively indicate whether the functional module has an error.
The system further comprises: a display device 303.
Wherein the display device 303 is disposed on the test device 302 or is independent of the test device 302; it is assumed in the present embodiment that the display device 303 is independent of the test device 302.
The display device 303 is used to display one of two opposite states to which the test device is switched.
The system may also include a commissioning device 304.
The debugging device 304 is configured to debug the functional module with an error when one of the states displayed by the display device indicates that the functional module to be tested 3011 has an error.
In this embodiment, the test device 302 may be implemented by a programmable logic device, such as an FPGA, a CPLD, or the like.
Structural composition of the test apparatus 302 referring to fig. 4, fig. 4 is a diagram of a test apparatus according to an embodiment of the present invention. As shown in fig. 4, the apparatus includes: a receiving unit 401 and a testing unit 402.
The receiving unit 401 is configured to receive a signal of a functional module to be tested in a chip to be tested disposed outside the testing apparatus, and send the signal to the testing unit 402.
The test unit 402 is configured to test a functional module to be tested in a chip to be tested through a test logic disposed in the test unit, and convert a test result into one of two opposite states, where the two opposite states respectively indicate whether the functional module has an error.
The apparatus further comprises: a display unit 403.
The display unit 403 is an LED display lamp or an LCD display screen;
in this embodiment, the display unit 403 is an LED display lamp. When one of the states indicates that the functional module has an error, the LED display lamp is turned on; otherwise, the LED display lamp is turned off.
In this embodiment, if the estimated error that may be generated by the functional module to be tested is more than 1, in order to increase the testing speed, more than 1 test logic subunit corresponding to different errors may also be simultaneously set in the testing apparatus for the functional module, and the specific structure is shown in fig. 5.
In addition, if the number of functional modules to be tested in the chip to be tested is more than 1 and the same error may occur in each functional module, in order to increase the testing speed, a plurality of testing logics corresponding to the same error of different functional modules may be simultaneously set in the testing equipment.
As can be seen from the above embodiments, the test device according to the embodiments of the present invention can be implemented by a programmable logic device, such as an FPGA, a CPLD, or the like, so that the test device has low cost and can be mass-produced. In addition, the test equipment is arranged outside the chip to be tested, and the test logic can be modified or increased or decreased according to the requirements at any time, so that the test function of the test equipment can be conveniently and flexibly realized, and the test speed is improved. In addition, the embodiment of the invention writes the test logic into the test equipment arranged outside the chip to be tested, so that the test equipment is arranged outside the chip to be tested, a test module in the chip in the prior art can be omitted, the area of the chip to be tested is reduced, and the cost of the core piece is reduced. In addition, the invention can allow the chip to be tested under the condition of no oscilloscope or logic analyzer, thereby reducing the cost for testing the chip to be tested.
It should be understood that the above-mentioned embodiments are merely preferred embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (12)
1. A method for testing a chip is characterized in that errors which can occur in a functional module to be tested on the chip to be tested are estimated; setting a test logic for testing the error, and setting the test logic in test equipment positioned outside a chip to be tested;
the method comprises the following steps:
the test equipment tests the functional module through the test logic;
and converting the obtained test result into one of two opposite states, wherein the two opposite states respectively indicate whether the functional module has errors.
2. The method of claim 1, further comprising: and displaying one of the states through a Light Emitting Diode (LED) display lamp or a Liquid Crystal Display (LCD).
3. The method of claim 2, wherein the one of the statuses is displayed by an LED display lamp as:
when one of the states indicates that the functional module has an error, an LED display lamp is turned on; otherwise, the LED display lamp is turned off.
4. A method according to any of claims 1-3, characterized in that the method further comprises: and when one of the states indicates that the functional module has an error, debugging the functional module with the error.
5. A system for testing a chip is characterized by comprising a chip to be tested and testing equipment; wherein,
the chip to be tested comprises a functional module to be tested;
the test equipment is provided with test logic for testing a functional module to be tested on an external chip to be tested, the test logic is used for testing errors which can occur in the functional module and converting a test result into one of two opposite states, and the two opposite states respectively indicate whether the functional module has errors or not.
6. The system of claim 5, further comprising: a display device, wherein the display device is disposed on the test device or is independent of the test device;
the display device is used for displaying one of the states.
7. The system of claim 6, further comprising:
and the debugging equipment is used for debugging the functional module with the error when one of the states displayed by the display equipment indicates that the functional module has the error.
8. A test apparatus, characterized in that the apparatus comprises: a receiving unit and a testing unit; wherein,
the receiving unit is used for receiving a signal of a functional module to be tested in a chip to be tested outside the testing equipment and sending the signal to the testing unit;
the test unit is used for testing the functional module to be tested through the test logic arranged in the test unit, and converting a test result into one of two opposite states, wherein the two opposite states respectively indicate whether the functional module has errors.
9. The apparatus of claim 8, further comprising: a display unit;
the display unit is used for displaying one of the states.
10. The apparatus of claim 9, wherein the display unit is a Light Emitting Diode (LED) display lamp or a Liquid Crystal Display (LCD).
11. The apparatus of claim 9, wherein the display unit is an LED display light that lights up when one of the states indicates an error in the functional module; otherwise, the lamp goes out.
12. The apparatus of claim 8, wherein the test unit is implemented by a programmable logic device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101793231A CN101191818A (en) | 2007-12-12 | 2007-12-12 | Chip test method, system and apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101793231A CN101191818A (en) | 2007-12-12 | 2007-12-12 | Chip test method, system and apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101191818A true CN101191818A (en) | 2008-06-04 |
Family
ID=39486942
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007101793231A Pending CN101191818A (en) | 2007-12-12 | 2007-12-12 | Chip test method, system and apparatus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101191818A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103645435A (en) * | 2013-12-13 | 2014-03-19 | 电子科技大学 | Software module testability design method of multi-signal model programming logic device |
| CN105629153A (en) * | 2015-12-24 | 2016-06-01 | 大唐微电子技术有限公司 | Chip testing method |
| CN114384400A (en) * | 2022-01-13 | 2022-04-22 | 集睿致远(厦门)科技有限公司 | Positioning system and positioning method for chip abnormal signals |
-
2007
- 2007-12-12 CN CNA2007101793231A patent/CN101191818A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103645435A (en) * | 2013-12-13 | 2014-03-19 | 电子科技大学 | Software module testability design method of multi-signal model programming logic device |
| CN103645435B (en) * | 2013-12-13 | 2016-03-23 | 电子科技大学 | The software module design for Measurability method of multi-signal model programmable logic device (PLD) |
| CN105629153A (en) * | 2015-12-24 | 2016-06-01 | 大唐微电子技术有限公司 | Chip testing method |
| CN105629153B (en) * | 2015-12-24 | 2018-10-09 | 大唐微电子技术有限公司 | A kind of method of chip testing |
| CN114384400A (en) * | 2022-01-13 | 2022-04-22 | 集睿致远(厦门)科技有限公司 | Positioning system and positioning method for chip abnormal signals |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US12085612B2 (en) | On-chip debugging device and method | |
| CN110050441B (en) | Capturing traffic in real time for protocol debugging in case of failure | |
| CN102092477A (en) | Device and method for automatic test and fault diagnosis of plane audio integrated system | |
| CN105738792A (en) | PCBA test device and test method | |
| IES20000160A2 (en) | A Method and system for testing microprocessor-based boards in a manufacturing environment | |
| CN103376340B (en) | A kind of keyset, multi-platform serial test system and method | |
| CN103077114A (en) | Automatic testing method based on communication protocol of temperature measuring device | |
| CN114325333A (en) | High-efficiency normalized SOC (system on chip) system level verification method and device | |
| DE602007010039D1 (en) | SYSTEM AND COMPUTER PROGRAM PRODUCT FOR TESTING LOGICAL SWITCHING | |
| CN117787155B (en) | Chip testability code dynamic simulation test system and test method | |
| CN112231163A (en) | Multifunctional computer detection equipment and operation method thereof | |
| CN101191818A (en) | Chip test method, system and apparatus | |
| CN115454751A (en) | FPGA chip testing method and device and computer readable storage medium | |
| US7577876B2 (en) | Debug system for data tracking | |
| US20230184831A1 (en) | Server jtag component adaptive interconnection system and method | |
| CN1230885C (en) | Fault-telerance method and system of testing chip for boundary scanning | |
| CN116521468B (en) | FPGA online debugging method and FPGA supporting online debugging | |
| RU73093U1 (en) | SOFTWARE DIAGNOSTIC DEVICE "DOLTA" | |
| CN106226615A (en) | A kind of electronic equipment automatization test system | |
| CN113990382B (en) | System-on-chip, test method and test system | |
| JP5532134B2 (en) | Semiconductor integrated circuit device, control method thereof, and information processing device | |
| CN102645609B (en) | Joint test action group (JTAG) link circuit test device and test method of JTAG chain circuit test device | |
| CN115932544A (en) | Device and method for automatically testing power consumption of GPU chip | |
| Ng et al. | Improving efficiency of IC burn-In testing | |
| US20150039955A1 (en) | Systems and methods for Analog, Digital, Boundary Scan, and SPI Automatic Test Equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Open date: 20080604 |