CN114373725A - Chip array and electronic equipment - Google Patents
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- CN114373725A CN114373725A CN202111521527.5A CN202111521527A CN114373725A CN 114373725 A CN114373725 A CN 114373725A CN 202111521527 A CN202111521527 A CN 202111521527A CN 114373725 A CN114373725 A CN 114373725A
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- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/467—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing gases, e.g. air
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
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Abstract
The present disclosure relates to a chip array and an electronic device; the chip array includes: the power calculation board comprises a power calculation board and at least two types of chips, wherein a first type of chip in the at least two types of chips is arranged in a first area of the power calculation board, a second type of chip in the at least two types of chips is arranged in a second area of the power calculation board, and the power consumption of the first type of chip is larger than that of the second type of chip; the heat dissipation priority of the first area is greater than the heat dissipation priority of the second area. Therefore, the aging trend of the data chip can be slowed down, and the heat dissipation efficiency of the data chip is improved.
Description
Technical Field
The present disclosure relates to, but not limited to, the field of chip design technologies, and in particular, to a chip array and an electronic device.
Background
In the related art, the layout design of the data chip is generally to arrange the data chip and the device related to the data chip at the air outlet.
However, in the practical application process, the data chip designed at the air outlet not only has the heat dissipation requirement, but also can bear the heat brought by the air outlet, and then the problems that the data chip positioned at the air outlet and devices related to the data chip can be accelerated to age due to long-term high temperature and the data chip can not dissipate heat effectively exist.
In view of the above-mentioned problem of poor heat dissipation of the data chip caused by unreasonable heat dissipation layout in the related art, no effective solution has been proposed at present.
Disclosure of Invention
The present disclosure provides a chip array and an electronic device to solve the problem of poor heat dissipation of a data chip due to unreasonable heat dissipation layout in the related art.
According to a first aspect of embodiments of the present disclosure, there is provided a chip array, including: the power calculation board comprises a power calculation board and at least two types of chips, wherein a first type of chip in the at least two types of chips is arranged in a first area of the power calculation board, a second type of chip in the at least two types of chips is arranged in a second area of the power calculation board, and the power consumption of the first type of chip is larger than that of the second type of chip; the heat dissipation priority of the first area is greater than the heat dissipation priority of the second area.
In the above solution, on the force calculation plate, the first type chip in the first area is disposed on the second type chip side in the second area.
In the above scheme, on the force calculation plate, the first type chips in the first region and the second type chips in the second region are alternately arranged.
In the scheme, on the force calculation board, the second type of chips in the second area are positioned at the periphery of the first type of chips in the first area; or the first type of chips in the first area are positioned around the second type of chips in the second area.
In the above scheme, the first region and the second region are determined by performing a temperature test on the first type chip and the second type chip.
According to a second aspect of the embodiments of the present disclosure, there is provided an electronic apparatus including: the chip array and the heat dissipation device are arranged, wherein a refrigerant input end in the heat dissipation device corresponds to a first area of the chip array; the output end of the refrigerant in the heat dissipation device corresponds to the second area of the chip array.
In the above solution, under the condition that the heat dissipation device includes the heat dissipation fan, the heat dissipation fan is connected to the refrigerant input end, the refrigerant input end corresponds to the first region of the force calculation plate, and the refrigerant output end corresponds to the second region of the force calculation plate, wherein the refrigerant input end introduces cold air, the refrigerant output end discharges cold air, and the refrigerant input end and the refrigerant output end are disposed opposite to each other or in the same column.
In the scheme, the refrigerant input end is positioned at one side of the first type of chip; the refrigerant output end and the refrigerant input end are arranged oppositely and are positioned on one side of the second type chip; or the refrigerant input end is positioned at one side of the first type of chip; the refrigerant output end and the refrigerant input end are arranged in the same row.
In the above scheme, the refrigerant input end is located above the level of the first type of chip, and the refrigerant output end is located at any side of the second type of chip.
In the above scheme, under the condition that the heat dissipation device comprises the cooling pipe and the turning pump machine, the refrigerant input end of the cooling pipe is connected with the output end of the turning pump machine, the cooling pipe is distributed above the level of the first type of chip and the level of the second type of chip, and the refrigerant output end of the cooling pipe is connected with the input end of the turning pump machine.
The technical scheme provided by the disclosure can comprise the following beneficial effects:
in the disclosure, aiming at the characteristics of high frequency, high power consumption, high heat dissipation and low frequency, low power consumption and low heat dissipation of the data chip, different working frequencies are configured for chips at different positions, the heat dissipation power of the chips at different positions is controlled to realize the temperature equalization of the whole product, the aging trend of the data chip is slowed down, and the heat dissipation efficiency of the data chip is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.
FIG. 1 shows a schematic diagram of a chip array provided by an exemplary embodiment;
FIG. 2 illustrates a schematic diagram of a chip array provided by an exemplary embodiment;
FIG. 3 illustrates a schematic diagram of another chip array provided by an exemplary embodiment;
FIG. 4a is a schematic diagram illustrating an array of chips in a decreasing configuration, according to an exemplary embodiment;
FIG. 4b is a schematic diagram of an array of chips in an alternate configuration, according to an exemplary embodiment;
FIG. 4c is a schematic diagram of an array of chips in a diamond configuration, according to an exemplary embodiment;
FIG. 5 illustrates a schematic diagram of an electronic device provided by an exemplary embodiment;
fig. 6a is a schematic diagram illustrating an example of an arrangement of a first refrigerant input end and a first refrigerant output end of an electronic device;
fig. 6b is a schematic diagram illustrating that the first cooling medium input end and the first cooling medium output end of the electronic device provided in the exemplary embodiment are arranged in the same column.
Detailed Description
The embodiments of the present disclosure are described below with reference to the drawings in the embodiments of the present disclosure. In the following description, reference is made to the accompanying drawings which form a part hereof and in which is shown by way of illustration specific aspects of embodiments of the disclosure or in which aspects of embodiments of the disclosure may be practiced. It should be understood that the disclosed embodiments may be used in other respects, and may include structural or logical changes not depicted in the drawings. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims. For example, it should be understood that the disclosure in connection with the described methods may equally apply to the corresponding apparatus or system for performing the methods, and vice versa. For example, if one or more particular method steps are described, the corresponding apparatus may comprise one or more units, such as functional units, to perform the described one or more method steps (e.g., a unit performs one or more steps, or multiple units, each of which performs one or more of the multiple steps), even if such one or more units are not explicitly described or illustrated in the figures. On the other hand, for example, if a particular apparatus is described based on one or more units, such as functional units, the corresponding method may comprise one step to perform the functionality of the one or more units (e.g., one step performs the functionality of the one or more units, or multiple steps, each of which performs the functionality of one or more of the plurality of units), even if such one or more steps are not explicitly described or illustrated in the figures. Further, it is to be understood that features of the various exemplary embodiments and/or aspects described herein may be combined with each other, unless explicitly stated otherwise.
Example 1
The present disclosure provides a chip array as shown in fig. 1, fig. 1 shows a schematic diagram of a chip array provided by one exemplary embodiment.
The chip array provided by the embodiment of the disclosure comprises: the computing board 12 and the at least two types of chips 14, wherein a first type of chip 141 of the at least two types of chips 14 is disposed in a first area of the computing board 12, and a second type of chip 142 of the at least two types of chips 14 is disposed in a second area of the computing board 12, wherein the power consumption of the first type of chip 141 is greater than the power consumption of the second type of chip 142; the heat dissipation priority of the first area is greater than the heat dissipation priority of the second area.
Specifically, as shown in fig. 1, the chip array according to the embodiment of the present disclosure performs a pre-test on a plurality of chips mounted on the computation force board 12, and obtains at least two types of chips through the test, that is, a first type of chip 141, a high-frequency, high-power, and high-heat dissipation chip; the second type of chip 142 is a low frequency, low power consumption, low heat dissipation chip. The first type chips 141 are marked as blank grids in fig. 1; the second type of chip 142 is marked as a solid grid.
The chip array provided by the embodiment of the present disclosure may include, in a heat dissipation manner: the air cooling and/or liquid cooling mode is adopted, wherein the air cooling heat dissipation mode is to take away the heat on the surface of the chip by taking air as a refrigerant, so that the purpose of heat dissipation is realized;
the liquid cooling heat dissipation mode can be an immersion type cooling mode in which the chip is cooled by cooling liquid, or the cooling pipe is in contact with the chip, and the heat on the surface of the chip is taken away by the cooling liquid in the cooling pipe, so that the purpose of heat dissipation is achieved.
In the embodiment of the present disclosure, the refrigerant is an air-cooled refrigerant, that is, air introduced through the air inlet brings heat dissipated by the chip away through contact between the air and the chip, and is finally discharged through the air outlet, after the first type chip 141 and the second type chip are obtained, because the first type chip 141 is a high-frequency, high-power, and high-heat dissipation chip, the first type chip 141 is disposed at the position of the air inlet, that is, in an achievable manner, because the air inlet amount at a position close to the air inlet is controllable and the air speed is greater than the air speed at a position close to a space, the high-frequency, high-power, and high-heat dissipation chip is favorably cooled and dissipated;
for the low-frequency, low-power consumption and low-heat dissipation chip, that is, the second type chip 142 in the embodiment of the present disclosure, is disposed near the air outlet, that is, in an achievable manner, since the heat dissipation requirement of the second type chip 142 is lower than that of the first type chip 141, after the first type chip 141 is cooled, the second type chip 142 disposed at the air outlet can still obtain effective heat dissipation. In the embodiment of the present disclosure, the first type chip 141 and the second type chip 142 are mounted on the force calculation board 12, and the first type chip 141 and the second type chip 142 are connected by a serial port, where the serial port may be a connection port reserved between the chips and/or a designated interface.
In the embodiments of the present disclosure, serial connections between chips may be configured as a symmetrical design, as shown in fig. 2, and fig. 2 shows a schematic diagram of a chip array according to an exemplary embodiment, so as to achieve balanced temperature and balanced wear.
Wherein, the purpose of the serial port connection of chip and chip in the embodiment of the present disclosure is:
firstly, the data streams are communicated with each other, so that the possibility of configuration is increased, and the data streams are reversely connected, namely the original data streams from a chip 0 to a chip 100, the data streams can be reversely configured in an interconnecting and communicating way, and a high-frequency and high-temperature area can be changed into a low-frequency and low-temperature area by matching with the physical layout of an external chip, so that the wear balance is ensured;
secondly, the advantage of interconnection is that due to the characteristics of a specific chip, the data volume of the serial port TX (Transmit) is larger than that of the RX (Receive), and when the link signal of TX in one direction is too noisy (due to process or material). The reverse communication ensures the availability of materials;
thirdly, interconnection and intercommunication improve the efficiency of force calculation board verification, and the chip verification method in the related technology is as follows: the number of chips is searched in one direction, and when the number is not enough, the number is stopped at the second position, so that the problem exists in the second chip; the chip can be searched from two directions respectively, and the problems that the two chips are broken, one chip is damaged, the TX of one chip is bad, and the RX of one chip is bad can be positioned.
And, the purpose of the symmetrical design of the chip array in the embodiments of the present disclosure is:
firstly, the symmetric design and the intercommunication and interconnection of the serial ports can ensure that the force calculation board can be used reversely, so that the yield of the force calculation board is improved;
secondly, since the working points (frequency + voltage) of different heat dissipation areas (i.e., the area where the first type chip 141 is located and the area where the second type chip 142 is located) are different, the chips in different areas of the same force calculation plate 12 are worn differently, and in order to increase the service life, the force calculation plate 12 is designed symmetrically, and the force calculation plate 12 can be physically reversed or fans at an air inlet and an air outlet are reversely driven (wind direction is reversed), so that wear balance is realized.
Thirdly, the air inlet and the air outlet cannot be dynamically adjusted at present, but if the force plate 12 is symmetrically arranged, the bidirectional fan can be designed to be dynamically adjusted.
The force calculation board 12 provides a first operating frequency to the first type of chip 141 and a second operating frequency to the second type of chip 142, respectively, wherein the first operating frequency is greater than the second operating frequency.
Specifically, in the embodiment of the present disclosure, the operating frequencies of different regions (i.e., the region where the first type chip 141 is located and the region where the second type chip 142 is located) are set to be different through different configurations, so as to achieve temperature equalization of the entire force computing board 12.
It should be noted that, in the actual simulation test process, the chips may be further classified according to the operating frequency, power consumption, and heat dissipation of the chips, that is, the chips are classified into at least three types according to each set operating frequency, power consumption, and heat dissipation continuation interval, as shown in fig. 3, fig. 3 shows a schematic diagram of another chip array provided in an exemplary embodiment, where an area where the high-frequency and high-temperature chips are located is a position of a blank grid, an area where the medium-frequency and medium-temperature chips are located is a position of a shadow grid, and an area where the low-frequency and low-temperature chips are located is a position of a solid grid.
In the disclosure, a chip array comprises a force calculation board and at least two types of chips, wherein a first type of chip of the at least two types of chips is arranged in a first area of the force calculation board, and a second type of chip of the at least two types of chips is arranged in a second area of the force calculation board, wherein the power consumption of the first type of chip is greater than that of the second type of chip; the heat dissipation priority of the first area is greater than that of the second area, due to the fact that the data chip is characterized by high frequency, high power consumption, high heat dissipation and low frequency, low power consumption and low heat dissipation, different working frequencies are configured for chips at different positions, the heat dissipation power of the chips at different positions is controlled to achieve temperature equalization of the whole product, the problem that in the related art, due to the fact that heat dissipation layout is unreasonable, heat dissipation of the data chip is poor is solved, the aging trend of the data chip is relieved, and the heat dissipation efficiency of the data chip is improved.
In summary, the chip array provided in the embodiment of the present disclosure includes the following implementation manners, specifically:
the first method is as follows: decremental configuration
In a preferred example, on the force calculation plate 12, the first type chip 141 in the first region is disposed on the side of the second type chip 142 in the second region.
Wherein, each chip in the sub-chips of the first type chip 141 and the second type chip 142 is provided with a serial number; each of the first type chips 141 is connected to each of the second type chips 142 by a digital phase-locked loop.
Specifically, as shown in fig. 4a, fig. 4a shows a schematic diagram of a chip array provided by an exemplary embodiment under a decreasing configuration condition, for example, each group is 10 chips, the chips are grouped into a first group according to physical distribution 1 to 10, a second group according to physical distribution 11 to 21, and a third group according to physical distribution 3 to 23 to 32. Then, the frequency is configured according to the frequency calculated by frequency _ fix-mod (chip _ id,10) × frequency _ step, wherein frequency _ fix is the working frequency of each chip, chip _ id is the number of the chip, and frequency _ step is the frequency step selected according to a digital Locked Loop (PLL for short), so as to ensure the stability of the system. It should be noted that if each group includes 20 chips, the group is denoted by mod (chip _ id,20), and so on, and the embodiments of the present disclosure are not particularly limited.
In addition, in addition to the descending configuration structure shown in fig. 4a, the deployment manner of the first type chip 141 and the second type chip 142 of the chip array provided by the embodiment of the present disclosure may further include: the numbers 0-16 are the first kind of chips, and the numbers 17-32 are the second kind of chips.
The embodiments of the present disclosure are only described by taking the above examples as examples, and the implementation of the chip array provided by the embodiments of the present disclosure is subject to no limitation.
The second method comprises the following steps: alternate arrangement
In a preferred example, the first type chips 141 in the first region are alternately arranged with the second type chips 142 in the second region on the force calculation plate 12.
Specifically, in the embodiment of the present disclosure, taking air cooling and heat dissipation as an example, the alternating configuration of the chips may include the following cases:
case 1: a first chip with high frequency, high power consumption and high heat dissipation is arranged at the air inlet, the first chip with high frequency, high power consumption and high heat dissipation is connected with a first chip with low frequency, low power consumption and low heat dissipation in a serial port manner, then the first chip with low frequency, low power consumption and low heat dissipation is connected with a second chip with high frequency, high power consumption and high heat dissipation in a serial port manner until the last chip with high frequency, high power consumption and high heat dissipation or the chip with low frequency, low power consumption and low heat dissipation is arranged at the air outlet;
specifically, as shown in fig. 4b, fig. 4b is a schematic diagram of a chip array provided by an exemplary embodiment in an alternate configuration, where a blank cell represents the first type of chip 141, and a solid cell represents the second type of chip 142; the air inlet is provided with a first sub-chip of the first type chip 141, the first sub-chip of the first type chip 141 is connected with a first sub-chip of the second type chip through a serial port, a second sub-chip of the first type chip is connected with a first sub-chip of the second type chip through a serial port, a second sub-chip of the second type chip is connected with a second sub-chip of the first type chip through a serial port until an Nth sub-chip of the first type chip is connected with an N-1 th sub-chip of the second type chip through a serial port, the Nth sub-chip of the second type chip is connected with an Nth sub-chip of the first type chip through a serial port, and the air outlet is provided with an Nth sub-chip of the second type chip, wherein N is an integer.
Case 2: the air inlet is provided with a first high-frequency high-power-consumption high-heat-dissipation chip which is connected with a second low-frequency low-power-consumption low-heat-dissipation chip in a serial port manner, the second low-frequency low-power-consumption low-heat-dissipation chip is connected with a third low-frequency low-power-consumption low-heat-dissipation chip in a serial port manner, or the second low-frequency low-power-consumption low-heat-dissipation chip is connected with a third low-frequency low-power-consumption low-heat-dissipation chip in a serial port manner and a fourth low-frequency low-power-consumption low-heat-dissipation chip in a serial port manner, then the third low-frequency low-power-consumption low-heat-dissipation chip or the fourth low-frequency low-power-consumption low-heat-dissipation chip is connected with the second high-frequency high-power-consumption high-heat-dissipation chip in a serial port manner until the last high-frequency high-power-consumption high-heat-dissipation chip or the low-frequency low-power-consumption low-heat-dissipation chip is arranged at the air outlet;
it should be noted that, the embodiment of the present disclosure is only described by taking the above two cases as examples, so as to implement the chip array provided by the embodiment of the present disclosure, and the embodiment of the present disclosure is not particularly limited.
Based on the alternate configuration in the second mode, in the embodiment of the present disclosure, the configuration may be performed according to the following formula in the configuration process:
frequency_fix–mod(chip_id,2)*freq_step，
based on the formula, the temperature uniformity of the whole Printed Circuit Board (pcb) Board (i.e., the force computing Board in the embodiment of the present disclosure) can be ensured.
The third method comprises the following steps: diamond configuration
In a preferred example, on the force computing board 12, the second type chips 142 in the second area are located around the first type chips 141 in the first area; or, the first type chips 141 in the first region are located around the second type chips 142 in the second region.
Specifically, as shown in fig. 4c, fig. 4c is a schematic diagram of a chip array provided by an exemplary embodiment in a diamond configuration, where a blank grid represents the first type of chip 141, and a solid grid represents the second type of chip 142;
because the wind of the circular fan flows in the rectangular space, the heat dissipation capacity of each position of the rectangular space is not uniform in nature, the heat dissipation capacity of the middle position is strong, and the heat dissipation capacity of the corners is weak. Thus, for the characteristics of the first type of chip 141: the high-frequency, high-power consumption and high-heat dissipation are realized by concentrating the first type chips 141 in the center of the force computing board and arranging the second type chips 142 at the positions of the force computing board surrounding the first type chips 141.
Similarly, when the first type chips 141 in the first region are located around the second type chips 142 in the second region, the position of the first type chips 142 in fig. 4c is the position of the first type chips 141 in the current situation, and at this time, the position of the first type chips 141 is subjected to the heat dissipation treatment preferentially, that is, taking air cooling as an example, an air duct is arranged to guide the air outlet of the heat dissipation fan corresponding to the air inlet of the chip array into the outside air (or, the cooling air) to perform the heat dissipation treatment preferentially on the first type chips 141. The above examples are merely described as preferred specific examples, so as to implement the chip array provided by the embodiments of the present disclosure, and are not limited specifically.
The method is as follows: gradual change diamond configuration
Wherein, the fourth mode is a combination scheme of the first mode and the third mode.
The fifth mode is as follows: computing power arrangement
In a preferred example, the first and second regions are determined by performing a temperature test on the first type of chip 141 and the second type of chip 142.
Specifically, the temperature of each chip is obtained by testing each chip in the first type chip 141 and the second type chip 142; determined on the force computation board 12 according to the temperature of each chip. The temperature of each chip is tested, and then the working point is configured according to the temperature value, and each chip is configured independently. Thereby realizing the advantage of better temperature uniformity.
The chip array in the embodiment of the disclosure can be applied to electronic equipment with high computational power demand to satisfy the demand of the electronic equipment on the computational power of the chip, and the chip heat dissipation is balanced based on the arrangement mode of the chip array, so that the service life of the chip is prolonged, and the capability of stable operation of the chip is improved.
Example 2
The present disclosure provides an electronic device as shown in fig. 5, fig. 5 showing a schematic view of an electronic device provided by one exemplary embodiment.
The electronic equipment that this disclosed embodiment provided includes: the chip array 52 and the heat dissipation device 54 in embodiment 1, wherein in the electronic device provided in the embodiment of the present disclosure, the chip array 52 may be the chip array described in embodiment 1, and since the power consumption of the first type of chip in the chip array 52 is higher than that of the second type of chip, an area where the first type of chip is located in the chip array 52 in the embodiment of the present disclosure is a first area, and an area where the second type of chip is located is a second area, where a heat dissipation priority of the first area is higher than a heat dissipation priority of the second area;
the heat dissipation method of the heat dissipation device 54 includes: air-cooled heat dissipation and/or liquid-cooled heat dissipation. The refrigerant includes: air-cooled refrigerant and liquid cooling refrigerant, wherein, the air-cooled refrigerant is used for taking away the mode of chip surface heat with the gaseous state and dispels the heat to the chip, includes at least: air, compressed refrigeration air and inert cold air; the liquid cooling refrigerant at least includes: cooling water, liquid gas.
In a preferred example, in the case that the heat dissipation device 54 includes a heat dissipation fan, the heat dissipation fan is connected to a cooling medium input end, the cooling medium input end corresponds to the first area of the force calculation plate, and the cooling medium output end corresponds to the second area of the force calculation plate, wherein the cooling medium input end introduces cold air, the cooling medium output end discharges cold air, and the cooling medium input end and the cooling medium output end are disposed opposite to each other or in the same column.
Specifically, in the electronic device provided in the embodiment of the present disclosure, the heat dissipation fan may be a turning fan set, and since the working frequency of the first type chip and the second type chip may be controlled by the force calculating board, the heat dissipation requirement may also change during the process of adjusting the working frequency of the chips, and the turning fan set may adjust the flow direction of the air above the whole chip array according to the heat dissipation requirement of the chip array, so as to adjust the air flow direction according to the heat dissipation requirement of the chip, and meet the heat dissipation requirement of the whole chip array in real time;
in this embodiment of this disclosure, turning fan group includes first turning fan and second turning fan, and first turning fan is installed in first refrigerant input, and the second turning fan is installed in first refrigerant output, and when the actual operation, default control can be: controlling the first turning fan to operate in the forward direction, namely, air enters the chip array from the outside through the first refrigerant input end, the second turning fan and the first turning fan operate in the same direction, and the air flowing through the chip array is discharged to the outside through the first refrigerant output end;
after the working frequency of each chip in the chip array is adjusted by the computing board, if the heat dissipation requirement changes, the working frequency can be adjusted by controlling the running directions of the first turning fan and the second turning fan, namely, when the heat dissipation requirement changes, the first turning fan is controlled to run reversely, namely, air is discharged from the chip array to the outside through the first refrigerant input end, the second turning fan and the first turning fan run in the same direction, and the outside air flows through the chip array through the first refrigerant output end;
in this disclosure, to the chip array at first refrigerant input installation first diversion fan, at first refrigerant output installation second diversion fan, realized adjusting the overhead air flow direction of chip array according to the heat dissipation demand, and then reduced the temperature unbalance, reduced cooling system's pressure, reduced the pressure to the device, realize low-cost product realization.
In a preferred example, the refrigerant input end is positioned at one side of the first type chip; the refrigerant output end and the refrigerant input end are arranged oppositely and are positioned on one side of the second type chip; or the refrigerant input end is positioned at one side of the first type of chip; the refrigerant output end and the refrigerant input end are arranged in the same row.
Specifically, as shown in fig. 6a and fig. 6b, fig. 6a is a schematic diagram illustrating a refrigerant input end and a refrigerant output end of an electronic device provided in an exemplary embodiment that are arranged oppositely, where the refrigerant input end corresponds to one side of a first type chip, the refrigerant output end is arranged oppositely to the refrigerant input end, and the refrigerant output end is arranged at one side of a second type chip;
fig. 6b is a schematic diagram illustrating that a refrigerant input end and a refrigerant output end in an electronic device are arranged in the same column according to an exemplary embodiment, that is, in another implementation manner corresponding to the first implementation manner in embodiment 1, the refrigerant input end corresponds to one side of the first type chip, and the refrigerant output end is parallel to the refrigerant input end.
In a preferred example, the refrigerant input end is located above the level of the first type of chip, and the refrigerant output end is located on any side of the second type of chip.
Specifically, the heat dissipation fan is installed above the level of the first type of chip, air directly output by the heat dissipation fan guided by the refrigerant input end directly blows air to the first type of chip for heat dissipation, and air flowing through the first type of chip and the second type of chip is guided out by the refrigerant output end, so that the overall temperature of the chip array 52 is reduced.
In a preferred example, in the case that the heat sink 54 includes a cooling pipe and a direction-changing pump, the refrigerant input end of the cooling pipe is connected to the output end of the direction-changing pump, the cooling pipe is distributed above the level of the first type chip and the level of the second type chip, and the refrigerant output end of the cooling pipe is connected to the input end of the direction-changing pump.
In the embodiment of the present disclosure, taking a liquid cooling refrigerant as an example, the flow direction and/or the flow rate of the cooling liquid in the cooling pipe is adjusted by the turning pump through the cooling pipes distributed on the chip array 52, so as to realize effective heat dissipation for the characteristics of the first type chip and the second type chip.
Specifically, under the radiating mode of liquid cooling, the liquid cooling refrigerant can be the coolant liquid, based on diversion pump machine and cooling tube connection structure, can be through the flow direction and/or the velocity of flow of the coolant liquid in the power consumption adjustment cooling tube of each chip in the chip array of gathering.
It should be noted that, in the embodiment of the present disclosure, the heat dissipation manner for the chip array includes three manners, air-cooled heat dissipation, liquid-cooled heat dissipation, air-cooled heat dissipation, and liquid-cooled heat dissipation.
The chip array provided by the embodiment of the present disclosure is only exemplified by the above heat dissipation manner, and is subject to the realization of the chip array provided by the embodiment of the present disclosure, which is not particularly limited.
Those of skill in the art will appreciate that the functions described in connection with the various illustrative logical blocks, modules, and algorithm steps described in the disclosure herein may be implemented as hardware, software, firmware, or any combination thereof. If implemented in software, the functions described in the various illustrative logical blocks, modules, and steps may be stored on or transmitted over as one or more instructions or code on a computer-readable medium and executed by a hardware-based processing unit. The computer-readable medium may include a computer-readable storage medium, which corresponds to a tangible medium, such as a data storage medium, or any communication medium including a medium that facilitates transfer of a computer program from one place to another (e.g., according to a communication protocol). In this manner, a computer-readable medium may generally correspond to (1) a non-transitory tangible computer-readable storage medium, or (2) a communication medium, such as a signal or carrier wave. A data storage medium may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, code and/or data structures for implementing the techniques described in this disclosure. The computer program product may include a computer-readable medium.
By way of example, and not limitation, such computer-readable storage media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the instructions are transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. It should be understood, however, that the computer-readable storage media and data storage media do not include connections, carrier waves, signals, or other transitory media, but are instead directed to non-transitory tangible storage media. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The instructions may be executed by one or more processors, such as one or more Digital Signal Processors (DSPs), general purpose microprocessors, Application Specific Integrated Circuits (ASICs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Thus, the term "processor," as used herein may refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. Additionally, in some aspects, the functions described by the various illustrative logical blocks, modules, and steps described herein may be provided within dedicated hardware and/or software modules configured for encoding and decoding, or incorporated in a combined codec. Also, the techniques may be fully implemented in one or more circuits or logic elements.
The techniques of this disclosure may be implemented in a variety of described devices or apparatuses, including a wireless handset, an Integrated Circuit (IC), or a set of ICs (e.g., a chipset). Various components, modules, or units are described in this disclosure to emphasize functional aspects of means for performing the disclosed techniques, but do not necessarily require realization by different hardware units. Indeed, as described above, the various units may be combined in a codec hardware unit, in conjunction with suitable software and/or firmware, or provided by an interoperating hardware unit (including one or more processors as described above).
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The above description is only an exemplary embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present disclosure should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.
Claims (10)
1. A chip array, comprising:
an algorithm board and at least two types of chips, wherein,
a first chip of the at least two types of chips is arranged in a first area of the force calculation board, and a second chip of the at least two types of chips is arranged in a second area of the force calculation board, wherein the power consumption of the first chip is greater than that of the second chip; the heat dissipation priority of the first area is greater than the heat dissipation priority of the second area.
2. The chip array of claim 1, wherein the first type of chips in the first region are disposed on a side of the second type of chips in the second region on the force computation plate.
3. The chip array of claim 1, wherein the first type of chips in the first region alternate with the second type of chips in the second region on the force computation plate.
4. The chip array according to claim 1 or 2, wherein the second type of chips in the second area are located around the first type of chips in the first area on the computing board; or the first type of chips in the first area are positioned around the second type of chips in the second area.
5. The chip array of claim 1, wherein the first area and the second area are determined by performing a temperature test on the first type of chip and the second type of chip.
6. An electronic device, comprising: the chip array and the heat dissipating apparatus according to any of claims 1 to 5,
the input end of a refrigerant in the heat dissipation device corresponds to the first area of the chip array; and the refrigerant output end in the heat radiating device corresponds to the second area of the chip array.
7. The electronic device of claim 6, wherein, in the case where the heat sink comprises a heat dissipation fan,
the cooling fan is connected with the refrigerant input end, the refrigerant input end corresponds to a first area of the force calculation plate, the refrigerant output end corresponds to a second area of the force calculation plate, cold air is introduced into the refrigerant input end, the cold air is discharged from the refrigerant output end, and the refrigerant input end and the refrigerant output end are arranged oppositely or in the same row.
8. The electronic device of claim 7,
the refrigerant input end is positioned on one side of the first type of chip; the refrigerant output end and the refrigerant input end are arranged oppositely and are positioned on one side of the second type chip; or the like, or, alternatively,
the refrigerant input end is positioned on one side of the first type of chip; the refrigerant output end and the refrigerant input end are arranged in the same row.
9. The electronic device of claim 7,
the refrigerant input end is located above the level of the first type of chip, and the refrigerant output end is located on any side of the second type of chip.
10. The electronic apparatus according to claim 6, wherein in the case where the heat dissipating means includes a cooling pipe and a direction-changing pump,
the refrigerant input end of the cooling pipe is connected with the output end of the turning pump, the cooling pipe is distributed above the level of the first type of chip and the level of the second type of chip, and the refrigerant output end of the cooling pipe is connected with the input end of the turning pump.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111521527.5A CN114373725A (en) | 2021-12-13 | 2021-12-13 | Chip array and electronic equipment |
| PCT/CN2022/132170 WO2023109411A1 (en) | 2021-12-13 | 2022-11-16 | Chip array and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111521527.5A CN114373725A (en) | 2021-12-13 | 2021-12-13 | Chip array and electronic equipment |
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| Publication Number | Publication Date |
|---|---|
| CN114373725A true CN114373725A (en) | 2022-04-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111521527.5A Pending CN114373725A (en) | 2021-12-13 | 2021-12-13 | Chip array and electronic equipment |
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| Country | Link |
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| CN (1) | CN114373725A (en) |
| WO (1) | WO2023109411A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023109411A1 (en) * | 2021-12-13 | 2023-06-22 | 北京比特大陆科技有限公司 | Chip array and electronic device |
| CN116583096A (en) * | 2023-07-14 | 2023-08-11 | 四川天中星航空科技有限公司 | Totally-enclosed radio frequency comprehensive test equipment |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106304768A (en) * | 2015-06-02 | 2017-01-04 | 中兴通讯股份有限公司 | Subrack and plug-in card thereof |
| CN110764598A (en) * | 2019-12-09 | 2020-02-07 | 北京益现科技有限公司 | Radiator, circuit board assembly and computing device |
| CN113126723A (en) * | 2019-12-31 | 2021-07-16 | 北京灵汐科技有限公司 | Method for setting chip radiator of electronic board card and electronic board card |
| CN112492862B (en) * | 2021-01-05 | 2021-04-23 | 四川赛狄信息技术股份公司 | High-power printed circuit board |
| CN114373725A (en) * | 2021-12-13 | 2022-04-19 | 北京比特大陆科技有限公司 | Chip array and electronic equipment |
-
2021
- 2021-12-13 CN CN202111521527.5A patent/CN114373725A/en active Pending
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2022
- 2022-11-16 WO PCT/CN2022/132170 patent/WO2023109411A1/en unknown
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023109411A1 (en) * | 2021-12-13 | 2023-06-22 | 北京比特大陆科技有限公司 | Chip array and electronic device |
| CN116583096A (en) * | 2023-07-14 | 2023-08-11 | 四川天中星航空科技有限公司 | Totally-enclosed radio frequency comprehensive test equipment |
| CN116583096B (en) * | 2023-07-14 | 2023-09-12 | 四川天中星航空科技有限公司 | Totally-enclosed radio frequency comprehensive test equipment |
Also Published As
| Publication number | Publication date |
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| WO2023109411A1 (en) | 2023-06-22 |
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