CN114373425A

CN114373425A - Driving circuit, display panel and driving method

Info

Publication number: CN114373425A
Application number: CN202210049535.2A
Authority: CN
Inventors: 栗华; 张留旗
Original assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2022-01-17
Filing date: 2022-01-17
Publication date: 2022-04-19
Anticipated expiration: 2042-01-17
Also published as: CN114373425B

Abstract

The application provides a driving circuit, a display panel and a driving method. The driving circuit comprises a driving transistor, a light-emitting device, a storage module, a data signal writing module, a first initialization module, a second initialization module and a control module. According to the driving circuit, the display panel and the driving method, the control module comprising the at least two transistors is arranged, so that the at least two transistors in the control module are alternately conducted in the preset time sequence period, and the problem of poor quality of the display panel caused by long-term operation and aging of the driving circuit is obviously reduced.

Description

Driving circuit, display panel and driving method

Technical Field

The application relates to the technical field of display, in particular to a driving circuit, a display panel and a driving method.

Background

The Organic Light Emitting Diode (OLED) display panel has the advantages of self-emission, viewing angle Light, fast response speed, high Light Emitting efficiency, wide color gamut, low working voltage, thin body, capability of being manufactured in large size, capability of being actually bent, and the like, and has become an important development direction of the flat panel display technology at present.

However, the OLED display panel is limited by the stability of its own material, and its display quality deteriorates with the increase of the usage time, and the main reasons for the deterioration of the display quality are that the driving transistor of the driving circuit is biased forward in threshold voltage and the OLED device is aged, so that the OLED driving current changes, and the display quality of the OLED display panel is affected.

Disclosure of Invention

The application provides a driving circuit, a display panel and a driving method for overcoming the technical defect that the existing OLED display panel has poor display picture due to overlong service time, so as to solve the problem that the threshold voltage of a driving transistor is forward biased and ensure the display quality of the OLED display panel.

According to an aspect of the present invention, there is provided a driving circuit, including,

a driving transistor, a gate of which is electrically connected to a first node, one of a source and a drain of which is electrically connected to a second node, and the other of the source and the drain of which is electrically connected to a third node;

a light emitting device, a first terminal of which is electrically connected to the third node and a second terminal of which is electrically connected to a first power supply;

a first end of the storage module is electrically connected with the first node, and a second end of the storage module is electrically connected with the third node;

the data signal writing module is accessed to a data control signal and a data signal and is electrically connected with the first node, and the data signal writing module is used for outputting the data signal to the first node under the control of the data control signal;

the first initialization module is accessed to a first initialization control signal and a first initialization signal and is electrically connected to the first node, and the first initialization module is used for outputting the first initialization signal to the first node under the control of the first initialization control signal;

the second initialization module is accessed to a second initialization control signal and a second initialization signal and is electrically connected to the third node, and the second initialization module is used for outputting the second initialization signal to the third node under the control of the second initialization control signal;

a control module disposed in series between a second power supply and the second node, the control module including at least two transistors; wherein at least two of the transistors are alternately turned on within a preset timing period.

Further, the control module comprises a first transistor and a second transistor; a gate of the first transistor is connected to a first control signal, one of a source and a drain of the first transistor is electrically connected to the second power supply, and the other of the source and the drain of the first transistor is electrically connected to the second node; a gate of the second transistor is connected to a second control signal, one of a source and a drain of the second transistor is electrically connected to the second power supply, and the other of the source and the drain of the second transistor is electrically connected to the second node.

In the driving circuit provided by the present application, the preset timing period includes at least two frame display periods; in an on period in any one of the display periods, the first transistor or the second transistor is turned on.

In the driving circuit provided by the present application, the preset timing period includes a first display period and a second display period; the first display period is adjacent to the second display period; the first transistor is turned on during a turn-on period in the first display period, and the second transistor is turned on during a turn-on period in the second display period.

In the driving circuit provided by the present application, the first reset module includes a third thin film transistor; the grid electrode of the third thin film transistor is connected with the first scanning signal input end, the first pole of the third thin film transistor is connected with the control end of the driving module, and the second pole of the third thin film transistor is connected with the first reset signal input end. The preset time sequence period comprises a first display period, a second display period and a third display period; the first display period, the second display period and the third display period are adjacent to each other;

the first transistor is turned on during a turn-on period in the first display period, the second transistor is turned on during a turn-on period in the second display period, and the first transistor or the second transistor is turned on during a turn-on period in the third display period.

In the driving circuit provided by the present application, the preset timing period is a frame display period; the one-frame display period includes a first on period and a second on period; one of the first transistor and the second transistor is turned on in the first on period; the other of the first transistor and the second transistor is turned on in the second conduction period.

In the driving circuit provided by the present application, the first initialization module includes a third transistor, a gate of the third transistor is connected to the first initialization control signal, one of a source and a drain of the third transistor is connected to the first initialization signal, and the other of the source and the drain of the third transistor is electrically connected to the first node;

the second initialization module comprises a fourth transistor, the grid electrode of the fourth transistor is connected with the second initialization control signal, one of the source electrode and the drain electrode of the fourth transistor is connected with the second initialization signal, and the other of the source electrode and the drain electrode of the fourth transistor is electrically connected with the third node;

and/or the storage module comprises a storage capacitor, wherein a first end of the storage capacitor is electrically connected with the first node, and a second end of the storage capacitor is electrically connected with the third node;

and/or the data signal writing module comprises a fifth transistor, the grid electrode of the fifth transistor is connected with the data control signal, one of the source electrode and the drain electrode of the fifth transistor is connected with the data signal, and the other of the source electrode and the drain electrode of the fifth transistor is electrically connected with the first node.

In the driving circuit provided by the application, in at least two transistors, the transistors are both N-type transistors or P-type transistors.

According to another aspect of the present invention, there is provided a display panel, including,

a data line for supplying a data signal;

a first initialization line for providing a first initialization signal;

a second initialization line for providing a second initialization signal;

a first scan line for providing a data control signal;

a second scan line for providing a first initialization control signal;

a third scan line for providing a second initialization control signal; and the driving circuit described above, which is electrically connected to the data line, the first initialization line, the second initialization line, the first scan line, the second scan line, and the third scan line.

According to another aspect of the present invention, there is also provided a driving method of the above display panel, the driving method including:

an initialization phase, wherein the first initialization module provides the first initialization signal to the first node, and the second initialization module provides the second initialization signal to the third node;

a compensation phase, wherein the first initialization module provides the first initialization signal to the first node; one of at least two transistors of the control module is turned on to provide a second voltage of the second power supply to the second node;

a data write phase, wherein the data write module provides the data signal to the first node;

and in a light emitting stage, the other of the at least two transistors of the control module is conducted to provide the second voltage to the second node.

The invention has the beneficial technical effects that: the driving circuit is provided with a control module comprising at least two transistors so as to realize continuous and effective control on the driving transistors; meanwhile, the design of the driving circuit makes the driving current flowing through the light-emitting device irrelevant to the threshold voltage of the driving transistor, thereby obviously reducing the poor quality of the display panel caused by the positive bias of the threshold voltage and the aging of the driving circuit device.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a driving circuit provided in an embodiment of the present application;

fig. 2 is a circuit schematic diagram of a driving circuit provided in an embodiment of the present application;

FIG. 3 is a timing diagram of a driving circuit provided in an embodiment of the present application;

FIG. 4 is a schematic diagram of a reset phase of a driving circuit provided in an embodiment of the present application at the driving timing shown in FIG. 3;

FIG. 5 is a schematic diagram of a path of a compensation stage of the driving circuit provided by the embodiment of the present application under the driving timing shown in FIG. 3;

FIG. 6 is a schematic diagram of a data write phase of the driving circuit according to the embodiment of the present application at the driving timing shown in FIG. 3;

FIG. 7 is a schematic diagram of a light-emitting stage of a driving circuit provided in the embodiment of the present application at the driving timing shown in FIG. 3;

fig. 8 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

fig. 9 is a schematic step diagram of a driving method of a display panel according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In the transistor of the present invention, the source and the drain are symmetric, and therefore the source and the drain are interchangeable.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure. As shown in fig. 1, the driving circuit 10 provided in the embodiment of the present application includes a driving transistor T0, a light emitting device D, a memory module 101, a data signal writing module 102, a first initialization module 103, a second initialization module 104, and a control module 105. It should be noted that the light emitting device D may be a mini light emitting diode, a micro light emitting diode or an organic light emitting diode.

The gate of the driving transistor T0 is connected to the first node Q, one of the source and the drain of the driving transistor T0 is electrically connected to the second node Z, and the other of the source and the drain of the driving transistor T0 is electrically connected to the third node S. A first terminal of the light emitting device D is electrically connected to the third node S, and a second terminal of the light emitting device D is electrically connected to the first power source VSS. A first terminal of the memory module 101 is electrically connected to the first node Q, and a second terminal of the memory module 101 is electrically connected to the third node S. The first initialization module 103 receives the first initialization control signal REF and the first initialization signal Vref and is electrically connected to the first node Q. The second initialization module 104 accesses the second initialization control signal INI and the second initialization signal Vini, and is electrically connected to the third node S. The control module 105 is serially connected between the second power supply VDD and the second node Z.

It should be noted that the control module 105 of the embodiment of the present application includes at least two transistors, and at least two transistors are turned on alternately in a preset timing period, so as to significantly reduce the stress of the control module 105 that is subjected to a positive bias voltage due to long-term operation of the driving circuit 10, and ensure that the control module 105 is turned on normally for a long time.

Specifically, the driving transistor T0 is used to control the current flowing through the light emitting loop. The first initialization module 103 is configured to write a first initialization signal Vref to the gate of the driving transistor T0 through the first node Q under the control of the first initialization control signal REF. The second initialization block 104 is configured to write the second initialization signal Vini to one of the source and the drain of the driving transistor T0 through the third node S under the control of the second initialization control signal INI. The data signal writing module 102 is configured to write the data signal Vdata to the gate of the driving transistor T0 through the first node Q under the control of the data signal Vdata. The memory module 101 is used for storing the gate potential of the driving transistor T0 and adjusting the potential of the third node S. The control module 105 is configured to enable a plurality of transistors of the control module 105 to alternately control the light emitting loop to be turned on or off within a preset timing period under the control of the control signal.

The driving circuit 10 provided in the embodiment of the present application controls the turn-on or turn-off of the light emitting loop alternately by setting the control module 105 including at least two transistors, so as to significantly reduce the forward bias voltage generated by the aging of the transistors or the long-term operation of the driving circuit 10, avoid the control module 105 from being affected by the stress of the forward bias voltage, and ensure that the control module 105 is normally turned on for a long time.

In some embodiments, please refer to fig. 2, and fig. 2 is a circuit diagram of a driving circuit according to an embodiment of the present disclosure. Referring to fig. 1 and 2, the control module 105 according to the embodiment of the present disclosure includes a first transistor T1 and a second transistor T2, a gate of the first transistor T1 is connected to a first control signal Em1, one of a source and a drain of the first transistor T1 is electrically connected to the second power source VDD, and the other of the source and the drain of the first transistor T1 is electrically connected to the second node Z. The gate of the second transistor T2 is connected to the second control signal Em2, one of the source and the drain of the second transistor T2 is electrically connected to the second power supply VDD, and the other of the source and the drain of the second transistor T2 is electrically connected to one of the source and the drain of the driving transistor T0 through the second node Z.

In some embodiments, please continue to refer to fig. 1 and 2. The first initialization module 103 includes a third transistor T3, a gate of the third transistor T3 is connected to the first initialization control signal REF, one of a source and a drain of the third transistor T3 is connected to the first initialization signal Vref, and the other of the source and the drain of the third transistor T3 is electrically connected to the gate of the driving transistor T0 through a first node Q.

In some embodiments, please continue to refer to fig. 1 and 2. The second initialization block 104 includes a fourth transistor T4, a gate of the fourth transistor T4 is connected to the second initialization control signal INI, one of a source and a drain of the fourth transistor T4 is connected to the second initialization signal Vini, and the other of the source and the drain of the fourth transistor T4 is electrically connected to the other of the source and the drain of the driving transistor T0 through a third node S.

In some embodiments, please continue to refer to fig. 1 and 2. The storage module 101 includes a storage capacitor Cst, a first terminal of the storage capacitor Cst is electrically connected to the gate of the driving transistor T0 through a first node Q, and a second terminal of the storage capacitor Cst is electrically connected to the other of the source and the drain of the driving transistor T0 through a third node S.

In some embodiments, please continue to refer to fig. 1 and 2. The data signal Vdata write module 103 includes a fifth transistor T5, a gate of the fifth transistor T5 is connected to the data control signal Gn, one of a source and a drain of the fifth transistor T5 is connected to the data signal Vdata, and the other of the source and the drain of the fifth transistor T5 is electrically connected to the gate of the driving transistor T0 through a first node Q.

In some embodiments, the first power source VSS and the second power source VDD are both used for outputting a predetermined voltage value. In addition, in the embodiment of the present application, the potential of the second power supply VDD is larger than the potential of the first power supply VSS. Specifically, the potential of the first power supply VSS may be the potential of the ground terminal. Of course, it is understood that the potential of the second power supply VDD may be other.

In some embodiments, the plurality of transistors in the control module 105 are all N-type transistors or P-type transistors. Thereby avoiding the effect of the differences between the different types of transistors on the turn-on and turn-off functionality of the control module 105.

In some embodiments, the driving transistor T0, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be one or more of a low temperature polysilicon thin film transistor, an oxide semiconductor thin film transistor, or an amorphous silicon thin film transistor. Further, the transistors in the driving circuit 10 provided in the embodiment of the present application may be configured as the same type of transistors, that is, both of the transistors are N-type transistors or P-type transistors. Thereby avoiding the influence of the difference between different types of transistors on the driving circuit 10.

In some embodiments, referring to fig. 3, fig. 3 is a timing diagram of a 6T2C driving circuit according to an embodiment of the present disclosure. As shown in fig. 3, the preset timing period includes at least two display periods of two frames, and the first transistor T1 or the second transistor T2 is turned on in the turn-on period of any one of the display periods. Specifically, in the present embodiment, the preset timing cycle includes a first control signal Em1, a second control signal Em2, a first initialization signal Vref, a second initialization signal Vini, and a data writing signal, which are combined to correspond to the initialization phase t1, the compensation phase t2, the data writing phase t3, and the light emitting phase t4 in sequence.

In some embodiments, in the reset phase, the first initialization control signal REF and the second initialization control signal INI are both high, and the data control signal Gn, the first control signal Em1, and the second control signal Em2 are all low.

In some embodiments, during the compensation period t2, one of the first initialization control signal REF, the first control signal Em1 and the second control signal Em2 is at a high potential, and the other of the second initialization control signal INI, the data control signal Gn, the first control signal Em1 and the second control signal Em2 is at a low potential.

In some embodiments, during the data writing phase t3, the data control signal Gn is high, and the first initialization control signal REF, the second initialization control signal INI, the first control signal Em1, and the second control signal Em2 are low.

In some embodiments, during the light emitting period t4, one of the first control signal Em1 and the second control signal Em2 is at a high level, and the other of the first control signal Em1 and the second control signal Em2, the first initialization control signal REF, the second initialization control signal INI, and the data control signal Gn are all at a low level. In the one-frame display period, one of the first control signal Em1 and the second control signal Em2 in the compensation phase t2, which is at the high potential, may be the same as or different from one of the first control signal Em1 and the second control signal Em2 in the emission phase t4, which is at the high potential.

Specifically, referring to fig. 3 and fig. 4, fig. 4 is a schematic diagram of a path of a reset stage of the driving circuit according to the embodiment of the present application at the driving timing shown in fig. 3. The preset time sequence period comprises a first display period and a second display period, and the first display period is adjacent to the second display period. The first display period please refer to the display period T1, and the second display period please refer to the display period T2. The first display period and the second display period sequentially include an initialization period t1, a compensation period t2, a data writing period t3, and a light emitting period t 4.

In the initialization period T1 of the first display period, the first initialization control signal REF is high, the third transistor T3 is turned on under the high potential control of the first initialization control signal REF, and the first initialization signal Vref is written into the gate of the driving transistor T0 through the first node Q to initialize the gate of the driving transistor T0. In the initialization stage T1, the second initialization control signal INI is at a high level, the fourth transistor T4 is turned on under the high level control of the second initialization control signal INI, and the second initialization signal Vini is written into one of the source and the drain of the driving transistor T0 through the third node S to realize the initialization of one of the source and the drain of the driving transistor T0.

Meanwhile, in the reset phase, the first control signal Em1, the second control signal Em2 and the data control signal Gn are all low-potential, so that the first transistor T1, the second transistor T2, the fifth transistor T5 and the driving transistor T0 are all turned off.

Referring to fig. 3 and fig. 5, fig. 5 is a schematic path diagram of a compensation stage t2 of the driving circuit 10 according to the embodiment of the present application under the driving timing shown in fig. 3. In the compensation period T2 of the first display period, the first initialization control signal REF is at a high level, the third transistor T3 is turned on under the control of the high level of the first initialization control signal REF, and the first initialization signal Vref is written into the gate of the driving transistor T0 through the first node Q. In the compensation period T2 of the first display period, the first control signal Em1 is at a high level, the first transistor T1 is turned on under the control of the high level of the first control signal Em1, and the second power VDD flows through the first transistor T1 and is written into the other of the source and the drain of the driving transistor T0 through the second node Z. At this time, the driving transistor T0 is turned on to raise the potential of the third node S, and when the gate-source voltage difference of the driving transistor T0 is equal to the threshold voltage of the driving transistor T0, the driving transistor T0 is turned off, and the off-threshold condition is satisfied: the potential of the third node S is the difference between the potential of the gate of the driving transistor T0 and the threshold voltage of the driving transistor T0. Also, due to the existence of the storage capacitor Cst, the potential of the third node S is maintained at the difference between the potential of the gate of the driving transistor T0 and the threshold voltage of the driving transistor T0.

Meanwhile, in the compensation stage T2, the second control signal Em2, the second initialization control signal INI, and the data control signal Gn are low, so that the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are all turned off.

Referring to fig. 3 and fig. 6, fig. 6 is a schematic diagram illustrating a path of the data writing stage t3 of the driving circuit 10 according to the embodiment of the present application at the driving timing shown in fig. 3. In the data writing period T3 of the first display period, the data control signal Gn is at a high level, the fifth transistor T5 is turned on under the control of the high level of the data control signal Gn, and the data signal Vdata is written into the gate of the driving transistor T0 through the first node Q. At this time, the potential of the first node Q is raised from the first initialization signal Vref to the data signal Vdata. At this time, the potential of the third node S is maintained at the difference between the potential of the gate of the driving transistor T0 and the threshold voltage of the driving transistor T0 due to the presence of the storage capacitor Cst.

Meanwhile, in the data writing phase T3, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the driving transistor T0 are all turned off because the first control signal Em1, the second control signal Em2, the first initialization control signal REF and the second initialization control signal INI are low.

Referring to fig. 3 and fig. 7, fig. 7 is a schematic path diagram of a light emitting phase t4 of the driving circuit 10 according to the embodiment of the present application at the driving timing shown in fig. 3. In the light emitting period T4 of the first display period, the first control signal Em1 is at a high voltage level, the first transistor T1 is turned on under the control of the high voltage level of the first control signal Em1, the second voltage is written into the second node Z through the second transistor T2, and the voltage level of the first node Q is still maintained at the data signal Vdata due to the existence of the storage capacitor Cst. At this time, the driving transistor T0 is turned on, and the light emitting device D emits light.

Further, the formula for calculating the current flowing through the light emitting device D is:

I_OLED＝1/2Cox(μ1W1/L1)(Vgs－Vth))²in which I_OLEDμ 1 is a current flowing through the light emitting device D, and μ 1 is a current flowing through the driving transistor T0The mobility, W1 and L1 are the width and length, respectively, of the channel of the driving transistor T0, Vgs is the voltage difference between the gate and one of the source and drain of the driving transistor T0, and Vth is the threshold voltage of the driving transistor T0.

That is, the current flowing through the light emitting device D:

I_OLED＝1/2Cox(μ1W1/L1)(Vgs-Vth)²＝1/2Cox(μ1W1/L1)

(Vdata+Vth-Vref-Vth)2＝1/2Cox(μ1W1/L1)(Vdata-Vref)²。

at this time, the current flowing through the light emitting device D is independent of the threshold voltage of the driving transistor T0, thereby achieving a threshold voltage compensation effect.

Meanwhile, in the light emitting period T4, the first initialization control signal REF, the second initialization control signal INI, the second control signal Em2, and the data control signal Gn are all low-level, so that the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all turned off.

In the second display period adjacent to the first display period, the second display period is different from the first display period in that, in the compensation period T2 of the second display period, the second control signal Em2 is high potential, the second transistor T2 is turned on under the control of the high potential of the second control signal Em2, and the second power VDD flows through the second transistor T2 and is written into the other one of the source and the drain of the driving transistor T0 through the second node Z. At the same time, the first control signal Em1 is low, such that the first transistor T1 is turned off. In the lighting period T4 of the second display period, the second control signal Em2 is at a high potential, the second transistor T2 is turned on under the control of the high potential of the second control signal Em2, and the second power VDD is written to the other of the source and the drain of the driving transistor T0 through the second node Z via the second transistor T2.

In the preset display period constituted by the first display period and the second display period, the first transistor T1 is turned on for the on period in the first display period, and the second transistor T2 is turned on for the on period in the second display period.

The driving circuit 10 according to the embodiment of the present application is provided with the control module 105 including the first transistor T1 and the second transistor T2. The first transistor T1 and the second transistor T2 alternately control the turn-on or turn-off of the light emitting circuit in a preset display period, so that the positive bias voltage generated by the aging of the transistors or the long-term operation of the driving circuit 10 is obviously reduced, the control module 105 is prevented from being affected by the stress of the positive bias voltage, and the control module 105 is ensured to be normally turned on for a long time.

In another embodiment, please refer to fig. 3-7. The preset time sequence period comprises a first display period, a second display period and a third display period, and the first display period is adjacent to the second display period and the third display period in pairs. The first display period and the third display period refer to the display period T1, and the second display period refers to the display period T2. The first transistor T1 is turned on for a turn-on period in the first display period, the second transistor T2 is turned on for a turn-on period in the second display period, and the first transistor T1 is turned on for a turn-on period in the third display period.

In another embodiment, please refer to fig. 3-7. The preset time sequence period comprises a first display period, a second display period and a third display period, and the first display period is adjacent to the second display period and the third display period in pairs. The first display period please refer to the display period T1, the second display period, and the third display period please refer to the display period T2. The first transistor T1 is turned on during the turn-on period in the first display period, the second transistor T2 is turned on during the turn-on period in the second display period, and the second transistor T2 is turned on during the turn-on period in the third display period.

In another embodiment, please refer to fig. 3-7. The preset time sequence period comprises a first display period, a second display period and a third display period, and the first display period is adjacent to the second display period and the third display period in pairs. The first display period and the second display period refer to the display period T1, and the third display period refers to the display period T2. The first transistor T1 is turned on for a turn-on period in the first display period, the first transistor T1 is turned on for a turn-on period in the second display period, and the second transistor T2 is turned on for a turn-on period in the third display period.

In yet another embodiment, please refer to fig. 3-7. The predetermined timing period is a frame display period, specifically, please refer to the display period T3 shown in fig. 3. The present embodiment is different from the previous embodiments in that the first transistor T1 is turned on during the compensation period T2, and the second transistor T2 is turned off during the compensation period T2. The first transistor T1 is turned off during the lighting period T4, and the second transistor T2 is turned on during the compensation period T2.

In another embodiment, the predetermined timing period is a frame display period, specifically, please refer to the display period Tn shown in fig. 3. The present embodiment is different from the previous embodiments in that the second transistor T2 is turned on during the compensation period T2, and the first transistor T1 is turned off during the compensation period T2. The second transistor T2 is turned off during the lighting period T4, and the first transistor T1 is turned on during the compensation period T2.

In yet another embodiment, please refer to fig. 3-7. The preset time sequence period comprises a first display period, a second display period and a third display period, and the first display period is adjacent to the second display period and the third display period in pairs. The first display period please refer to the display period T1, the second display period please refer to the display period T2, and the third display period please refer to the display period T3. The present embodiment is different from the previous embodiments in that the first transistor T1 is turned on in the turn-on period of the first display period, the second transistor T2 is turned on in the turn-on period of the second display period, the first transistor T1 is turned on in the compensation period T2 of the third display period, the second transistor T2 is turned off in the compensation period T2 of the third display period, the first transistor T1 is turned off in the light-emitting period T4 of the third display period, and the second transistor T2 is turned on in the compensation period T2 of the third display period.

Therefore, the display period T1, the display period T2, the display period T3, and the display period Tn may form a plurality of preset display periods that meet the purpose of the present disclosure, so that the driving circuit 10 of the present disclosure sets a plurality of transistors to alternately operate through the control module 105 in the preset display periods to continuously and effectively control the driving transistor T0.

Referring to fig. 8, fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. The present application further provides a display panel 100, which includes a data line 20, a first initialization line 30, a second initialization line 40, a first scan line 50, a second scan line 60, a third scan line 70, and the driving circuit 10 described above. The data line 20 is used for supplying a data signal. The first initialization line 30 is used to provide a first initialization signal. The second initialization line 40 is used to provide a second initialization signal. The first scan line 50 is used to provide a data control signal. The second scan line 60 is used to provide a first initialization control signal. The third scan line 70 is used to provide a second initialization control signal. The driving circuit 10 is electrically connected to the data line 20, the first initialization line 30, the second initialization line 40, the first scan line 50, the second scan line 60, and the third scan line 70. The driving circuit 10 can refer to the above description of the driving circuit 10, and is not described herein again.

The display panel 100 provided by the embodiment of the present application is provided with the driving circuit 10 provided by the embodiment of the present application, so that the forward bias voltage generated due to the aging of the transistor or the long-term operation of the driving circuit 10 is obviously reduced, the transistor is prevented from being affected by the stress of the forward bias voltage, the display quality of the display panel is ensured, and the display uniformity of the display panel is maintained for a long time.

Referring to fig. 9, fig. 9 is a schematic step diagram of a driving method of a display panel according to an embodiment of the present disclosure. The driving method is applied to the driving circuit 10 according to any embodiment, and the driving method for the pixels in each frame display period sequentially includes an initialization phase, a compensation phase, a data writing phase, and a light emitting phase.

In the initialization stage, the first initialization module provides a first initialization signal to the first node, and the second initialization module provides a second initialization signal to the third node.

S1002, in a compensation stage, a first initialization module provides a first initialization signal to a first node; one of the at least two transistors of the control module is turned on to provide the second voltage of the second power supply to the second node.

S1003, a data writing stage, wherein the data writing module provides a data signal to the first node.

And S1004, in a light-emitting stage, the other one of the at least two transistors of the control module is conducted, and the second voltage is provided to the second node.

The embodiment of the application provides a driving method of a display panel, and by applying the driving method of the embodiment of the application, positive bias voltage generated due to aging of a transistor or long-term operation of a driving circuit is obviously reduced, stress influence of the positive bias voltage on the transistor is avoided, display quality of the display panel is guaranteed, and display uniformity of the display panel is maintained for a long time.

The foregoing provides a detailed description of embodiments of the present application, and the principles and embodiments of the present application have been described herein using specific examples, which are presented solely to aid in the understanding of the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. A driver circuit, comprising:

2. The driving circuit according to claim 1, wherein the control module comprises a first transistor and a second transistor;

a gate of the first transistor is connected to a first control signal, one of a source and a drain of the first transistor is electrically connected to the second power supply, and the other of the source and the drain of the first transistor is electrically connected to the second node;

a gate of the second transistor is connected to a second control signal, one of a source and a drain of the second transistor is electrically connected to the second power supply, and the other of the source and the drain of the second transistor is electrically connected to the second node.

3. The driving circuit according to claim 2, wherein the preset timing period comprises at least two frame display periods; in an on period in any one of the display periods, the first transistor or the second transistor is turned on.

4. The driving circuit according to claim 3, wherein the preset timing period comprises a first display period and a second display period; the first display period is adjacent to the second display period; the first transistor is turned on during a turn-on period in the first display period, and the second transistor is turned on during a turn-on period in the second display period.

5. The driving circuit according to claim 3, wherein the preset timing period comprises a first display period, a second display period, and a third display period; the first display period, the second display period and the third display period are adjacent to each other;

6. The driving circuit according to claim 2, wherein the predetermined timing period is a frame display period; the one-frame display period includes a first on period and a second on period; one of the first transistor and the second transistor is turned on in the first on period; the other of the first transistor and the second transistor is turned on in the second conduction period.

7. The drive circuit according to claim 1,

the first initialization module comprises a third transistor, the grid electrode of the third transistor is connected with the first initialization control signal in an access mode, one of the source electrode and the drain electrode of the third transistor is connected with the first initialization signal in an access mode, and the other of the source electrode and the drain electrode of the third transistor is electrically connected with the first node;

8. The driving circuit according to claim 1, wherein in at least two of the transistors, the transistors are both N-type transistors or P-type transistors.

9. A display panel, comprising;

a data line for supplying a data signal;

a first initialization line for providing a first initialization signal;

a second initialization line for providing a second initialization signal;

a first scan line for providing a data control signal;

a second scan line for providing a first initialization control signal;

a third scan line for providing a second initialization control signal; and

the driver circuit according to any one of claims 1 to 8, which is electrically connected to the data line, the first initialization line, the second initialization line, the first scan line, the second scan line, and the third scan line.

10. A driving method of the display panel according to claim 9, comprising: