CN114361103A - Chip packaging structure and packaging method - Google Patents
Chip packaging structure and packaging method Download PDFInfo
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- CN114361103A CN114361103A CN202111666616.9A CN202111666616A CN114361103A CN 114361103 A CN114361103 A CN 114361103A CN 202111666616 A CN202111666616 A CN 202111666616A CN 114361103 A CN114361103 A CN 114361103A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
The invention discloses a chip packaging structure and a packaging method, relating to the technical field of semiconductors, wherein the chip packaging method comprises the following steps: providing a chip, wherein a plurality of chip pins are arranged on the chip; providing a substrate, wherein a plurality of first through holes are formed in the substrate corresponding to the chip pins, and the substrate pins are arranged on the inner wall of each first through hole and the edge of each first through hole on the surface of the substrate; connecting the substrate and the chip by using a connecting layer by adopting a surface mounting process so as to mount the chip on the substrate, wherein the pin of the chip corresponds to the first through hole; preparing a plastic packaging layer on the surface of one side of the chip, which is far away from the connecting layer, by adopting a plastic packaging process; removing the material at the position of the connecting layer corresponding to the first through hole so as to form a plurality of second through holes on the connecting layer; and filling fluid conductive substances into the first through hole and the second through hole and curing the fluid conductive substances so as to electrically connect the chip pin and the substrate pin. The chip packaging structure and the packaging method provided by the invention have low requirement on the shape of the interconnected micropores, and further can improve the electrical property and reliability of interconnection.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a chip packaging structure and a chip packaging method.
Background
As electronic devices have advanced, electronic devices have become smaller and lighter. Therefore, semiconductor packages used in electronic devices must also become smaller and lighter while still maintaining high reliability, high performance, and high capacity. The semiconductor chip is generally mounted on a printed circuit board (substrate) and electrically connected to the substrate using bonding wires or a connecting member.
In the chip packaging technology, a vertical interconnection process is involved when a semiconductor chip and a substrate are interconnected. The vertical interconnect process is typically accomplished by electroplating micro-holes. The electroplating technology has a complex process route and high requirements for the quality of the micropores, undercut regions exist in the formation process of the micropores, particularly irregular micropores, the electroplating technology is difficult to prepare a metal seed layer, electroplated metal is difficult to fill the undercut regions of the micropores, the electrical connection between the electroplated metal and the interconnection metal is affected, and the interconnection reliability risk exists.
Disclosure of Invention
The application aims to provide a chip packaging structure and a chip packaging method, which have low requirement on the shape of interconnected micropores and can further improve the electrical property and reliability of interconnection.
An embodiment of the present application provides a chip packaging method, including: providing a chip, wherein a plurality of chip pins are arranged on the chip; providing a substrate, wherein a plurality of first through holes are formed in the substrate corresponding to the chip pins, and the substrate pins are arranged on the inner wall of each first through hole and the edge of each first through hole on the surface of the substrate; connecting the substrate and the chip by using a connecting layer by adopting a surface mounting process so as to mount the chip on the substrate, wherein the pin of the chip corresponds to the first through hole; preparing a plastic packaging layer on the surface of one side of the chip, which is far away from the connecting layer, by adopting a plastic packaging process; removing the material at the position of the connecting layer corresponding to the first through hole so as to form a plurality of second through holes on the connecting layer; placing the fluid conductor in and/or above the first through hole by adopting silk-screen printing, steel seal, dispensing or ink-jet printing processes; promoting the transfer of the fluid conductor into the first through hole and the second through hole through vacuumizing and/or pressurizing so that the fluid conductor is tightly filled in the first through hole and the second through hole; and curing the fluid conductor to electrically connect the chip pins with the substrate pins.
As a practical way, the fluid conductor is a mixture of solid conductive particles and liquid organic material, and the fluid conductor has conductivity and rheological characteristics.
As an implementable manner, the curing conditions for curing the fluid conductor are: the curing temperature is between 80 and 300 ℃, and the curing time is between 0.5 and 180 min.
As one practical way, promoting the transfer of the fluid conductor into the first and second vias via evacuation and/or pressurization comprises: the fluid conductor fills the first and second vias, wherein the fluid conductor fills the second via, partially covers the first via, completely fills the first via, or overfills the first via.
As a practical manner, after providing the substrate, the chip packaging method further includes: and coating metal layers on the inner wall of the first through hole and the edge of the first through hole on the substrate in a chemical coating or physical coating mode to form a coverage through hole, wherein the metal layers cover the substrate pin.
As one practical way, the removing the material of the connection layer at the position corresponding to the first via to form the plurality of second vias includes: removing the material at the position of the connecting layer corresponding to the first through hole by adopting a dry etching or wet etching process; or removing the material at the position of the connecting layer and the first through hole by adopting a laser drilling or mechanical drilling process to form a second through hole.
As an implementable manner, the facilitating transfer of the fluid conductor into the first and second vias via an evacuation and/or pressurization process comprises: the fluid conductor fills the first through hole and the second through hole at once or at a proper ratio a plurality of times.
As a practical way, after filling the fluid conductor in the first through hole and the second through hole and curing, the chip packaging method further includes: and preparing an insulating layer on the surface of the substrate on the side far away from the connecting layer so as to cover the substrate and solidify the conductor.
Another aspect of the embodiments of the present application provides a chip package structure, including a chip provided with a plurality of pins, a connection layer, and a substrate, where the connection layer has a plurality of second through holes respectively corresponding to the pins, the substrate has a first through hole corresponding to the second through hole, the inner wall of the first through hole and the substrate at the edge are provided with substrate pins, the first through hole and the second through hole are filled with a conductive material, the substrate packages the chip through the connection layer, and the pins are electrically connected to the substrate pins through the conductive material.
As a practical way, the connection layer is made of a material having adhesive properties and insulating properties.
The beneficial effects of the embodiment of the application include:
the chip packaging method provided by the invention comprises the following steps: providing a chip, wherein a plurality of chip pins are arranged on the chip; providing a substrate, wherein a plurality of first through holes are formed in the substrate corresponding to the chip pins, and the substrate pins are arranged on the inner wall of each first through hole and the edge of each first through hole on the surface of the substrate; connecting the substrate and the chip by using a connecting layer by adopting a surface mounting process so as to mount the chip on the substrate, wherein the pin of the chip corresponds to the first through hole; removing the material at the position of the connecting layer corresponding to the first through hole so as to form a plurality of second through holes on the connecting layer; placing the fluid conductor in and/or above the first through hole by adopting silk-screen printing, steel seal, dispensing or ink-jet printing processes; promoting the transfer of the fluid conductor into the first through hole and the second through hole through vacuumizing and/or pressurizing so that the fluid conductor is tightly filled in the first through hole and the second through hole; the fluid conductive material is solidified to electrically connect the chip pin and the substrate pin, and compared with the method for filling the micropores by electroplating, the method for filling the substrate pin with the fluid conductive material has the advantages that the filling speed is higher, the efficiency is higher, the used equipment is relatively simple, and the cost is lower; moreover, the fluid conductive substance is filled, and the fluid conductive substance has certain fluidity, so that the fluid conductive substance can flow into the tiny gaps, and high-quality filling can be realized for irregular micropores, particularly for the micropores with undercuts, thereby improving the electrical performance and reliability of interconnection.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a flowchart of a chip packaging method according to an embodiment of the present disclosure;
fig. 2 is a state diagram of a chip package structure according to an embodiment of the present disclosure;
fig. 3 is a second state diagram of a chip package structure according to an embodiment of the present disclosure;
fig. 4 is a third state diagram of a chip package structure according to an embodiment of the present disclosure;
fig. 5 is a fourth state diagram of a chip package structure according to an embodiment of the present disclosure;
fig. 6 is a fifth state diagram of a chip package structure according to an embodiment of the present disclosure;
fig. 7 is a sixth state diagram of a chip packaging method according to an embodiment of the present application;
fig. 8 is a seventh state diagram of a chip package structure according to an embodiment of the present disclosure;
fig. 9 is an eighth state diagram of a chip package structure according to an embodiment of the present application;
fig. 10 is a ninth view illustrating a state of a chip package structure according to an embodiment of the present disclosure;
fig. 11 is a tenth view of a state diagram of a chip package structure according to an embodiment of the present application;
fig. 12 is an eleventh view illustrating a state of a chip package structure according to an embodiment of the disclosure;
fig. 13 is a twelfth state diagram of a chip package structure according to an embodiment of the present disclosure.
Icon: 110-chip; 111-chip pins; 120-a substrate; 121 — a first via; 122-substrate pins; 130-a tie layer; 131-a second via; 133-a metal layer; 140-plastic packaging layer; 150-an insulating layer; 160-fluid conductor.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the following embodiments, the semiconductor package may include an electronic device such as a semiconductor chip. The semiconductor chips can be obtained by separating a semiconductor substrate such as a wafer into a plurality of pieces using a dicing process. The semiconductor chip may correspond to a memory chip, a logic chip (including an Application Specific Integrated Circuit (ASIC) chip), or a system on a chip (SoC). The memory chip may include a Dynamic Random Access Memory (DRAM) circuit, a Static Random Access Memory (SRAM) circuit, a NAND-type flash memory circuit, a NOR-type flash memory circuit, a Magnetic Random Access Memory (MRAM) circuit, a resistive random access memory (ReRAM) circuit, a ferroelectric random access memory (FeRAM) circuit, or a phase change random access memory (PcRAM) circuit integrated on a semiconductor substrate. The logic chip may include logic circuitry integrated on a semiconductor substrate. The semiconductor chip may be referred to as a semiconductor die.
The semiconductor package may include a printed circuit on which the semiconductor chip is mounted. The printed circuit may include at least one layer of integrated circuit patterns and may be referred to as a substrate in this specification. Connection techniques may be used for communication between the package substrate and the semiconductor chip.
The semiconductor package may be used in various communication systems such as mobile phones, electronic systems associated with biotechnology or healthcare, or wearable electronic systems.
The existing connection technology for connecting the packaging substrate and the semiconductor chip generally adopts a connection layer arranged between the packaging substrate and the semiconductor chip, micropores are formed on the connection layer, and electroplating metal materials are electroplated in the micropores by adopting an electroplating process so as to connect the pins of the packaging substrate and the pins of the semiconductor chip.
The invention provides a method for packaging a chip 110, as shown in fig. 1, comprising the following steps:
s110, providing a chip 110, wherein as shown in FIG. 2, a plurality of chip pins 111 are arranged on the chip 110;
the plurality of chip leads 111 are disposed on the same side of the chip 110, the side of the chip 110 where the chip leads 111 are disposed is a functional surface, and the side where the chip leads 111 are not disposed is a non-functional surface.
And S120, providing a substrate 120, wherein as shown in FIG. 3, a plurality of first through holes 121 are arranged on the substrate 120 corresponding to the chip pins 111, and substrate pins 122 are arranged in the first through holes 121 and at the edges of the first through holes 121 on the surface of the substrate 120.
The substrate pins 122 may be disposed on the inner wall of the first through hole 121 and the substrate 120 at the edge of the first through hole 121 on the surface of the substrate 120, and the disposition of the substrate pins 122 may be classified into three cases: in the first case, as shown at a in fig. 3, the substrate pin 122 includes a metal disposed at an inner wall of the first through hole 121 and an edge of the first through hole 121 at one side of the substrate 120; in the second case, as shown at B in fig. 3, the substrate pin 122 includes a metal disposed at an inner wall of the first through-hole 121 and an edge of the first through-hole 121 at the other side of the substrate 120; in the third case, the substrate pin 122 includes metal disposed on the inner wall of the first through-hole 121 and the edges of the first through-hole 121 at both sides of the substrate 120.
The chip pins 111 correspond to the first through holes 121, which means that the plurality of pins respectively correspond to the plurality of first through holes 121 one by one, and the position arrangement of the plurality of chip pins 111 is the same as the position arrangement of the first through holes 121.
S130, as shown in FIG. 4, a chip mounting process is adopted, the substrate 120 and the chip 110 are connected by using the connection layer 130, so that the chip 110 is mounted on the substrate 120, and the chip pins 111 correspond to the first through holes 121.
When the connection layer 130 connects the substrate 120 and the chip 110, the connection layer 130 is disposed on the functional surface of the chip 110, and then the substrate 120 is disposed on the connection layer 130, and when the substrate 120 is disposed on the connection layer 130, attention needs to be paid to aligning the first through holes 121 with the chip pins 111.
S140: as shown in fig. 5, a molding process is used to prepare a molding layer 140 on a side of the chip away from the connection layer.
In order to avoid the chip 110 from being rubbed and collided by the outside, the molding layer 140 is prepared on the surface of one side of the chip 110 away from the connecting layer 130, that is, the molding layer 140 is prepared on the non-functional surface of the chip 110, the molding layer 140 has certain rigidity and can play a certain role in protecting the chip 110, and the molding layer 140 is made of a molding material which has certain insulativity and can play a role in preventing the chip 110 from being damaged by static electricity in the environment.
And S150, as shown in FIG. 6, removing the material of the connection layer 130 at the position corresponding to the first via hole 121 to form a plurality of second via holes 131 on the connection layer 130.
When the substrate 120 is connected to the chip 110 by using the connection layer 130, the connection layer 130 is disposed on the functional surface of the chip 110, such that the connection layer 130 covers the chip pins 111, in order to expose the chip pins 111, the connection layer 130 on the chip pins 111 needs to be removed, and the chip pins 111 are disposed corresponding to the first through holes 121, such that the material of the connection layer 130 at the positions corresponding to the first through holes 121 needs to be removed and the second through holes 131 need to be formed.
And S160, placing the fluid conductor in and/or above the first through hole by adopting silk-screen printing, steel seal, dispensing or ink-jet printing processes.
Wherein, silk screen printing adopts the silk screen to carry out, and the embossed seal adopts the steel mesh to carry out, and the structure of silk screen or steel mesh sets up according to the position of a plurality of first through-holes 121 for fluid conductor 160 only exists in the top of first through-hole 121.
And S170, as shown in the figures 7, 8 and 9, promoting the transfer of the fluid conductor into the first through hole 121 and the second through hole 131 through vacuum pumping and/or pressurization so that the fluid conductor 160 tightly fills the first through hole 121 and the second through hole 131.
When the fluid conductor 160 is placed above the first through hole 121, the first through hole 121 and the second through hole 131 are vacuumized, so that a negative pressure is formed at the opening of the first through hole 121, and the fluid conductor 160 is transferred to the first through hole 121 and the second through hole 131, and in order to enable the fluid conductor 160 to densely fill the first through hole 121 and the second through hole 131, the fluid conductor 160 is pressed.
It should be noted that, in the embodiments and/or the fingers of the present invention, both may be performed as separate embodiments, or may be performed in both manners. Specifically, the vacuum pumping and/or the pressurization can be performed by adopting the vacuum pumping alone, the pressurization mode, or the vacuum pumping and the pressurization mode simultaneously.
And S180, curing the fluid conductor 160 to electrically connect the chip pins 111 with the substrate pins 122.
Curing the fluid conductor 160 causes the fluid conductor 160 to cure into a fixed shape to achieve the connection of the substrate pins 122 and the chip pins 111. Since the fluid conductor 160 is still in a fluid state after filling the first and second through holes 121 and 131, the fluid conductor is easy to flow out of the first through hole 121, so that the fluid conductor 160 in the first through hole 121 is reduced, and the substrate pin 122 is not successfully communicated with the chip pin 111.
The package of the chip 110 is mainly to lead out an electrical signal on the chip 110, when the chip pin 111 is communicated with the substrate pin 122, the electrical signal on the chip 110 can be transmitted to the substrate 120, the first through hole 121 and the second through hole 131 are filled with the fluid conductor 160 and cured, the cured fluid conductor 160 is called as a cured conductor, because the substrate pin 122 is arranged on the substrate 120 at the inner wall and the edge of the first through hole 121, the chip pin 111 is exposed through the first through hole 121, and when the first through hole 121 and the second through hole 131 are filled with the solid conductor, the solid conductor connects the chip pin 111 with the substrate pin 122, so that the substrate 120 and the chip 110 communicate with each other.
It should be noted that the first through hole 121 and the second through hole 131 serve as connection holes for the chip pin 111 and the substrate pin 122, and the chip pin 111 and the substrate pin 122 are interconnected after being filled with the fluid conductor 160, which actually belongs to a micro-porous structure.
The specific material of the molding layer 140 is not limited in the present invention, and may be epoxy resin, polyimide, silica gel, etc. It should be noted that, in order to protect the chip 110 completely, the outer periphery of the molding layer 140 may extend toward the side of the chip 110 and be combined with the connection layer 130, so as to enclose the chip 110 between the molding layer 140 and the connection layer 130.
The chip 110 packaging method provided by the invention comprises the following steps: providing a chip 110, wherein a plurality of chip pins 111 are arranged on the chip 110; providing a substrate 120, wherein a plurality of first through holes 121 are formed in the substrate 120 corresponding to the chip pins 111, and substrate pins 122 are formed on the inner walls of the first through holes 121 and the edges of the first through holes 121 on the surface of the substrate 120; a chip mounting process is adopted, the substrate 120 is connected with the chip 110 by using the connecting layer 130, so that the chip 110 is mounted on the substrate 120, and the chip pin 111 corresponds to the first through hole 121; removing the material of the connection layer 130 at the position corresponding to the first via hole 121 to form a plurality of second via holes 131 on the connection layer 130; placing the fluid conductor 160 in and/or over the first via 121 using a screen printing, steel stamping, dispensing, or ink jet printing process; facilitating the transfer of the fluid conductor 160 into the first and second vias 121 and 131 by evacuation and/or pressurization such that the fluid conductor 160 tightly fills the first and second vias 121 and 131; the fluid conductive material 160 is solidified to electrically connect the chip pin 111 and the substrate pin 122, and compared with the method for filling the micropores by electroplating, the method for filling the fluid conductive material 160 into the first through hole 121 and the second through hole 131 has the advantages of higher filling speed, higher efficiency, simpler used equipment and lower cost; moreover, with the filling of the fluid conductor 160, since the fluid conductor 160 has a certain fluidity, so that the fluid conductor 160 can flow into the tiny gaps, the filling with high quality can be realized for the irregular micropores, especially the micropores with undercut, thereby improving the electrical performance and reliability of the interconnection.
In one way of accomplishing this embodiment of the present invention, the fluid conductor 160 is a mixture of solid conductive particles and a liquid organic material, the fluid conductor having both conductivity and rheological properties.
The conductive particles are used for electrically connecting the chip pins 111 with the substrate pins 122 to realize transmission between the chip 110 and the substrate 120, the liquid organic material is used as a flowing carrier of the flowing conductive object, so that the flowing conductive object has fluidity and can be filled in the first through holes 121 and the second through holes 131, and the liquid organic material drives the conductive particles to be filled in the first through holes 121 and the second through holes 131 due to the adoption of a vacuumizing and pressurizing mode.
The present invention is not limited to the specific material of the fluid conductor 160, and for example, the fluid conductor 160 may be a material having conductive properties, such as silver paste, aluminum paste, copper paste, carbon paste, and solder paste. The liquid organic material recipe is not particularly limited, and the liquid organic material may be a volatile solvent with a low boiling point or a nonvolatile solvent with a high boiling point.
For the volatile solvent with low boiling point, the liquid organic material is volatilized in a high temperature environment during the curing process of the fluid conductor 160, wherein the liquid organic material is used as the solvent and does not affect the transmission of the electrical signal of the conductive particles after being volatilized. And for the solvent with high boiling point and difficult volatilization, the solvent is solidified and forms a solidified conductor with the conductive particles in a high-temperature environment.
In an implementation manner of the embodiment of the present invention, the curing conditions for curing the fluid conductor 160 are as follows: the curing temperature is between 80 and 300 ℃, and the curing time is between 0.5 and 180 min.
In order to rapidly cure the fluid conductor 160, the curing process may be performed at a high temperature, specifically at a temperature of 80-300 ℃, because the high temperature can promote the solvent of the fluid conductor 160 to volatilize, thereby increasing the curing rate, and the curing time is 0.5-180min, wherein the curing apparatus is not limited in the present invention, and may be an oven.
Alternatively, as shown in fig. 7, 8 and 9, the step of promoting the fluid conductor 160 to enter the first through hole 121 and the second through hole 131 by vacuum and/or pressurization comprises: the fluid conductor 160 fills the first via 121 and the second via 131, wherein the fluid conductor 160 fills the second via 131, and the fluid conductor 160 partially covers the first via 121, completely fills the first via 121, or overfills the first via 121.
The fluid conductor 160 fills the second through hole 131 to lead out the chip pin 111, and for filling the first through hole 121, partial filling, complete filling or overfilling can be selected according to actual conditions, as long as the fluid conductor 160 can be ensured to be in contact with the substrate pin 122. Fig. 7 shows the fluid conductor 160 partially filling the first through hole 121, fig. 8 shows the fluid conductor 160 completely filling the first through hole 121, and fig. 9 shows the fluid conductor 160 overfilling the first through hole 121.
In an implementation manner of the embodiment of the present invention, as shown in fig. 11, after providing the substrate 120, the chip 110 packaging method further includes:
and S121, coating a metal layer 133 on the inner wall of the first through hole 121 and the edge of the first through hole 121 on the substrate by adopting an electroless plating or physical plating mode to form a plated through hole, wherein the metal layer 133 covers the substrate pin 122.
PTH (plated-through hole), a conductor electrically connects the chip pin 111 and the substrate pin 122 through the plated through hole. The material of the metal layer 133 is not particularly limited in the present invention, and may be formed by plating a metal such as copper (Cu), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), or an alloy thereof in the first through hole 121.
As shown in fig. 12, the substrate 120 with the through holes formed thereon is bonded to the chip 110 by using the connection layer 130 through a bonding process, so as to attach the chip 110 to the substrate 120, and then the second through hole 131 is formed by removing the connection layer 130 and filling the first through hole 121 and the second through hole 131, so as to form a package structure, as shown in fig. 13.
Optionally, removing the material of the connection layer 130 at the position corresponding to the first through hole 121 includes: removing the material at the position of the connecting layer 130 corresponding to the first through hole 121 by adopting a dry etching or wet etching process; or removing the material at the position of the connection layer 130 and the first via 121 by using a laser drilling or mechanical drilling process to form the second via 131.
The material of the connection layer 130 may be photoresist, a dry film, a DAF film, a chip adhesive, a liquid crystal polymer, resin, etc., so that the material at the position of the connection layer 130 corresponding to the first through hole 121 may be removed by an etching process or a punching process, wherein the punching process may be performed by a mechanical punching manner or a laser punching manner. A person skilled in the art may select a suitable material of the connection layer 130 and a suitable process to remove the material at the position of the connection layer 130 corresponding to the first through hole 121 according to actual conditions, for example, when the material of the connection layer 130 is a photoresist, an etching process may be adopted, and the etching is performed through exposure and development of a mask.
In an implementable manner of the embodiments of the invention, facilitating transfer of the fluid conductor into the first via and the second via a method of evacuation and/or pressurization comprises: the fluid conductor can be used for filling the first through hole and the second through hole at one time or can be divided into a plurality of parts to be filled into the first through hole and the second through hole in a proper proportion.
The specific filling times and proportion can be set according to actual conditions, the invention is not particularly limited, and for example, the filling can be carried out in three times, and the volume sum of the first through hole and the second through hole is 33% each time.
Optionally, as shown in fig. 10, after the fluid conductor 160 is filled in the first via 121 and the second via 131 and cured, the chip 110 packaging method further includes:
and S151, preparing an insulating layer 150 on the surface of the substrate 120 on the side far away from the connecting layer 130 so as to cover the substrate 120 and solidify the conductor.
After the substrate 120 is connected to the chip 110, in the process of use or transportation, there may be a situation of collision or bumping, which may cause physical damage to the package structure, and there may also be a situation of rubbing to generate static electricity, and the static electricity has a great influence on the performance of the chip 110.
Here, the specific material of the insulating layer 150 is not limited in the present invention as long as the protective function and the antistatic property can be satisfied at the same time. The material of the molding layer 140 may be the same or different.
Another aspect of the present disclosure provides a chip 110 package structure, as shown in fig. 10 and 13, including a chip 110 having a plurality of pins, a connection layer 130 and a substrate 120, where the connection layer 130 has a plurality of second through holes 131 respectively corresponding to the pins, the substrate 120 has a first through hole 121 corresponding to the second through hole 131, the substrate 120 has a substrate pin 122 on an inner wall and an edge of the first through hole 121, the first through hole 121 and the second through hole 131 are filled with a conductive material, the substrate 120 packages the chip 110 through the connection layer 130, and the pin is electrically connected to the substrate pin 122 through the conductive material.
The first through hole 121 and the second through hole 131 can be filled with a conductive material, because the second through hole 131 is formed in the connection layer 130 corresponding to the pin, after the conductive material is filled in the second through hole 131, the conductive material is connected with the pin, the substrate pins 122 are arranged on the inner wall of the first through hole 121 and the substrate 120 at the edge, and after the conductive material is filled in the first through hole 121, the conductive material is connected with the substrate pins 122, so that the substrate pins 122 are connected with the pin.
To further protect the chip 110 and the substrate 120, an encapsulation layer may be disposed on the outer side surfaces of the substrate 120 and the chip 110.
In one achievable form of an embodiment of the invention, the connecting layer 130 is made of a material having adhesive and insulating properties.
The connection layer 130, serving as a connection structure between the substrate 120 and the chip 110, should have a certain viscosity, so that the substrate 120 and the chip 110 are fixedly connected to achieve the effect of packaging the chip 110, and serving as an intermediate layer between the substrate 120 and the chip 110, the second through hole 131 formed in the connection layer 130 is filled with a conductive material to electrically connect the substrate pin 122 and the pin.
The specific material of the connection layer 130 is not limited in the present invention, and may be photoresist, dry film, DAF film, adhesive, liquid crystal polymer, resin, etc., as long as the substrate 120 and the chip 110 are connected and no current is conducted, that is, the substrate has both adhesive property and insulating property.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A method of chip packaging, comprising:
providing a chip, wherein a plurality of chip pins are arranged on the chip;
providing a substrate, wherein a plurality of first through holes are formed in the substrate corresponding to the chip pins, and substrate pins are arranged on the inner wall of each first through hole and the edge of each first through hole on the surface of the substrate;
connecting the substrate and the chip by using a connecting layer by adopting a surface mounting process so as to mount the chip on the substrate, wherein the chip pin corresponds to the first through hole;
preparing a plastic packaging layer on the surface of one side, far away from the connecting layer, of the chip by adopting a plastic packaging process;
removing materials at the positions of the connecting layer corresponding to the first through holes so as to form a plurality of second through holes on the connecting layer;
placing the fluid conductor in and/or above the first through hole by adopting a silk-screen printing, steel seal, dispensing or ink-jet printing process;
facilitating transfer of a fluid conductor into the first and second vias via evacuation and/or pressurization such that the fluid conductor closely fills the first and second vias;
and curing the fluid conductor to electrically connect the chip pins with the substrate pins.
2. The chip packaging method according to claim 1, wherein the fluid conductor is a mixture of solid conductive particles and a liquid organic material, and the fluid conductor has conductivity and rheological properties.
3. The chip packaging method according to claim 1, wherein the curing conditions for curing the fluid conductor are as follows:
the curing temperature is between 80 and 300 ℃, and the curing time is between 0.5 and 180 min.
4. The chip packaging method according to claim 1, wherein the promoting the transfer of the fluid conductor into the first and second vias by evacuation and/or pressurization comprises:
the fluid conductor fills the first and second vias, wherein the fluid conductor fills the second via, partially covers the first via, completely fills the first via, or overfills the first via.
5. The chip packaging method according to claim 1, wherein after the providing the substrate, the method further comprises:
and coating metal layers on the inner wall of the first through hole and the edge of the first through hole on the substrate in a chemical coating or physical coating mode to form a plated through hole, wherein the metal layers cover the substrate pins.
6. The chip packaging method according to claim 1, wherein the removing material of the connection layer at a position corresponding to the first via to form a plurality of second vias comprises:
and removing the material at the position of the connecting layer corresponding to the first through hole by adopting a dry etching or wet etching process, or removing the material at the position of the connecting layer corresponding to the first through hole by adopting a laser drilling or mechanical drilling process to form the second through hole.
7. The chip packaging method according to claim 1, wherein the promoting the transfer of the fluid conductor into the first and second vias via an evacuation and/or pressurization method comprises: the fluid conductor fills the first through hole and the second through hole at one time or fills the first through hole and the second through hole at a plurality of times in an appropriate ratio.
8. The chip packaging method according to claim 1, wherein after the filling and curing of the fluid conductor in the first and second vias, the method further comprises:
and preparing an insulating layer on the surface of one side of the substrate, which is far away from the connecting layer, so as to cover the substrate and the solidified conductor.
9. A chip packaging structure is characterized by comprising a chip provided with a plurality of pins, a connecting layer and a substrate, wherein the connecting layer is provided with a plurality of second through holes corresponding to the pins respectively, the substrate is provided with first through holes corresponding to the second through holes, substrate pins are arranged on the inner wall of each first through hole and the substrate at the edge of each first through hole, conductive objects are filled in the first through holes and the second through holes, the substrate packages the chip through the connecting layer, and the pins are electrically connected with the substrate pins through the conductive objects.
10. The chip package structure according to claim 9, wherein the connection layer is made of a material having adhesive and insulating properties.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111666616.9A CN114361103A (en) | 2021-12-31 | 2021-12-31 | Chip packaging structure and packaging method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111666616.9A CN114361103A (en) | 2021-12-31 | 2021-12-31 | Chip packaging structure and packaging method |
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| CN114361103A true CN114361103A (en) | 2022-04-15 |
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| CN202111666616.9A Pending CN114361103A (en) | 2021-12-31 | 2021-12-31 | Chip packaging structure and packaging method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115332094A (en) * | 2022-08-08 | 2022-11-11 | 浙江亚芯微电子股份有限公司 | Five-chip packaging method |
| CN115377015A (en) * | 2022-08-29 | 2022-11-22 | 北京超材信息科技有限公司 | Packaging structure of electronic device and manufacturing method |
-
2021
- 2021-12-31 CN CN202111666616.9A patent/CN114361103A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115332094A (en) * | 2022-08-08 | 2022-11-11 | 浙江亚芯微电子股份有限公司 | Five-chip packaging method |
| CN115332094B (en) * | 2022-08-08 | 2023-09-05 | 浙江亚芯微电子股份有限公司 | Five-chip packaging method |
| CN115377015A (en) * | 2022-08-29 | 2022-11-22 | 北京超材信息科技有限公司 | Packaging structure of electronic device and manufacturing method |
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