CN114361055A - Power circuit packaging structure and packaging method thereof - Google Patents
Power circuit packaging structure and packaging method thereof Download PDFInfo
- Publication number
- CN114361055A CN114361055A CN202111671525.4A CN202111671525A CN114361055A CN 114361055 A CN114361055 A CN 114361055A CN 202111671525 A CN202111671525 A CN 202111671525A CN 114361055 A CN114361055 A CN 114361055A
- Authority
- CN
- China
- Prior art keywords
- copper
- metal base
- sub
- base island
- polyimide layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/14181—On opposite sides of the body
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a power circuit packaging structure, which comprises a plastic package body, an IC control chip on the plastic package body, a first metal base island and a second metal base island on two sides of the IC control chip, connect the MOS switch chip of IC control chip and first metal base island, set up first polyimide layer on the MOS switch chip, IC control chip sets up the second polyimide layer, MOS switch chip sets up the first copper post on first polyimide layer, the first copper billet perpendicular with first copper post and with the laminating of first metal base island, the outside first pin that extends of first metal base island, run through second copper post and the second copper billet on first polyimide layer and second polyimide layer, be provided with on the IC control chip and be located third copper post between the second copper post, the third copper billet perpendicular with third copper post and with the laminating of second metal base island, the second metal base island is connected with outside second pin. The invention also provides a power circuit packaging method, which greatly reduces power consumption and improves working frequency.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a packaging structure and a packaging method of a power circuit.
Background
The main components of a power circuit include a power switch, an Integrated Circuit (IC), a protection device and a passive device. Among them, the power switch is usually a metal Oxide Semiconductor Field Effect Transistor (MOSFET for short) or an Insulated Gate Bipolar Transistor (IGBT for short). The IC may be a driver chip or a PWM control chip, or a combination of both. The MOSFET is used as a switch and is controlled by the IC to complete the pulse width modulation of the input power supply, and the voltage required by the load is output through the passive device.
At present, the mainstream packaging method of the power circuit mainly adopts the mode that the MOSFET, the IC and the passive devices are packaged in the same package body in a centralized mode, and various devices are interconnected through the metal base island and the metal lead wire inside the package body so as to achieve the circuit function. Due to the characteristics of the switching power supply, a large current needs to be transferred, and the parasitic resistance and parasitic inductance of the whole power supply circuit are obviously increased by the lead wires between the devices, so that the current density and the switching frequency of the circuit are influenced.
Disclosure of Invention
In view of the above, the present invention provides a power circuit package structure with low parasitic resistance and low parasitic inductance and capable of improving circuit integration and a package method thereof, so as to solve the above technical problems, and the present invention is specifically implemented by the following technical solutions.
In a first aspect, the present invention provides a power circuit package structure, which includes a plastic package body, an IC control chip located on the plastic package body, first metal base islands located on two sides of the IC control chip, second metal base islands connected to the IC control chip, and an MOS switch chip connected to the IC control chip and the first metal base islands, wherein a first polyimide layer is disposed on an upper surface of the MOS switch chip, a second polyimide layer is disposed on a lower surface of the IC control chip, first copper pillars penetrating through the first polyimide layer and arranged at intervals, first copper blocks perpendicular to the first copper pillars and attached to a first end surface of the first metal base islands, first pins extending outward from a second end surface of the first metal base islands, and second copper pillars, arranged at intervals, penetrating through the first polyimide layer and the second polyimide layer, are disposed on another side of the MOS switch chip, And a second copper block which is vertical to the second copper column and is positioned between the first polyimide layer and the second polyimide layer, a third copper column which is positioned between the second copper columns and penetrates through the second polyimide layer and a third copper block which is vertical to the third copper column and is attached to one end of the second metal base island are arranged on the IC control chip, and a second pin which extends outwards is connected to the other end of the second metal base island.
In a second aspect, the present invention further provides a power circuit packaging method, including the following steps:
coating a polyimide layer on the upper surfaces of two MOS switch chips, removing polyimide at a lead window of the chips to form a first polyimide layer, implanting copper balls for growing to form first copper columns penetrating through the first polyimide layer in an interval arrangement mode and first sub-copper columns positioned on the other side of the MOS switch chips, coating a layer of metal on the first copper columns and the first sub-copper columns, removing redundant metal, and forming a first copper block positioned on the first copper columns and a first sub-copper block positioned on the first sub-copper columns;
forming a second polyimide layer, second sub-copper columns penetrating through the second polyimide layer and arranged at intervals, third copper columns located between the second sub-copper columns, second sub-copper blocks perpendicular to the second sub-copper columns and third copper blocks perpendicular to the third copper columns on the surface of an IC control chip;
the method comprises the following steps that a metal frame, two first metal base islands fixedly connected with the metal frame and a second metal base island located between the first metal base islands are adopted, so that first copper blocks of two MOS switch chips are connected with the bottom surfaces of the first metal base islands through conductive silver adhesive, the first metal base islands are connected with first pins, and the second metal base islands are connected with second pins;
turning the IC control chip for 180 degrees and connecting the IC control chip with the second metal base island through silver adhesive, wherein the IC control chip is arranged between the first metal base islands, the MOS switch chips are symmetrically arranged on two sides of the IC control chip, the first sub copper block is connected with the second sub copper block, the third copper block is connected with the second metal base island, the first sub copper block and the second sub copper block are thermally bonded to form a second copper block, and the first sub copper column is thermally bonded with the second copper column to form a second copper column;
and cutting off the metal frame, and filling and sealing the plastic package body to obtain the power circuit packaging structure.
The invention provides a power circuit packaging structure and a packaging method thereof, and compared with the prior art, the power circuit packaging structure has the following beneficial effects:
coating a polyimide layer on the upper surfaces of two MOS switch chips, removing the polyimide at the lead window of the chips to form a first polyimide layer, implanting copper balls for growth to form first copper columns penetrating through the first polyimide layer in interval arrangement and first sub-copper columns positioned on the other side of the MOS switch chips, coating a layer of metal on the first copper columns and the first sub-copper columns and removing redundant metal to form first copper blocks positioned on the first copper columns and first sub-copper blocks positioned on the first sub-copper columns, forming a second polyimide layer on the surface of an IC control chip, second sub-copper columns penetrating through the second polyimide layer in interval arrangement, third copper columns positioned between the second sub-copper columns, second sub-copper blocks perpendicular to the second sub-copper columns and third copper blocks perpendicular to the third copper columns, connecting the IC control chip with the two MOS switch chips by thermal bonding, the two metal base islands are respectively connected with the two MOS switch chips, and the two MOS switch chips and the IC control chip are precisely and skillfully attached together in a small size range, so that the whole circuit has extremely low transmission resistance and extremely low parasitic inductance, the power consumption is greatly reduced, and the working frequency is improved. Meanwhile, the volume of the whole packaging body is reduced, so that the circuit has a smaller appearance, and the application scene is greatly widened.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a flowchart of a power circuit packaging method according to an embodiment of the present invention;
fig. 2 to fig. 6 are process diagrams of a power circuit packaging method according to an embodiment of the invention;
fig. 7 is a schematic structural diagram of a power circuit package structure according to an embodiment of the invention.
The main element symbols are as follows:
10-power circuit package structure; 11-a plastic package body; 12-IC control chip; 13-a first metal base island; 14-a second metal base island; 15-MOS switch chip; 16-a first polyimide layer; 17-a second polyimide layer; 18-a first copper pillar; 19-a first copper block; 20-a second copper pillar; 21-a first sub-copper pillar; 22-a second sub-copper pillar; 23-a second copper block; 24-a first sub-copper block; 25-a second sub-copper block; 26-a third copper pillar; 27-a third copper block; 28-first pin; 29-a second pin; 30-metal frame.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Referring to fig. 1, 2 to 6, the present invention further provides a power circuit packaging method, including the following steps:
s1: coating a polyimide layer on the upper surfaces of two MOS switch chips 15, removing the polyimide at the lead windows of the chips to form a first polyimide layer 16, implanting copper balls for growing to form first copper columns 18 which penetrate through the first polyimide layer 16 and are arranged at intervals and first sub-copper columns 21 which are positioned on the other side of the MOS switch chips 15, covering a layer of metal on the first copper columns 18 and the first sub-copper columns 21, and removing redundant metal to form first copper blocks 19 positioned on the first copper columns 18 and first sub-copper blocks 24 positioned on the first sub-copper columns 21;
referring to fig. 2, in this embodiment, the MOS switch chip 15 is a commonly used mosfet, the MOS transistor is a semiconductor device in which unipolar carriers participate in conduction, and is divided into an N channel and a P channel according to carriers of a conduction channel, the N channel is the channel if the carriers of the conduction channel are electrons, the P channel is the channel if the carriers of the conduction channel are holes, and the conduction channel of the MOS transistor is formed in a manufacturing process, or formed by turning on an external power supply, and when a gate voltage is equal to zero, the channel is a depletion type, and when an external voltage is applied, the channel is an enhancement type, and is divided into a P channel enhancement type MOS transistor, a P channel depletion type MOS transistor, an N channel enhancement type MOS transistor, and an N channel korean star MOS transistor according to a process of forming the conduction channel. Polyimide is a polymer containing imide rings on a main chain, can resist high temperature of more than 400 ℃, can be used as photoresist comprising negative glue and positive glue, can be used as a dielectric layer for interlayer insulation in a microelectronic device, or can be used as a buffer layer for reducing stress and improving yield, or can be used as a protective layer for reducing the influence of the environment on the device, and the like.
It should be noted that, firstly, a layer of insulating film, i.e. polyimide, is coated on the surfaces of the two MOS switch chips 15, which has good insulating property and is beneficial to reducing stress, then the polyimide at the lead window of the chip is removed to form a groove (not shown), copper balls are implanted into the groove and metal growth is performed, first copper pillars 18 and first sub-copper pillars 21 which are arranged at intervals are formed on the first polyimide layer 16, the first copper pillars 18 and the first sub-copper pillars 21 are respectively located at two sides of the MOS switch chip 15, the first sub-copper pillars 21 have the same length but different diameters, and subsequent thermal bonding is facilitated. And covering a layer of copper on the upper surfaces of the first copper columns 18 and the first sub-copper columns 21, and removing the redundant copper, wherein the first copper blocks 19 completely cover each first copper column 18 for a whole block, and a gap exists between the first sub-copper blocks 24, namely the first sub-copper blocks 24 and the first sub-copper columns 21 are in a T shape, so that the subsequent thermal bonding with the IC control chip 12 is facilitated. The other MOS switch chip 15 has a structure corresponding to the other MOS switch chip, but the left side is a small first sub-copper block 24, and the right side is a large first copper block 19.
S2: forming a second polyimide layer 17, second sub-copper pillars 22 penetrating through the second polyimide layer 17 and arranged at intervals, third copper pillars 26 located between the second sub-copper pillars 22, second sub-copper blocks 25 perpendicular to the second sub-copper pillars 22, and third copper blocks 27 perpendicular to the third copper pillars 26 on the surface of the IC control chip 12;
referring to fig. 3, in the present embodiment, the IC control chip 12 is also processed by the above step S1, a layer of polyimide is first coated on the surface thereof, then the excess polyimide is removed to form the second polyimide layer 17, the second polyimide layer 17 and the first polyimide layer 16 may have the same thickness and both may serve as insulating layers, then the second sub-copper pillars 22 located on both sides of the surface of the IC control chip 12 and the second sub-copper blocks 25 located on the second sub-copper pillars 22 are fabricated, the second sub-copper pillars 22 and the second sub-copper blocks 25 are respectively disposed corresponding to the first sub-copper pillars 21 and the first sub-copper blocks 24, that is, the number is the same as the number of each copper pillar or the distance between the copper blocks, the third copper pillars 26 penetrating through the second polyimide layer 17 and the third copper blocks 27 located on the third copper pillars 26 are fabricated between the two second sub-copper pillars 22, the third copper pillars 26 and the second sub-copper pillars 22 are located on the same horizontal line, and the second sub-copper block 25 and the third copper block 27 are also located on the same horizontal line, i.e. corresponding structures on the IC control chip 12 are made for subsequent interconnection.
S3: by adopting a metal frame 30, two first metal base islands 13 fixedly connected with the metal frame 30 and a second metal base island 14 positioned between the first metal base islands 13, the first copper blocks 19 of the two MOS switch chips 15 are connected with the bottom surfaces of the first metal base islands 13 through conductive silver adhesive, the first metal base islands 13 are connected with first pins 28, and the second metal base island 14 is connected with second pins 29;
referring to fig. 4, in the present embodiment, the metal frame 30 has a T shape, the cross-sectional area of the first metal base island 13 is larger than that of the first copper block 19, and the cross-sectional area of the second metal base island 14 is larger than that of the third copper block 27. The method adopts a proper metal frame 30 and three metal base islands, namely two first metal base islands 13 are positioned at two sides of the metal frame 30, a second metal base island 14 is positioned between the two first metal base islands 13, the metal frame 30 and the metal base islands are fixed together, so that two MOS switch chips 15 are connected with the bottom surfaces of the metal base islands through conductive silver adhesive, the conductive silver adhesive combines conductive particles together through the adhesion effect of basic resin to form a conductive path, the conductive connection of adhered materials is realized, and the proper curing temperature can be selected for adhesion. The bottom surface of the first metal base island 13 is attached to the first copper block 19, the surface of the first metal base island 13 extending along the horizontal direction is connected with the first pin 28, one end of the second metal base island 14 is connected with the metal frame 30, the other end of the second metal base island is connected with the second pin 29, the two MOS switch chips 15 are symmetrically arranged relative to the second metal base island 14, and the metal frame 30 and the metal base island can improve the packaging efficiency of the power circuit and the working reliability of the chips.
S4: turning the IC control chip 12 by 180 degrees and connecting the IC control chip with the second metal base island 14 through conductive silver adhesive, wherein the IC control chip 12 is arranged between the first metal base islands 13, the MOS switch chips 15 are symmetrically arranged at two sides of the IC control chip 12, the first sub copper block 24 is connected with the second sub copper block 25, the third copper block 27 is connected with the second metal base island 14, the first sub copper block 24 and the second sub copper block 25 are thermally bonded to form a second copper block 23, and the first sub copper column 21 and the second copper column 22 are thermally bonded to form a second copper column 20;
referring to fig. 5, in this embodiment, the number of the first copper pillars 18 and the number of the second copper pillars 20 are both three, the number of the third copper pillars 26 is one, the thicknesses of the first copper blocks 19, the second copper blocks 23 and the third copper blocks 27 are the same, the height of the second metal base island 14 is smaller than the height of the first metal base island 13, and the second metal base island 14, the first copper pillars 18 and the first sub-copper pillars 21 are located on the same horizontal line. The height of the first copper column 18 is smaller than that of the second copper column 20, the height of the third copper column 26 is also smaller than that of the second copper column 20, the first copper block 19 is respectively attached to the first polyimide layer 16 and the first metal base island 13, the second copper block 23 is respectively attached to the first polyimide layer 16 and the second polyimide layer 17, and the third copper block 27 is respectively attached to the second polyimide layer 17 and the second metal base island 14, so that the stability of the packaging structure is improved.
It should be noted that, first, the IC control chip 12 is turned over 180 °, the surface of the chip, that is, the surface with the second sub-copper pillar 22 and the second sub-copper block 25, faces downward, and then is connected to the first metal base island 13 and the second metal base island 14 through the conductive silver paste, and meanwhile, both sides of the IC control chip 12 are connected to the two MOS switch chips 15 at the same time. And then, carrying out a thermal bonding process to enable the first sub-copper block 24 of the MOS switch chip 15 and the second sub-copper block 24 on the IC control chip 12 to be tightly bonded together to form lower contact resistance, wherein the bonding is to directly bond two homogeneous or heterogeneous semiconductor materials with clean surfaces and flat atomic levels under certain conditions through surface cleaning and activating treatment, and the wafer is bonded into a whole through Van der Waals force, molecular force or atomic force, so that the conduction loss of the chip can be reduced, and compared with the traditional technology for wire bonding connection for packaging, the resistance is reduced by more than 80%.
S5: and cutting the metal frame 30, and filling and sealing the plastic package body 11 to obtain the power circuit packaging structure 10.
Referring to fig. 6, in this embodiment, the plastic package body 11 is made of epoxy resin, a molding machine is used to fill and seal the plastic package body 11, the module is cut, that is, the metal frame 30 is cut, and then the plastic package body 11 is placed into the molding machine to fill and mold the plastic package body, the epoxy resin has a good sealing effect, so as to effectively protect the internal chip, and finally, a package product with a structural shape, that is, the power circuit package structure 10 is formed.
Referring to fig. 7, the present invention provides a power circuit package structure 10, including a plastic package body 11, an IC control chip 12 located on the plastic package body 11, first metal base islands 13 located on two sides of the IC control chip 12, second metal base islands 14 connected to the IC control chip 12, and a MOS switch chip 15 connected to the IC control chip 12 and the first metal base islands 13, wherein a first polyimide layer 16 is disposed on an upper surface of the MOS switch chip 15, a second polyimide layer 17 is disposed on a lower surface of the IC control chip 12, first copper pillars 18 penetrating through the first polyimide layer 16 and arranged at intervals, first copper blocks 19 perpendicular to the first copper pillars 18 and attached to a first end surface of the first metal base islands 13 are disposed on one side of the MOS switch chip 15, first pins 28 extending outward from a second end surface of the first metal base islands 13, the other side of the MOS switch chip 15 is provided with second copper pillars 20 respectively penetrating through the first polyimide layer 16 and the second polyimide layer 17 and arranged at intervals, a second copper block 23 perpendicular to the second copper pillars 20 and located between the first polyimide layer 16 and the second polyimide layer 17, a third copper pillar 26 located between the second copper pillars 20 and penetrating through the second polyimide layer 17, and a third copper block 27 perpendicular to the third copper pillar 26 and attached to one end of the second metal base island 14, and the other end of the second metal base island 14 is connected with a second pin 29 extending outwards.
In this embodiment, the size of the first copper block 19 is larger than the size of the second copper block 23, and the size of the first metal base island 13 is larger than the size of the second metal base island 14. In the direction parallel to the plastic package body 11, the height of the second metal base island 14 is smaller than that of the first metal base island 13, and the first copper block 19, the second copper block 23 and the third copper block 27 are located on the same horizontal line. The structure of the MOS switch chip 15 is symmetrical, the first polyimide layer 16 is positioned on the upper surface of the MOS switch chip 15, the second polyimide layer 17 is positioned on the lower surface of the IC control chip 12, the two first metal base islands 13 are symmetrically arranged relative to the second metal base island 14, the height of the two first metal base islands 13 is less than that of the IC control chip 12, the thicknesses of the first polyimide layer 16 and the second polyimide layer 17 can be the same and can both play an insulating role to isolate each copper column, the bottom surface of the first metal base island 13 is attached to the first copper block 19, the second metal base island 14 is attached to the third copper block 27, the second copper block 23 is respectively attached to the first polyimide layer 16 and the second polyimide layer 17, the integration level of the chip package can be improved, the first pin 28 and the second pin 29 extend outwards, the lead connection is omitted, the current density and the integration level of the chip package are improved, the manufacturing cost is reduced.
The invention provides a power circuit packaging structure and a packaging method thereof, wherein a polyimide layer is coated on the upper surfaces of two MOS switch chips 15, the polyimide at the lead window of the chips is removed to form a first polyimide layer 16, copper balls are implanted to grow to form first copper columns 18 which penetrate through the first polyimide layer 16 and are arranged at intervals and first sub-copper columns 21 which are positioned at the other side of the MOS switch chips 15, a layer of metal is coated on the first copper columns 18 and the first sub-copper columns 21, redundant metal is removed, first copper blocks 19 positioned on the first copper columns 18 and first sub-copper blocks 24 positioned on the first sub-copper columns 21 are formed, a second polyimide layer 17, second sub-copper columns 22 which penetrate through the second polyimide layer 17 and are arranged at intervals, third copper columns 26 positioned between the second sub-copper columns 22, second sub-copper blocks 25 which are vertical to the second sub-copper columns 22 and third copper blocks 27 which are vertical to the third copper columns 26 are formed on the surface of an IC control chip 12, the IC control chip 12 is connected with the two MOS switch chips 15 by adopting thermal bonding, the two metal base islands are respectively connected with the two MOS switch chips 15, and the two MOS switch chips 15 and the IC control chip 12 are precisely and ingeniously attached together in a small size range, so that the whole circuit has extremely low transmission resistance and extremely low parasitic inductance, the power consumption is greatly reduced, and the working frequency is improved. Meanwhile, the volume of the whole packaging body is reduced, so that the circuit has a smaller appearance, and the application scene is greatly widened.
In all examples shown and described herein, any particular value should be construed as merely exemplary, and not as a limitation, and thus other examples of example embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The above examples are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but not to be construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention.
Claims (8)
1. The utility model provides a power supply circuit packaging structure, its characterized in that, including the plastic-sealed body, be located IC control chip on the plastic-sealed body, be located the first metal base island of IC control chip both sides, with the second metal base island that IC control chip is connected, connect IC control chip with the MOS switch chip of first metal base island, MOS switch chip upper surface is provided with first polyimide layer, IC control chip lower surface is provided with second polyimide layer, one side of MOS switch chip is provided with and runs through first polyimide layer and interval arrangement's first copper post, with first copper post is perpendicular and with the first copper piece of the first terminal surface laminating of first metal base island, the first pin of the second terminal surface outside extension of first metal base island, the opposite side of MOS switch chip is provided with and runs through respectively first polyimide layer and the second polyimide layer and interval arrangement's second copper post, And a second copper block which is vertical to the second copper column and is positioned between the first polyimide layer and the second polyimide layer, a third copper column which is positioned between the second copper columns and penetrates through the second polyimide layer and a third copper block which is vertical to the third copper column and is attached to one end of the second metal base island are arranged on the IC control chip, and a second pin which extends outwards is connected to the other end of the second metal base island.
2. The power supply circuit packaging structure according to claim 1, wherein the size of the first copper block is larger than the size of the second copper block, and the size of the first metal base island is larger than the size of the second metal base island.
3. The power supply circuit packaging structure according to claim 1, wherein the height of the second metal base island is smaller than the height of the first metal base island in a direction parallel to the molding compound body, and the first copper block, the second copper block and the third copper block are located at the same horizontal line.
4. A power circuit packaging method is characterized by comprising the following steps:
coating a polyimide layer on the upper surfaces of two MOS switch chips, removing polyimide at a lead window of the chips to form a first polyimide layer, implanting copper balls for growing to form first copper columns penetrating through the first polyimide layer in an interval arrangement mode and first sub-copper columns positioned on the other side of the MOS switch chips, coating a layer of metal on the first copper columns and the first sub-copper columns, removing redundant metal, and forming a first copper block positioned on the first copper columns and a first sub-copper block positioned on the first sub-copper columns;
forming a second polyimide layer, second sub-copper columns penetrating through the second polyimide layer and arranged at intervals, third copper columns located between the second sub-copper columns, second sub-copper blocks perpendicular to the second sub-copper columns and third copper blocks perpendicular to the third copper columns on the surface of an IC control chip;
the method comprises the following steps that a metal frame, two first metal base islands fixedly connected with the metal frame and a second metal base island located between the first metal base islands are adopted, so that first copper blocks of two MOS switch chips are connected with the bottom surfaces of the first metal base islands through conductive silver adhesive, the first metal base islands are connected with first pins, and the second metal base islands are connected with second pins;
turning the IC control chip 180 degrees and connecting the IC control chip with the second metal base island through conductive silver adhesive, wherein the IC control chip is arranged between the first metal base islands, the MOS switch chips are symmetrically arranged on two sides of the IC control chip, the first sub copper block is connected with the second sub copper block, the third copper block is connected with the second metal base island, the first sub copper block and the second sub copper block are thermally bonded to form a second copper block, and the first sub copper column is thermally bonded with the second copper column to form a second copper column;
and cutting off the metal frame, and filling and sealing the plastic package body to obtain the power circuit packaging structure.
5. The power circuit packaging method according to claim 4, wherein the material of the plastic package body is epoxy resin, and a molding machine is used for filling and sealing the plastic package body.
6. The power supply circuit packaging method according to claim 4, wherein the height of the second metal base island is smaller than that of the first metal base island, and the second metal base island, the first copper pillar and the first sub-copper pillar are located at the same horizontal line.
7. The power circuit packaging method according to claim 4, wherein the metal frame is T-shaped, the cross-sectional area of the first metal base island is larger than that of the first copper block, and the cross-sectional area of the second metal base island is larger than that of the third copper block.
8. The power circuit packaging method according to claim 4, wherein the number of the first copper pillars and the number of the second copper pillars are both three, the number of the third copper pillars is one, and the thicknesses of the first copper blocks, the second copper blocks and the third copper blocks are the same.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111671525.4A CN114361055A (en) | 2021-12-31 | 2021-12-31 | Power circuit packaging structure and packaging method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111671525.4A CN114361055A (en) | 2021-12-31 | 2021-12-31 | Power circuit packaging structure and packaging method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114361055A true CN114361055A (en) | 2022-04-15 |
Family
ID=81104496
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111671525.4A Pending CN114361055A (en) | 2021-12-31 | 2021-12-31 | Power circuit packaging structure and packaging method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114361055A (en) |
-
2021
- 2021-12-31 CN CN202111671525.4A patent/CN114361055A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9589869B2 (en) | Packaging solutions for devices and systems comprising lateral GaN power transistors | |
| US9824949B2 (en) | Packaging solutions for devices and systems comprising lateral GaN power transistors | |
| TWI590395B (en) | Power encapsulation module of multi-power chip and manufacturing method of power chip unit | |
| US8426963B2 (en) | Power semiconductor package structure and manufacturing method thereof | |
| KR101906458B1 (en) | Semiconductor product | |
| US8426953B2 (en) | Semiconductor package with an embedded printed circuit board and stacked die | |
| TWI565012B (en) | A stack frame for electrical connections and the method to fabricate thereof | |
| US11545421B2 (en) | Package including multiple semiconductor devices | |
| US11004764B2 (en) | Semiconductor package having symmetrically arranged power terminals and method for producing the same | |
| CN103681531B (en) | Integrated circuit and the method for making integrated circuit | |
| US20200194359A1 (en) | Power converter having a conductive clip | |
| TW201239998A (en) | Method for mold array process to prevent peripheries of substrate exposed | |
| US20180122729A1 (en) | High power and high frequency plastic pre-molded cavity package | |
| TWI641142B (en) | Insulated bump bonding | |
| CN114361055A (en) | Power circuit packaging structure and packaging method thereof | |
| CN109494209B (en) | Ultrathin packaging structure with wettable side wall and manufacturing method thereof | |
| TW202125768A (en) | Common source land grid array package | |
| US8970032B2 (en) | Chip module and method for fabricating a chip module | |
| CN113035724B (en) | Multi-chip packaging structure and manufacturing method thereof | |
| CN105633027A (en) | Fan-out wafer level chip packaging structure and manufacturing method thereof | |
| TWI827014B (en) | Package structure and circuit board assembly with embedded power chip | |
| CN213071137U (en) | Chip packaging structure and digital isolator | |
| US20240162205A1 (en) | Power semiconductor package and method for fabricating the same | |
| CN116978881A (en) | Packaging structure and circuit board assembly with embedded power chip | |
| TWI400773B (en) | Circuit device with at least partial packaging and method for forming |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |