CN114361019A - Semiconductor structure, preparation method thereof and storage device - Google Patents
Semiconductor structure, preparation method thereof and storage device Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 238000002360 preparation method Methods 0.000 title abstract description 12
- 238000003860 storage Methods 0.000 title description 2
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 67
- 230000003647 oxidation Effects 0.000 claims abstract description 66
- 238000011282 treatment Methods 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 230000001590 oxidative effect Effects 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 60
- 238000006243 chemical reaction Methods 0.000 claims description 41
- 239000012495 reaction gas Substances 0.000 claims description 20
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 13
- 239000001257 hydrogen Substances 0.000 claims description 13
- 229910052739 hydrogen Inorganic materials 0.000 claims description 13
- 239000001301 oxygen Substances 0.000 claims description 13
- 229910052760 oxygen Inorganic materials 0.000 claims description 13
- 125000004122 cyclic group Chemical group 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 239000007772 electrode material Substances 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims 2
- 230000007547 defect Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 4
- 230000004913 activation Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000035484 reaction time Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910008065 Si-SiO Inorganic materials 0.000 description 1
- 229910006405 Si—SiO Inorganic materials 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
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- 238000005502 peroxidation Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H01L21/28158—Making the insulator
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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Abstract
The invention relates to a preparation method of a semiconductor structure, which comprises the following steps: providing a substrate; forming an initial structure on a substrate, wherein the initial structure comprises a first gate dielectric layer and a first gate layer positioned on the first gate dielectric layer, and the first gate layer has a first thickness; and oxidizing the initial structure to form a second gate dielectric layer with a second thickness between the first gate dielectric layer and the first gate layer, wherein the second thickness is smaller than the first thickness. According to the preparation method of the semiconductor structure, the first gate layer in the initial structure is subjected to oxidation treatment, the high-quality second gate dielectric layer is grown on the surface of the first gate layer, dangling bonds at the interface between the first gate layer and the first gate dielectric layer are eliminated, and the film forming quality at the interface is improved.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a semiconductor, a preparation method thereof and a semiconductor device.
Background
When the gate layer is prepared on the surface of the gate dielectric layer, due to the interface characteristics of the gate layer and the gate dielectric layer, the periodicity of the crystal lattice of the gate layer is suddenly interrupted, so that a dangling bond is generated at the interface of the gate layer and the gate dielectric layer, an allowable electron energy level exists in a forbidden band, and adverse effects are caused on the improvement and stability of the performance of a semiconductor device.
Disclosure of Invention
In view of the above, it is necessary to provide a semiconductor structure, a method for fabricating the same, and a memory device.
The embodiment of the application discloses a preparation method of a semiconductor structure, which comprises the following steps: providing a substrate; forming an initial structure on a substrate, wherein the initial structure comprises a first gate dielectric layer and a first gate layer positioned on the first gate dielectric layer, and the first gate layer has a first thickness; and oxidizing the initial structure to form a second gate dielectric layer with a second thickness between the first gate dielectric layer and the first gate layer, wherein the second thickness is smaller than the first thickness.
According to the preparation method of the semiconductor structure, the first gate layer in the initial structure is subjected to oxidation treatment, the high-quality second gate dielectric layer is grown on the surface of the first gate layer, dangling bonds at the interface between the first gate layer and the first gate dielectric layer are eliminated, the film forming quality at the interface is improved, and the gate leakage and parasitic capacitance are reduced. And, the second thickness is limited to be less than the first thickness, ensuring that the first gate layer is not completely oxidized after the oxidation process.
In one embodiment, the first gate dielectric layer is formed by an in-situ water vapor growth process.
In one embodiment, the oxidizing the initial structure to form a second gate dielectric layer of a second thickness between the first gate dielectric layer and the first gate layer comprises: and carrying out oxidation treatment on the surface of the first gate layer facing the first gate dielectric layer to form a second gate dielectric layer.
In one embodiment, the oxidizing the initial structure to form a second gate dielectric layer of a second thickness between the first gate dielectric layer and the first gate layer comprises:
in one embodiment, the first gate layer is subjected to oxidation treatment, a second gate dielectric layer with a second thickness is formed on an interface of the first gate layer facing the first gate dielectric layer, an oxide layer with a third thickness is formed on an interface of the first gate layer far away from the first gate dielectric layer, the third thickness is larger than the second thickness, and the sum of the third thickness and the second thickness is smaller than the first thickness; and removing the oxide layer.
By controlling the sum of the third thickness and the second thickness to be smaller than the first thickness, the unoxidized part of the first gate layer can be ensured to remain, so that the gate material can be continuously deposited on the surface of the first gate after the oxide layer is removed, and the gate with the target thickness can be obtained.
In one embodiment, after removing the oxide layer, the method further includes: and forming a second gate layer on the upper surface of the first gate layer.
In one embodiment, the step of forming the second gate layer comprises: forming a second gate material layer on the upper surface of the first gate layer; annealing the second gate material layer; and etching the second grid electrode material layer to obtain a second grid electrode layer.
In one embodiment, the first gate layer and the second gate layer comprise polysilicon layers, and the first gate dielectric layer, the second gate dielectric layer and the oxide layer comprise silicon oxide layers.
In one embodiment, the first thickness comprises 5nm to 100nm and the second thickness comprises 0.1nm to 10 nm.
In one embodiment, the step of oxidizing comprises: providing a reaction chamber, and placing an initial structure inside the reaction chamber; introducing reaction gas into the reaction chamber, wherein the reaction gas comprises hydrogen and oxygen, and the volume percentage of the hydrogen in the reaction gas is 2-3%, and the volume percentage of the oxygen in the reaction gas is 97-98%; setting the temperature of the reaction chamber as the reaction temperature, wherein the reaction temperature is 900-1100 ℃, and reacting for 40-50 s at the reaction temperature.
In one embodiment, the oxidation treatment comprises a cyclic oxidation process comprising: performing first oxidation treatment on the initial structure, forming a second gate dielectric layer with a second thickness on an interface of the first gate layer facing the first gate dielectric layer, and forming a first oxide layer with a third thickness on an interface of the first gate layer far away from the first gate dielectric layer, wherein the sum of the third thickness and the second thickness is smaller than the first thickness; removing the first oxide layer to obtain an intermediate structure; performing second oxidation treatment on the intermediate structure, forming a third gate dielectric layer with a fourth thickness on the interface of the first gate layer facing the first gate dielectric layer, and forming a second oxide layer with a fifth thickness on the interface of the first gate layer far away from the first gate dielectric layer; the sum of the second thickness, the third thickness, the fourth thickness and the fifth thickness is less than the first thickness; removing the second oxide layer; and repeating the oxidation treatment until the thickness of the dielectric layer between the first gate dielectric layer and the first gate layer reaches the target thickness.
In one embodiment, the step of performing a single oxidation treatment in a cyclic oxidation process comprises: providing a reaction chamber, and placing an initial structure or an intermediate structure inside the reaction chamber; introducing reaction gas into the reaction chamber, wherein the reaction gas comprises hydrogen and oxygen, and the volume percentage of the hydrogen in the reaction gas is 2-3%, and the volume percentage of the oxygen in the reaction gas is 97-98%; setting the temperature of the reaction chamber as the reaction temperature, wherein the reaction temperature is 900-1100 ℃, and reacting for 8-10 s at the reaction temperature.
According to the preparation method of the semiconductor structure, the thickness of the newly-formed gate dielectric layer at the interface can be better controlled by reducing the time of a single oxidation process and increasing the times of the oxidation process, the condition of peroxidation is prevented, and the unoxidized part in the first gate layer is ensured to be remained.
In one embodiment, after forming the initial structure on the substrate, the method further comprises: and annealing the first gate layer.
In one embodiment, after forming the second gate dielectric layer, the method further includes: and annealing the second gate dielectric layer.
The application also discloses a semiconductor structure prepared by the preparation method of the semiconductor structure of any one of the embodiments.
The semiconductor structure adopts the preparation method of the semiconductor structure, eliminates the defects of dangling bonds and crystal boundaries at the interface of the grid electrode and the grid dielectric layer, improves the film forming quality, and reduces the electric leakage and parasitic capacitance of the grid electrode.
The application also discloses a memory device comprising the semiconductor structure in the embodiment.
Drawings
Fig. 1 is a flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.
Fig. 2 is a schematic cross-sectional structure diagram of a substrate provided in an embodiment of the present application.
Fig. 3 is a schematic cross-sectional view of a semiconductor structure obtained after forming an initial structure on a substrate according to an embodiment of the present application.
Fig. 4 is a schematic cross-sectional view of a semiconductor structure obtained after an oxide layer and a second gate dielectric layer are formed in an embodiment of the present application.
Fig. 5 is a schematic cross-sectional view of a semiconductor structure obtained after removing an oxide layer according to an embodiment of the present application.
Fig. 6 is a schematic cross-sectional view of a semiconductor structure obtained after forming a second gate layer according to an embodiment of the present application.
Fig. 7 is a schematic cross-sectional view of a semiconductor structure obtained after performing a second oxidation process on the first gate layer in an embodiment of the present application.
Fig. 8 is a schematic cross-sectional view of a semiconductor structure obtained after removing the second oxide layer in an embodiment of the present application.
The reference numbers illustrate:
10. a substrate; 11. doping the substrate; 12. a well region; 21. a first gate dielectric layer; 22. a first gate layer; 23. a second gate dielectric layer; 24. a first oxide layer; 25. a second gate layer; 26. a third gate dielectric layer; 27. a second oxide layer.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
In describing positional relationships, unless otherwise specified, when an element such as a layer, film or substrate is referred to as being "on" another layer, it can be directly on the other layer or intervening layers may also be present. Further, when a layer is referred to as being "under" another layer, it can be directly under, or one or more intervening layers may also be present. It will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
Where the terms "comprising," "having," and "including" are used herein, another element may be added unless an explicit limitation is used, such as "only," "consisting of … …," etc. Unless mentioned to the contrary, terms in the singular may include the plural and are not to be construed as being one in number.
One embodiment of the present application discloses a method for fabricating a semiconductor structure, as shown in fig. 1, comprising:
s10: providing a substrate;
s20: forming an initial structure on a substrate, wherein the initial structure comprises a first gate dielectric layer and a first gate layer positioned on the first gate dielectric layer, and the first gate layer has a first thickness;
s30: and oxidizing the initial structure to form a second gate dielectric layer with a second thickness between the first gate dielectric layer and the first gate layer, wherein the second thickness is smaller than the first thickness.
The transistor structure includes a gate dielectric layer and a gate conductive layer on the gate dielectric layer, and the interface performance of the gate dielectric layer and the gate conductive layer is an important factor affecting the performance of the transistor. For example, silicon dioxide films, which are the native oxide of silicon, are an important gate dielectric material for silicon-based MOSFETs (metal-oxide semiconductor field effect transistors). However, because the interface characteristics of SiO2 and Si are different, a dangling bond exists at the interface of the gate and the gate dielectric layer, so that an allowed electron energy level exists in a forbidden band, which adversely affects the improvement and stability of the performance of the semiconductor device. The method in the embodiment of the application can be used for well solving the problems.
In step S10, the substrate may include, but is not limited to, a silicon-based substrate. Illustratively, as shown in fig. 2, the substrate 10 includes a doped base 11 and a well region 12. As an example, the doped substrate 11 is a P-type doped substrate, and the well region 12 is a P-type well region. In other embodiments, the doped substrate 11 may also be an N-type doped substrate, and the well region 12 is an N-type well region. The present application does not limit the doping types of the well region 12 and the doped base 11 in the substrate 10.
In step S20, an initial structure formed on the substrate 10 is shown in fig. 3. Specifically, the step of forming the initial structure on the substrate 10 includes:
s21: a first gate dielectric layer 21 is formed on the upper surface of the substrate 10.
Illustratively, the first gate dielectric layer 21 may include, but is not limited to, a silicon oxide layer. The method for forming the first gate dielectric layer 21 includes a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process. In other embodiments, the first gate dielectric layer 21 may also be formed by an In-Situ Steam Generation (ISSG) process.
S22: a first gate layer 22 is formed on the top surface of the first gate dielectric layer 21.
The first gate layer 22 may include, but is not limited to, a polysilicon layer. Illustratively, a polysilicon layer of a first thickness may be deposited on the upper surface of the first gate dielectric layer 21. Wherein the first thickness may be 5nm to 100nm, such as 5nm, 10nm, 30nm, 50nm or 100 nm. In one embodiment, after forming the first gate layer 22 with the first thickness, the first gate layer 22 is annealed to improve the gate dopant activation rate and the gate quality.
In step S30, a second gate dielectric layer of a second thickness may be formed between the first gate dielectric layer 21 and the first gate layer 22 by subjecting the initial structure to an oxidation process. Wherein the second thickness is less than the first thickness.
Specifically, in some embodiments, the step of forming the second gate dielectric layer includes:
s31: the first gate layer 22 is subjected to an oxidation process, a second gate dielectric layer 23 with a second thickness is formed on an interface of the first gate layer 22 facing the first gate dielectric layer 21, and a first oxide layer 24 with a third thickness is formed on an interface of the first gate layer 22 away from the first gate dielectric layer 21, wherein the third thickness is greater than the second thickness, and the sum of the third thickness and the second thickness is smaller than the first thickness, as shown in fig. 4.
Illustratively, the method of performing the oxidation treatment on the first gate layer 22 may include, but is not limited to, an ISSG process. Specifically, during the process of oxidizing the initial structure by using the ISSG process, the first oxide layer 24 is formed on both the upper surface and the side surface of the first gate layer 22, and the second gate dielectric layer 23 is formed on the interface between the first gate layer 22 and the first gate dielectric layer 21, as shown in fig. 4. Illustratively, the first gate dielectric layer 22 is a polysilicon layer, the second gate dielectric layer 23 and the first oxide layer 24 are silicon oxide layers, and since the second gate dielectric layer 23 is formed by oxidizing silicon on the surface of the polysilicon layer, no interface defect or dangling bond exists between the second gate dielectric layer 23 and the first gate layer 22, and the interface defect or dangling bond between the first gate dielectric layer 21 and the first gate layer 22 in the initial structure is eliminated.
In addition, in the present embodiment, the sum of the third thickness and the second thickness is smaller than the first thickness, which aims to prevent the first gate layer 22 from being completely oxidized. If the first gate layer 22 is completely oxidized, a polysilicon material layer can be deposited only on the surface of the silicon oxide layer when the gate thickness needs to be increased in a subsequent step, so that a new Si-SiO layer is formed2Interface, generating new interface defect and dangling bond. Therefore, by controlling the sum of the third thickness and the second thickness to be smaller than the first thickness, the unoxidized polycrystalline silicon layer with a certain thickness can be ensured to be remained after the oxidation treatment is carried out on the initial structure, and the generation of new interface defects and dangling bonds is avoided when the thickness of the grid layer is increased in the subsequent steps.
Illustratively, the second thickness may be 0.1nm to 10 nm. Specifically, the thickness of the second gate dielectric layer 23 is related to the region where the semiconductor structure is located. When the semiconductor structure is located in the active region, the thickness of the second gate dielectric layer 23 is small, for example, 0.1nm to 5nm, for example, 0.1nm, 1nm, 3nm or 5 nm. When the semiconductor structure is located in the peripheral region, the thickness of the second gate dielectric layer 23 is larger, for example, 6nm to 10nm, for example, 6nm, 8nm or 10 nm. Illustratively, the third thickness may be 5nm-50nm, such as 5nm, 10nm, 20nm, 30nm, or 50 nm.
S32: the first oxide layer 24 is removed.
Illustratively, an etching process may be employed to remove the first oxide layer 24 on the top surface and the side surfaces of the first gate layer 22, resulting in the semiconductor structure shown in fig. 5.
In some embodiments, the surface of the first gate layer 22 facing the first gate dielectric layer 21 is subjected to an oxidation treatment to form a second gate dielectric layer 23, as shown in fig. 5.
Illustratively, the method of oxidation treatment includes, but is not limited to, an ISSG process. When the first gate layer 22 is a polysilicon layer, the second gate dielectric layer 23 is formed as a silicon oxide layer. Since the second gate dielectric layer 23 is formed by oxidizing silicon on the surface of the polysilicon layer, no interface defect or dangling bond exists between the second gate dielectric layer 23 and the first gate layer 22. In one embodiment, after the second gate dielectric layer 23 is formed, a step of annealing the second gate dielectric layer 23 is further included.
In one embodiment, after removing the first oxide layer 24, the method further includes:
s40: a second gate layer 25 is formed on the upper surface of the first gate layer 22, as shown in fig. 6.
The thickness of the first gate layer 22 in the initial structure is reduced after the oxidation process, and in order to obtain a gate with a desired thickness, the thickness of the gate needs to be increased on the basis of the first gate layer 22, for example, a second gate layer 25 can be formed on the upper surface of the first gate layer 22 to form a final semiconductor structure.
As an example, the finally formed semiconductor structure may be a MOS structure in a MOSFET (metal-oxide semiconductor field effect transistor).
Illustratively, the step of forming the second gate layer 25 includes:
s41: a second gate material layer is formed on the upper surface of the first gate layer 22.
Illustratively, the second gate material layer and the first gate layer 22 are polysilicon layers.
S42: and annealing the second gate material layer.
Through the annealing treatment, the activation rate of the gate dopant and the gate quality can be improved.
S43: and etching the second gate material layer to obtain a second gate layer 25.
Illustratively, the polysilicon layer exceeding the required thickness is removed by an etching process to obtain the second gate layer 25. In other embodiments, a planarization process may also be performed on the upper surface of the second gate layer 25.
In one embodiment, the step of subjecting the initial structure to an oxidation process comprises: providing a reaction chamber, and placing an initial structure inside the reaction chamber; introducing reaction gas into the reaction chamber, wherein the reaction gas comprises hydrogen and oxygen, and the volume percentage of the hydrogen in the reaction gas is 2% -3%, such as 2%, 2.5% or 3%; is 97% to 98% by volume of oxygen, for example 97%, 97.5% or 98%; the temperature of the reaction chamber is set to a reaction temperature of 900 ℃ to 1100 ℃, such as 900 ℃, 1000 ℃ or 1100 ℃, for 40s to 50s, such as 40s, 45s or 50s, at the reaction temperature.
As an example, the specific parameters for performing the oxidation treatment on the initial structure may be: the volume percent of hydrogen is 2.5 percent, the volume percent of oxygen is 97.5 percent, the reaction temperature is 1000 ℃, and the reaction time is set to be 45 s.
According to the preparation method of the semiconductor structure, the first gate layer in the initial structure is subjected to oxidation treatment, the high-quality second gate dielectric layer is grown on the surface of the first gate layer, dangling bonds at the interface between the first gate layer and the first gate dielectric layer are eliminated, the film forming quality at the interface is improved, and the gate leakage and parasitic capacitance are reduced. And, the second thickness is limited to be less than the first thickness, ensuring that the first gate layer is not completely oxidized after the oxidation process.
In the embodiments of the foregoing embodiments, the initial structure is subjected to the primary oxidation treatment. In one embodiment, the oxidation treatment may further include a cyclic oxidation process. The cyclic oxidation process is to shorten the time of single oxidation treatment and carry out multiple oxidation treatments on the initial structure under the condition of keeping other parameters unchanged.
For example, the time of the single oxidation treatment may be 1/3, 1/5, or 1/10 of the time of the single oxidation treatment in the foregoing embodiment. For example, in the foregoing embodiment, the oxidation treatment is performed only once on the initial structure for a treatment time of 40s to 50 s. The time for each oxidation treatment in the cyclic oxidation process may be, for example, 12s to 16s, or 8s to 10s, or 4s to 5 s. In other embodiments, the total time of the cyclic oxidation process is kept constant or flexibly adjusted according to the thickness of the dielectric layer formed between the first gate electrode layer 22 and the first gate dielectric layer 21.
In one embodiment, as an example, the time for each oxidation process is set to 8s, and the steps of performing the cyclic oxidation process on the initial structure are as follows:
s311: performing a first oxidation treatment on the initial structure, forming a second gate dielectric layer 23 with a second thickness on an interface of the first gate layer 22 facing the first gate dielectric layer 21, and forming a first oxide layer 24 with a third thickness on an interface of the first gate layer 22 far away from the first gate dielectric layer 21, wherein the sum of the third thickness and the second thickness is smaller than the first thickness, as shown in fig. 4;
s312: removing the first oxide layer 24 to obtain an intermediate structure, as shown in fig. 5;
s313: performing second oxidation treatment on the intermediate structure, forming a third gate dielectric layer 26 with a fourth thickness on the interface of the first gate layer 22 facing the first gate dielectric layer 21, and forming a second oxidation layer 27 with a fifth thickness on the interface of the first gate layer 22 far away from the first gate dielectric layer 21; the sum of the second thickness, the third thickness, the fourth thickness, and the fifth thickness is less than the first thickness, as shown in fig. 7;
s314: removing the second oxide layer 27, as shown in fig. 8;
s315: the above oxidation process is repeated until the dielectric layer thickness between the first gate dielectric layer 21 and the first gate layer 22 reaches the target thickness.
The target thickness may be 1nm to 10nm, for example 1nm, 3nm, 5nm, 6nm, 8nm or 10 nm. Illustratively, the target thickness is also related to the area where the semiconductor structure is located, and when the semiconductor structure is located in the active region, the target thickness is small, such as 1nm, 3nm, or 5 nm. When the semiconductor structure is located in the peripheral region, the target thickness is large, such as 6nm, 8nm, or 10 nm. In other embodiments, the target thickness is also related to the thickness of the first gate dielectric layer 21 in the initial structure. When the thickness of the first gate dielectric layer 21 is large, the target thickness may be reduced accordingly.
Since the time of the single oxidation treatment is short, the second thickness and the third thickness in the present embodiment are both smaller than those in the foregoing embodiments. After the first oxidation treatment, although the thickness (third thickness) of the first oxide layer 24 is still greater than the thickness (second thickness) of the second gate dielectric layer 23, the difference between the third thickness and the second thickness is reduced. Similarly, after removing the first oxide layer 24 and performing the second oxidation treatment on the intermediate structure, a third gate dielectric layer 26 having a fourth thickness and a second oxide layer 27 having a fifth thickness are formed, wherein the fourth thickness is the same as or close to the second thickness, and the fifth thickness is the same as or close to the third thickness. The thickness of the dielectric layer between the first gate dielectric layer 21 and the first gate layer 22 is the sum of the fourth thickness and the second thickness.
In the cyclic oxidation process, by reducing the time of the single oxidation treatment, the thicknesses of the newly generated oxide layer and the newly generated gate dielectric layer can be reduced, and the thickness difference between the newly generated oxide layer and the newly generated gate dielectric layer can be reduced, so that the oxidation degree of the first gate layer 22 in each oxidation treatment can be better controlled in the cyclic oxidation process, and the situation of over-oxidation is prevented. Further, by controlling the sum of the thicknesses of the oxide layer and the gate dielectric layer formed after the oxidation treatment to be within a range smaller than the first thickness, it is possible to ensure that a gate layer that is not oxidized remains in the first gate layer 22.
As an example, the steps of the single oxidation treatment in the cyclic oxidation process are: providing a reaction chamber, and placing an initial structure or an intermediate structure inside the reaction chamber; introducing reaction gas into the reaction chamber, wherein the reaction gas comprises hydrogen and oxygen, and the volume percentage of the hydrogen in the reaction gas is 2% -3%, such as 2%, 2.5% or 3%; is 97% to 98% by volume of oxygen, for example 97%, 97.5% or 98%; the temperature of the reaction chamber is set to a reaction temperature of 900 to 1100 deg.C, such as 900 deg.C, 1000 deg.C or 1100 deg.C, for 8 to 10 seconds, such as 8, 9 or 10 seconds, at the reaction temperature. In other embodiments, the reaction time may also include 12s-16s or 4s-5 s.
An embodiment of the present application further discloses a semiconductor structure, which is prepared by the method for preparing a semiconductor structure in any of the foregoing embodiments. By adopting the preparation method of the semiconductor structure in the embodiment, the defects of dangling bonds and grain boundaries at the interface of the grid electrode and the grid dielectric layer can be eliminated, the film forming quality is improved, and the grid electrode electric leakage and parasitic capacitance are reduced.
An embodiment of the present application also discloses a memory device including the semiconductor structure in the above embodiment. By adopting the semiconductor structure, the performance of the memory device can be improved.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (15)
1. A method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming an initial structure on the substrate, wherein the initial structure comprises a first gate dielectric layer and a first gate layer positioned on the first gate dielectric layer, and the first gate layer has a first thickness;
and carrying out oxidation treatment on the initial structure, and forming a second gate dielectric layer with a second thickness between the first gate dielectric layer and the first gate layer, wherein the second thickness is smaller than the first thickness.
2. The method of claim 1, wherein the first gate dielectric layer is formed using an in-situ vapor growth process.
3. The method of claim 1, wherein the oxidizing the initial structure to form a second gate dielectric layer of a second thickness between the first gate dielectric layer and the first gate layer comprises:
and carrying out oxidation treatment on the surface of the first gate layer facing the first gate dielectric layer to form the second gate dielectric layer.
4. The method of claim 1, wherein the oxidizing the initial structure to form a second gate dielectric layer of a second thickness between the first gate dielectric layer and the first gate layer comprises:
performing oxidation treatment on the first gate layer, forming a second gate dielectric layer with the second thickness on an interface of the first gate layer facing the first gate dielectric layer, and forming an oxide layer with a third thickness on an interface of the first gate layer far away from the first gate dielectric layer, wherein the third thickness is greater than the second thickness, and the sum of the third thickness and the second thickness is smaller than the first thickness;
and removing the oxide layer.
5. The method for fabricating a semiconductor structure according to claim 4, further comprising, after removing the oxide layer:
and forming a second gate layer on the upper surface of the first gate layer.
6. The method of claim 5, wherein the step of forming the second gate layer comprises:
forming a second gate material layer on the upper surface of the first gate layer;
annealing the second grid material layer;
and etching the second grid electrode material layer to obtain the second grid electrode layer.
7. The method of claim 6, wherein the first gate layer and the second gate layer comprise polysilicon layers, and the first gate dielectric layer, the second gate dielectric layer and the oxide layer comprise silicon oxide layers.
8. The method of claim 1, wherein the first thickness comprises 5nm to 100nm and the second thickness comprises 0.1nm to 10 nm.
9. The method of fabricating a semiconductor structure according to any one of claims 1 to 8, wherein the step of oxidizing comprises:
providing a reaction chamber, and placing the initial structure inside the reaction chamber;
introducing reaction gas into the reaction chamber, wherein the reaction gas comprises hydrogen and oxygen, and the volume percentage of the hydrogen is 2-3% and the volume percentage of the oxygen is 97-98% in the reaction gas;
setting the temperature of the reaction chamber as a reaction temperature, wherein the reaction temperature is 900-1100 ℃, and reacting for 40-50 s at the reaction temperature.
10. The method of claim 1, wherein the oxidation treatment comprises a cyclic oxidation process comprising:
performing first oxidation treatment on the initial structure, forming a second gate dielectric layer with a second thickness on an interface of the first gate layer facing the first gate dielectric layer, and forming a first oxide layer with a third thickness on an interface of the first gate layer far away from the first gate dielectric layer, wherein the sum of the third thickness and the second thickness is smaller than the first thickness;
removing the first oxide layer to obtain an intermediate structure;
performing second oxidation treatment on the intermediate structure, forming a third gate dielectric layer with a fourth thickness on an interface of the first gate layer facing the first gate dielectric layer, and forming a second oxidation layer with a fifth thickness on an interface of the first gate layer far away from the first gate dielectric layer; a sum of the second thickness, the third thickness, the fourth thickness, and the fifth thickness is less than the first thickness;
removing the second oxide layer;
and repeating the oxidation treatment until the thickness of the dielectric layer between the first gate dielectric layer and the first gate layer reaches the target thickness.
11. The method of claim 10, wherein the step of performing a single oxidation treatment in the cyclic oxidation process comprises:
providing a reaction chamber, and placing the initial structure or the intermediate structure inside the reaction chamber;
introducing reaction gas into the reaction chamber, wherein the reaction gas comprises hydrogen and oxygen, and the volume percentage of the hydrogen is 2-3% and the volume percentage of the oxygen is 97-98% in the reaction gas;
setting the temperature of the reaction chamber as a reaction temperature, wherein the reaction temperature is 900-1100 ℃, and reacting for 8-10 s at the reaction temperature.
12. The method of claim 1, further comprising, after forming the initial structure on the substrate: and annealing the first gate layer.
13. The method of claim 12, further comprising, after forming the second gate dielectric layer: and annealing the second gate dielectric layer.
14. A semiconductor structure produced by the method for producing a semiconductor structure according to any one of claims 1 to 13.
15. A memory device comprising the semiconductor structure of claim 14.
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| CN202210025444.5A CN114361019A (en) | 2022-01-11 | 2022-01-11 | Semiconductor structure, preparation method thereof and storage device |
| PCT/CN2022/125102 WO2023134241A1 (en) | 2022-01-11 | 2022-10-13 | Semiconductor structure and preparation method therefor, and memory device |
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| JP2005252052A (en) * | 2004-03-05 | 2005-09-15 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| US7151042B2 (en) * | 2005-02-02 | 2006-12-19 | Macronix International Co., Ltd. | Method of improving flash memory performance |
| CN102097383B (en) * | 2009-12-15 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing double-bit flash memory |
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