CN114356687A

CN114356687A - Signal detection method and device and electronic equipment

Info

Publication number: CN114356687A
Application number: CN202111382038.6A
Authority: CN
Inventors: 程子强
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2021-11-19
Filing date: 2021-11-19
Publication date: 2022-04-15
Anticipated expiration: 2041-11-19
Also published as: CN114356687B

Abstract

The invention discloses a signal detection method, a signal detection device and electronic equipment, which are used for a CPLD module, wherein the CPLD module is respectively connected with a PSU power supply module and a PCH module, and a power line insertion state detection module is arranged in the PSU power supply module; the method comprises the following steps: when detecting that a PWRGD signal of a last VR power supply chip is triggered, sending a PCH _ PWROK signal to the PCH module; and when the PROC _ PWRGD signal sent by the PCH module is received to be at a high level, determining whether to respond to the detection operation to the power-off indication signal of the accessed CPU according to the detection result fed back by the power line insertion state detection module. The power line insertion state detection result is added to the condition that the CPLD module filters THERMATRIP _ N of the CPU, so that THERMTRIP false alarm generated in the abnormal power-off process can be effectively filtered, the THERMTRIP detection accuracy is improved, the false alarm work order can be greatly reduced, and the after-sale and operation and maintenance burden is greatly reduced.

Description

Signal detection method and device and electronic equipment

Technical Field

The invention relates to the technical field of signal detection, in particular to a signal detection method, a signal detection device and electronic equipment.

Background

The Central Processing Unit (CPU) is the most important component of the server system, and as the main frequency of the CPU increases, the power consumption and the heat generation amount of the CPU also increase continuously, and the temperature of the CPU directly affects the stability of the server, which requires the system fan to diffuse the heat generated by the CPU in time when the CPU operates. When the server works, if the system fan stops rotating, for example, the fan cannot rotate due to the reasons of being clamped by foreign matters, poor power supply contact, fan damage and the like, heat generated by the CPU cannot be timely dissipated, the temperature of the CPU is too high, the server is halted, and even the CPU is burnt. In order to ensure that the server stably works and the heat dissipation of the CPU is normal, the temperature of the CPU needs to be effectively detected so as to find and process problems in time.

The CPU is provided with a set of temperature protection mechanism, when the CPU is overheated due to the fact that heat cannot be dissipated timely, the CPU triggers and generates a signal (PROCHOT #) for indicating frequency reduction firstly, then the CPU reduces the frequency firstly, when the temperature is still continuously increased, the CPU continues to reduce the frequency, when the CPU is reduced to the lowest frequency, the temperature is still continuously increased, when the temperature reaches a highest temperature protection point, the CPU is damaged by temperature increase again, at the moment, the CPU triggers and generates a signal (THERMTRIP #) for indicating power failure, the CPU enters a THERMTRIP # mechanism, a CPLD (complex programmable logic device) of a detection chip can rapidly cut off a system power supply, and the CPU is forcibly shut down and forcibly dissipated heat. Therefore, the THERMTRIP # signal of the CPU needs to be properly processed, for example, improper processing may cause forced shutdown of the system, forced offline of the business, and loss of important business data, and may cause high-risk alarm at the operation and maintenance end due to THERMTRIP # alarm, and each work order needs to be analyzed in detail, for example, false alarm may cause a large amount of operation and maintenance burden. The conventional CPLD only depends on the PROC _ PWRGD signal to filter the THERMTRIP # signal of the CPU, and cannot completely avoid the error report of THERMTRIP # under the abnormal condition of AC power-off when the power-on is incomplete.

Disclosure of Invention

Therefore, the technical problem to be solved by the present invention is to overcome the defect of poor accuracy of the conventional detection method for the THERMTRIP # signal of the CPU, so as to provide a signal detection method, a signal detection device and an electronic device.

According to a first aspect, the embodiment of the present invention discloses a signal detection method, which is used for a CPLD module, wherein the CPLD module is respectively connected with a PSU power module and a PCH module, and a power line insertion state detection module is arranged in the PSU power module; the method comprises the following steps: when detecting that a PWRGD signal of a last VR power supply chip is triggered, sending a PCH _ PWROK signal to the PCH module; and when the PROC _ PWRGD signal sent by the PCH module is received to be at a high level, determining whether to respond to the detection operation to the power-off indication signal of the accessed CPU according to the detection result fed back by the power line insertion state detection module.

Optionally, when the received PROC _ PWRGD signal sent by the PCH module is at a high level, determining whether to respond to a detection operation to a power-off indication signal of an accessed CPU according to a detection result fed back by the power line insertion state detection module includes: and if the power line is determined to be in the non-inserted state according to the detection result fed back by the power line insertion state detection module, the detection operation of the power-off indication signal of the accessed CPU is not responded.

Optionally, when the received PROC _ PWRGD signal sent by the PCH module is at a high level, determining whether to respond to a detection operation to a power-off indication signal of an accessed CPU according to a detection result fed back by the power line insertion state detection module, further includes: and if the power line is determined to be in the insertion state according to the detection result fed back by the power line insertion state detection module, responding to the power-off indication signal of the accessed CPU for detection operation.

Optionally, the method further comprises: when a power-off indication signal of any CPU is detected, the power-off indication signal is sent to the PCH module, so that the PCH module responds to quick power-off operation when detecting that the power-off indication signal is at a low level.

Optionally, after sending a PCH _ PWROK signal to the PCH module when detecting that the PWRGD signal of the last VR power chip triggers, the method further includes: and when the PROC _ PWRGD signal sent by the PCH module is received to be at a low level, the detection operation of the power-off indication signal of the accessed CPU is not responded.

Optionally, the method further comprises: recording the detected power-off indication signal to a register.

Optionally, the CPLD module is connected with the BMC module; after the recording the detected power-off indication signal to a register, the method further comprises: and setting the register, so that the BMC responds to trigger alarm operation when polling the register to be set.

According to a second aspect, the embodiment of the present invention further discloses a signal detection device, which is used for a CPLD module, wherein the CPLD module is respectively connected with a PSU power module and a PCH module, and a power line insertion state detection module is arranged in the PSU power module; the device comprises: the first signal sending module is used for sending a PCH _ PWROK signal to the PCH module when detecting that the PWRGD signal of the last VR power supply chip is triggered; and the first determining module is used for determining whether to respond to the detection operation to the power-off indication signal of the accessed CPU according to the detection result fed back by the power line insertion state detecting module when the received PROC _ PWRGD signal sent by the PCH module is in a high level.

According to a third aspect, an embodiment of the present invention further discloses an electronic device, including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to cause the at least one processor to perform the steps of the signal detection method according to the first aspect or any one of the optional embodiments of the first aspect.

According to a fourth aspect, the present invention further discloses a computer-readable storage medium, on which a computer program is stored, which, when executed by a processor, implements the steps of the signal detection method according to the first aspect or any one of the optional embodiments of the first aspect.

The technical scheme of the invention has the following advantages:

the signal detection method/device provided by the invention is used for a CPLD module which is respectively connected with a PSU power supply module and a PCH module, wherein the PSU power supply module is provided with a power line insertion state detection module, when the PWRGD signal trigger of the last VR power supply chip is detected, a PCH _ PWROK signal is sent to the PCH module, and when the PROC _ PWRGD signal sent by the PCH module is received to be in a high level, whether the detection operation is responded to the power-off indication signal of the accessed CPU is determined according to the detection result fed back by the power line insertion state detection module. The power line insertion state detection result is added to the condition that the CPLD module filters THERMATRIP _ N of the CPU, so that THERMTRIP false alarm generated in the abnormal power-off process can be effectively filtered, the THERMTRIP detection accuracy is improved, the false alarm work order can be greatly reduced, and the after-sale and operation and maintenance burden is greatly reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic structural diagram of a specific example of a signal detection method in the prior art;

FIG. 2 is a waveform diagram illustrating a normal AC power-down in the prior art;

FIG. 3 is a waveform diagram illustrating an abnormal AC power-down in the prior art;

fig. 4 is a flowchart of a specific example of a signal detection method in the embodiment of the present invention;

fig. 5 is a schematic structural diagram of a specific example of a signal detection method in the embodiment of the present invention;

FIG. 6 is a waveform illustrating a normal AC power-down according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a waveform of an abnormal AC power-down according to an embodiment of the present invention;

fig. 8 is a flowchart of a specific example of a signal detection method in the embodiment of the present invention;

fig. 9 is a schematic block diagram of a specific example of a signal detection apparatus in the embodiment of the present invention;

fig. 10 is a diagram of a specific example of an electronic device in an embodiment of the present invention.

Detailed Description

The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "first", "second", and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are intended to be inclusive and mean, for example, that they may be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

A common two-way CPU system is taken as an example to illustrate the prior art scheme, which is specifically shown in fig. 1:

1. after detecting that the CPU is powered on, a PCH (Platform Controller Hub) triggers to generate a PROC-PWRGD signal, wherein the PROC-PWRGD signal is sent by a PCH module and indicates that the power supply of the CPU is stable;

2. the CPLD (Complex Programmable Logic Device) can sample THERMTRIP _ N of the CPU after the PROC _ PWRGD signal is triggered, thus ensuring that the CPLD module can filter THERMTRIP _ N signals of the CPU in the power-up and power-down processes of the system and preventing false alarm caused by the power-up and power-down processes. The CPLD module samples 2 paths of THERMTRIP _ N signals, and if the signals are low level, the signals are written into a register for latching;

3. the CPLD module carries out AND operation on THERMTRIP _ N of the filtered 2 paths of CPUs, namely, the AND gate outputs low level as long as 1 path of THERMTRIP _ N signal is triggered to be low level;

4. the CPLD module delays the signal output by the AND gate by 100us and outputs the signal to THERMTRIP _ N PIN of the PCH module. After detecting THERMTRIP _ N PIN as low level, PCH runs fast down current path, and fast cuts off power supplies of CPU, DIMM and the like;

5. the BMC (Baseboard Management Controller) is provided with a polling mechanism, the register of the CPLD module is polled at an interval of 1-2S, when the register is polled and recorded with THERMTRIP signals and is set, the alarm mechanism is triggered, and the indicator light is controlled to alarm while alarm information is recorded.

As shown in fig. 2 and fig. 3, in a normal situation, the CPLD module controls the power-on logic to sequentially control the vr (voltagestaulator) to power on (including PVCCIO _ CPUx) in sequence. When the output Vout of the VR exceeds the upper threshold of the VR register PWRGD, PWRGD will output high level. The CPLD module will detect the PWRGD of each VR, when the last VRPWRGD is high level, the CPLD module pulls high PCH _ PWROK to the PCH module, and after the PCH module detects that the PCH _ PWROK is high level, the PCH module pulls high PROC _ PWRGD. The power-down logic sequence is opposite, the PCH module pulls down PROC _ PWRGD, the CPLD module pulls down PCH _ PWROK after detecting that PROC _ PWRGD is low level, and sequentially controls each path of VR to power down, when the output Vout of VR is lower than the lower limit of the threshold value set by the VR register PWRGD, the PWRGD outputs low level;

therefore, under normal conditions, the PROC _ PWRGD signal will pull up later than PVCCIO _ CPUx when powered up and will pull down earlier than PVCCIO _ CPUx when powered down, as shown in FIG. 2. Since the THERMTRIP _ N signal of the CPU is OD out, the external is pulled to PVCCIO _ CPUx through a pull-up resistor. Therefore, under normal conditions, the CPLD module does not have the problem of sampling THERMTRIP _ N of the CPU after PROC _ PWRGD is in high level, and can filter the THERMTRIP _ N signal triggered by mistake when the PROC _ PWRGD is in low level, thereby avoiding false alarm caused by mistake triggering in the power-up and power-down processes to a certain extent;

however, there is an abnormal situation that when the power is not completely supplied, the AC is powered off, that is, Vout of each VR exceeds the PWRGD setting threshold upper limit of the VR register, PWRGD of each VR outputs high level, the PCH module sends out PROC _ PWRGD, but the power supply process is not completely completed, at this time, the AC is suddenly powered off, that is, the power line of the PSU power supply is unplugged, but at this time, although the AC is disconnected, because the output of the PSU power supply has a large capacitor, the voltages of the server motherboard do not become low immediately, but become low again after a while. At this time, under the action of a large output capacitor of the PSU power supply, the voltage of the CPLD power supply is not lower than the lower limit and still works, the CPLD module still detects the PWRGD of each VR path, when all the VRPWRGD paths are at a high level, the CPLD module pulls up the PCH _ PWROK to the PCH, and after the PCH module detects that the PCH _ PWROK is at a high level, the PCH module pulls up the PROC _ PWRGD. However, because the capacity of the capacitor is continuously decreased, the output voltage of each VR (including PVCCIO _ CPUx) and the level of PROC _ PWRGD signal are also decreased, and PROC _ PWRGD is post-triggered, there is a very small time period when the output voltage of VR is already low, but the level of PROC _ PWRGD is still high. Since the THERMTRIP _ N signal of the CPU is OD out, the external is pulled to PVCCIO _ CPUx through a pull-up resistor. Therefore, as shown in fig. 3, THERMTRIP _ N of the CPU advances PROC _ PWRGD to become low, and at this time, according to the policy of the CPLD, the CPLD module cannot filter the false alarm of THERMTRIP _ N, and sets the THERMTRIP register, and at this time, if the BMC is still alive, when polling the CPLD register, an alarm mechanism is triggered, and an alarm information is recorded, and an alarm work order is generated, which generates a false alarm. It can be seen that the mechanism of filtering by means of the CPLD module with the PROC _ PWRGD signal cannot completely avoid THERMTRIP false alarm. In order to solve the problem that the detection mode of the THERMTRIP # signal of the CPU is poor in accuracy in the prior art, the embodiment of the present application provides a new method for detecting the THERMTRIP # signal.

The embodiment of the invention discloses a signal detection method, which is used for a CPLD module, wherein the CPLD module is respectively connected with a PSU power supply module and a PCH module, and the PSU power supply module is internally provided with a power line insertion state detection module. As shown in fig. 5, the embodiment of the present application takes a two-way CPU system as an example. As shown in fig. 4, the method includes the steps of:

step 101, when detecting that a PWRGD signal of a last VR power supply chip is triggered, sending a PCH _ PWROK signal to the PCH module;

illustratively, after the power-on and the startup, the CPLD module controls each VR to be powered on in sequence, and when the triggering of the PWRGD of the last VR power supply chip is detected, a PCH _ PWROK signal is sent to the PCH module, so that the PCH module sends PROC _ PWRGD to the CPLD module after detecting the PCH _ PWROK signal. When the main voltage is effective and stable, a PCH _ PWROK signal is emitted to the PCH module to inform the PCH module that each RUN voltage is ready.

And step 102, when the received PROC _ PWRGD signal sent by the PCH module is in a high level, determining whether to respond to the detection operation to the power-off indication signal of the accessed CPU according to the detection result fed back by the power line insertion state detection module.

Illustratively, the power line insertion state detection module may adopt, but is not limited to, a proximity switch detection mode, a photoelectric detection mode, an insertion level detection mode, and the like. The proximity switch is of an inductive type, a capacitive type, a Hall type, an alternating current type, a direct current type and the like, the switch detection circuit is arranged in the PSU, the metal or the magnet is arranged in the AC power line plug, and when the AC power line is plugged in or pulled out, the switch detection circuit in the PSU can output '0' state and '1' state, so that the CPLD module can judge whether the AC power line is plugged in or pulled out by judging the '0' state and the '1' state; the photoelectric detection mode is that a photoelectric geminate transistor is arranged in a power socket of the PSU, when an AC power line is inserted, the photoelectric geminate transistor is shielded, and the output of a detection circuit is 0; when the AC power line is pulled out, the photoelectric geminate transistor is not shielded any more, the output of the detection circuit is 1, and the CPLD module can judge whether the AC power line is plugged in or pulled out by judging the states of 0 and 1.

As an alternative embodiment of the present invention, step 102 includes: and if the power line is determined to be in the non-inserted state according to the detection result fed back by the power line insertion state detection module, the detection operation of the power-off indication signal of the accessed CPU is not responded.

As an optional implementation manner of the present invention, step 102 further includes: and if the power line is determined to be in the insertion state according to the detection result fed back by the power line insertion state detection module, responding to the power-off indication signal of the accessed CPU for detection operation.

As an optional embodiment of the present invention, after step 101, the method further comprises: and when the PROC _ PWRGD signal sent by the PCH module is received to be at a low level, the detection operation of the power-off indication signal of the accessed CPU is not responded.

The signal detection method provided by the invention is used for a CPLD module which is respectively connected with a PSU power supply module and a PCH module, wherein the PSU power supply module is provided with a power line insertion state detection module, when the PWRGD signal trigger of the last VR power supply chip is detected, a PCH _ PWROK signal is sent to the PCH module, and when the PROC _ PWRGD signal sent by the PCH module is received to be in a high level, whether the detection operation is responded to the power-off indication signal of the accessed CPU is determined according to the detection result fed back by the power line insertion state detection module. The power line insertion state detection result is added to the condition that the CPLD module filters THERMATRIP _ N of the CPU, so that THERMTRIP false alarm generated in the abnormal power-off process can be effectively filtered, the THERMTRIP detection accuracy is improved, the false alarm work order can be greatly reduced, and the after-sale and operation and maintenance burden is greatly reduced.

As an optional embodiment of the present invention, the method further comprises: when a power-off indication signal of any CPU is detected, the power-off indication signal is sent to the PCH module, so that the PCH module responds to quick power-off operation when detecting that the power-off indication signal is at a low level.

Exemplarily, if THERMTRIP _ N of the CPU has a trigger, it is determined that it is detected that the real THERMTRIP, CPLD module delays the THERMTRIP _ N signal and then sends the delayed signal to the THERMTRIP _ N PIN of the PCH module, and when the PCH module detects that the THERMTRIP _ N PIN is at a low level, the PCH module starts a fast power-down procedure; if neither of the CPU's THERMTRIP _ N triggers, a loop is made to determine THERMTRIP _ N current state.

As an optional embodiment of the present invention, the method further comprises: recording the detected power-off indication signal to a register.

As an alternative embodiment of the present invention, as shown in fig. 5, the CPLD module is connected to the BMC module; after recording the detected power-off indication signal to a register, the method further comprises: and setting the register, so that the BMC responds to trigger alarm operation when polling is carried out until the register is set.

Illustratively, when the CPLD module judges that THERMTRIP signals are triggered, the CPLD module will simultaneously record the internal registers, the BMC module will poll the registers of the CPLD module at an interval of 1-2S, and when the register storing THERMTRIP is polled to be set, the CPLD module will trigger an alarm mechanism, and simultaneously record alarm information, and control the indicator lamp to alarm.

As shown in fig. 5, the present embodiment of the application describes an optimized design method for detecting THERMTRIP _ N signal by using an insertion level detection method as a specific embodiment, a Vin detection circuit is provided in a PSU, so that when an AC power line is inserted, an AC _ OK signal is pulled high, and when the AC power line is pulled out, the AC _ OK signal is pulled low. The delay of the AC _ OK signal and Vin is small and almost simultaneous, so that the AC _ OK signal can reflect the insertion and extraction state of the AC power line in time. As shown in fig. 8, the specific detection process is as follows:

(1) powering on and starting up, sequentially controlling each VR to be powered on by the CPLD module, and sending a PCH _ PWROK signal to the PCH module when detecting PWRGD triggering of the last VR;

(2) after the PCH module detects the PCH _ PWROK signal, a PROC _ PWRGD signal is sent to the CPLD module;

(3) the CPLD module performs AND operation on the PROC _ PWRGD signal and the AC _ OK signal, and then takes the result after the AND operation as a filtering condition to judge the current state of THERMTRIP _ N of the CPU so as to judge whether the THERMTRIP _ N signal is triggered. When PROC _ PWRGD is at low level, and the result after AND operation is at low level, the THERMTRIP _ N signal of the CPU is not sampled; when PROC _ PROC is at a high level, if the AC _ OK signal is at a low level, the and operation result is at a low level, and the THERMTRIP _ N signal of the CPU is not sampled; when PROC _ PROC is high, and when the AC _ OK signal is also high, the and operation results are high, and the THERMTRIP _ N signal of the CPU is sampled.

If THERMTRIP _ N of the CPU has a trigger at this time, the CPU judges that a real THERMTRIP _ N signal is detected, the CPLD module delays the THERMTRIP _ N signal (for example, 100 microseconds) and then sends the signal to THERMTRIP _ N PIN of the PCH module, and the PCH module starts a quick power-off process when detecting that THERMTRIP _ NPIN is low level; if THERMTRIP _ N of all CPUs is not triggered, the current state of THERMTRIP _ N is circularly judged;

(4) when judging that the CPLD module detects the trigger of a real THERMTRIP _ N signal, the CPLD module records the internal registers at the same time, the BMC module polls the registers of the CPLD module at intervals of 1-2S, and when polling the registers recorded with THERMTRIP signal information are set, the CPLD module triggers an alarm mechanism and controls an indicator lamp to alarm while recording alarm information.

As shown in fig. 6 and 7, during power-up, since the PROC _ PWRGD signal is triggered last, THERMTRIP false triggering during power-up can be filtered out when PROC _ PWRGD is actually used as a determination condition. When the power is off, no matter the power is off by normal AC or abnormal AC, the AC _ OK is pulled out along with the AC power line, the reaction is fastest, therefore, THERMTRIP false triggering in the power-off process can be filtered out by actually taking the AC _ OK as a judgment condition.

In order to deal with the situation of sudden AC power-off THERMATRIP false alarm in the power-on process, the AC power line is pulled out through a mechanism of detecting the AC power line, so that the CPLD module does not detect whether the THERMTRIP _ N signal of the CPU is triggered or not after the AC power line is pulled out. The AC power line extraction signal and the PROC _ PWRG are used as filtering conditions, and when the AC power line extraction signal is triggered and the PROC _ PWRG is not triggered, the THERMTRIP _ N signal of the CPU is shielded, so that false alarm can be effectively avoided. Moreover, after the AC power line is pulled out, the duration is short, the power-down is completed within 3-5S generally, and the probability that the CPU triggers the real THERMTRIP _ N signal is extremely low in the time, so that the scheme described in the embodiment of the application is effective. And when the Power line insertion state is detected by adopting an insertion level detection mode, the used AC _ OK signal is a signal in a CRPS (common Redundant Power supplies) Power standard specification, and the detection can be realized without additional change, so that the realization mode is simple, and the detection cost is saved.

The embodiment of the invention also discloses a signal detection device which is used for the CPLD module, the CPLD module is respectively connected with the PSU power module and the PCH module, and the PSU power module is internally provided with a power line insertion state detection module. As shown in fig. 9, the apparatus includes:

a first signal sending module 201, configured to send a PCH _ PWROK signal to the PCH module when detecting that a PWRGD signal of a last VR power chip is triggered; for details, reference is made to the description of the corresponding parts of the above embodiments, which are not repeated herein.

A first determining module 202, configured to determine whether to respond to a detection operation for a power-off indication signal of an accessed CPU according to a detection result fed back by the power line insertion status detecting module when the received PROC _ PWRGD signal sent by the PCH module is at a high level. For details, reference is made to the description of the corresponding parts of the above embodiments, which are not repeated herein.

The signal detection device provided by the invention is used for a CPLD module which is respectively connected with a PSU power supply module and a PCH module, wherein the PSU power supply module is provided with a power line insertion state detection module, when the PWRGD signal trigger of the last VR power supply chip is detected, a PCH _ PWROK signal is sent to the PCH module, and when the PROC _ PWRGD signal sent by the PCH module is received to be in a high level, whether the detection operation is responded to the power-off indication signal of the accessed CPU is determined according to the detection result fed back by the power line insertion state detection module. The detection result of the power line insertion state is added into the condition that the CPLD module filters the CPU THERMATRIP _ N, so that THERMTRIP false reports generated in the abnormal power-off process can be effectively filtered, the detection accuracy of THERMTRIP is improved, a false alarm work order can be greatly reduced, and the burden of after-sale and operation and maintenance is greatly lightened.

As an optional embodiment of the present invention, the determining module includes: and the first determining submodule is used for not responding to the detection operation of the power-off indication signal of the accessed CPU if the power line is determined to be in the non-inserted state according to the detection result fed back by the power line insertion state detection module. For details, reference is made to the description of the corresponding parts of the above embodiments, which are not repeated herein.

As an optional embodiment of the present invention, the determining module further includes: and the second determining submodule is used for responding to the detection operation to the power-off indication signal of the accessed CPU if the power line is determined to be in the inserting state according to the detection result fed back by the power line inserting state detection module. For details, reference is made to the description of the corresponding parts of the above embodiments, which are not repeated herein.

As an optional embodiment of the present invention, the apparatus further comprises: and the second signal sending module is used for sending the power-off indication signal to the PCH module when the power-off indication signal of any CPU is detected, so that the PCH module responds to quick power-off operation when the power-off indication signal is detected to be at a low level. For details, reference is made to the description of the corresponding parts of the above embodiments, which are not repeated herein.

As an optional embodiment of the present invention, the apparatus further comprises: and the second determination module is used for not responding to the detection operation of the power-off indication signal of the accessed CPU when the PROC _ PWRGD signal sent by the PCH module is received to be low level. For details, reference is made to the description of the corresponding parts of the above embodiments, which are not repeated herein.

As an optional embodiment of the present invention, the apparatus further comprises: and the recording module is used for recording the detected power-off indication signal to a register. For details, reference is made to the description of the corresponding parts of the above embodiments, which are not repeated herein.

As an optional embodiment of the present invention, the apparatus further comprises: and the setting module is used for setting the register so that the BMC responds to trigger alarm operation when polling the register and setting the register. For details, reference is made to the description of the corresponding parts of the above embodiments, which are not repeated herein.

An embodiment of the present invention further provides an electronic device, as shown in fig. 10, the electronic device may include a processor 401 and a memory 402, where the processor 401 and the memory 402 may be connected by a bus or in another manner, and fig. 10 illustrates an example of a connection by a bus.

Processor 401 may be a Central Processing Unit (CPU). The Processor 401 may also be other general purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, or combinations thereof.

The memory 402, which is a non-transitory computer-readable storage medium, may be used for storing non-transitory software programs, non-transitory computer-executable programs, and modules, such as program instructions/modules corresponding to the signal detection method in the embodiment of the present invention. The processor 401 executes various functional applications and data processing of the processor by executing non-transitory software programs, instructions and modules stored in the memory 402, that is, implements the signal detection method in the above method embodiment.

The memory 402 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created by the processor 401, and the like. Further, the memory 402 may include high speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, memory 402 may optionally include memory located remotely from processor 401, which may be connected to processor 401 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The one or more modules are stored in the memory 402 and, when executed by the processor 401, perform the signal detection method in the embodiment shown in fig. 4.

The details of the electronic device may be understood with reference to the corresponding related description and effects in the embodiment shown in fig. 4, and are not described herein again.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic Disk, an optical Disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a Flash Memory (Flash Memory), a Hard Disk (Hard Disk Drive, abbreviated as HDD) or a Solid State Drive (SSD), etc.; the storage medium may also comprise a combination of memories of the kind described above.

Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A signal detection method is characterized in that the signal detection method is used for a CPLD module, the CPLD module is respectively connected with a PSU power supply module and a PCH module, wherein a power line insertion state detection module is arranged in the PSU power supply module; the method comprises the following steps:

when detecting that a PWRGD signal of a last VR power supply chip is triggered, sending a PCH _ PWROK signal to the PCH module;

and when the PROC _ PWRGD signal sent by the PCH module is received to be at a high level, determining whether to respond to the detection operation to the power-off indication signal of the accessed CPU according to the detection result fed back by the power line insertion state detection module.

2. The method as claimed in claim 1, wherein when receiving a high PROC _ PWRGD signal sent by the PCH module, determining whether to respond to a detection operation with a power-off indication signal of an accessed CPU according to a detection result fed back by the power line insertion status detection module comprises:

and if the power line is determined to be in the non-inserted state according to the detection result fed back by the power line insertion state detection module, the detection operation of the power-off indication signal of the accessed CPU is not responded.

3. The method as claimed in claim 1, wherein when receiving a high PROC _ PWRGD signal sent by the PCH module, determining whether to respond to a detection operation to a power-off indication signal of an accessed CPU according to a detection result fed back by the power line insertion status detection module, further comprises:

and if the power line is determined to be in the insertion state according to the detection result fed back by the power line insertion state detection module, responding to the power-off indication signal of the accessed CPU for detection operation.

4. The method of claim 3, further comprising:

when a power-off indication signal of any CPU is detected, the power-off indication signal is sent to the PCH module, so that the PCH module responds to quick power-off operation when detecting that the power-off indication signal is at a low level.

5. The method of claim 1, wherein after sending a PCH PWROK signal to the PCH module upon detection of PWRGD signal trigger of a last VR power chip, the method further comprises:

and when the PROC _ PWRGD signal sent by the PCH module is received to be at a low level, the detection operation of the power-off indication signal of the accessed CPU is not responded.

6. The method of claim 4, further comprising: recording the detected power-off indication signal to a register.

7. The method of claim 6, wherein the CPLD module is connected with the BMC module; after the recording the detected power-off indication signal to a register, the method further comprises:

and setting the register, so that the BMC responds to trigger alarm operation when polling the register to be set.

8. A signal detection device is characterized in that the signal detection device is used for a CPLD module, the CPLD module is respectively connected with a PSU power supply module and a PCH module, wherein a power line insertion state detection module is arranged in the PSU power supply module; the device comprises:

the first signal sending module is used for sending a PCH _ PWROK signal to the PCH module when detecting that the PWRGD signal of the last VR power supply chip is triggered;

and the first determining module is used for determining whether to respond to the detection operation to the power-off indication signal of the accessed CPU according to the detection result fed back by the power line insertion state detecting module when the received PROC _ PWRGD signal sent by the PCH module is in a high level.

9. An electronic device, comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to cause the at least one processor to perform the steps of the signal detection method according to any one of claims 1-7.

10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the signal detection method according to any one of claims 1 to 7.