CN114355299A - Radar echo signal detection method, device, system and storage medium - Google Patents

Abstract

The embodiment of the invention provides a method, a device and a system for detecting radar echo signals and a storage medium. The method comprises the following steps: obtaining a plurality of discrete data points of an original analog echo signal of a detection signal period to obtain a data set; determining a detection processing clock period corresponding to the detection signal based on the rising edge of the detection signal to obtain a reference clock period; determining sampling points of which the amplitudes of the sampling points in the reference clock period do not exceed a first preset threshold value to obtain reference sampling points; taking the product of the sampling clock period and the number of reference sampling points as the detection delay time; and performing delay processing on discrete data points in the data set based on the detection delay time length to obtain a processed data set. The invention can improve the accuracy of echo simulation, meet the requirement of radar target echo simulation and facilitate the improvement of the reliability of radar performance test.

Description

Radar echo signal detection method, device, system and storage medium

Technical Field

The present invention relates to the field of echo simulation technologies, and in particular, to a method, an apparatus, a system, and a storage medium for detecting a radar echo signal.

Background

At present, when radar target echo simulation is performed, a high-speed ADC (Analog-to-digital converter) is generally used to collect a radar pulse signal, transmit the collected signal to an FPGA (Field-Programmable Gate Array) to perform detection processing so as to determine a rising edge time of the detected signal, delay the signal based on the rising edge time, and then perform signal modulation and other operations, so as to simulate a target echo signal, that is, a target simulated echo signal. After the target simulation echo signal is received by the radar, the performance of the radar (such as radar ranging precision) can be tested.

Typically, the sampling rate of the ADC is typically above 1GSPS, while the processing frequency of the FPGA is typically within 350 MHz. For example, the sampling rate of the ADC is 2GSPS, the sampling clock period of the ADC is 500ps, the detection processing frequency of the FPGA is 250MHz, the detection processing clock period of the FPGA is 4ns, and the detection accuracy is the detection processing clock period of one FPGA, that is, the detection accuracy is ± 2 ns. It can be seen that such detection accuracy cannot meet the requirement of radar target echo simulation, and the difference between the target simulated echo signal obtained at the detection accuracy and the target echo signal received when the radar actually detects the target is large, which will result in the reliability of radar performance test being reduced.

Disclosure of Invention

The embodiment of the invention aims to provide a radar echo signal detection method, a radar echo signal detection device, a radar echo signal detection system and a radar echo signal detection storage medium, which can improve the accuracy of echo simulation, meet the requirement of radar target echo simulation and facilitate the improvement of the reliability of radar performance test. The specific technical scheme is as follows:

the invention provides a detection method of a radar echo signal, which comprises the following steps:

obtaining a plurality of discrete data points of an original analog echo signal of a detection signal period to obtain a data set, wherein the detection signal comprises a pulse level signal generated based on a sampling point of a radar pulse signal;

determining a detection processing clock period corresponding to the detection signal based on the rising edge of the detection signal to obtain a reference clock period, and determining a sampling point of which the amplitude of the sampling point under the reference clock period does not exceed a first preset threshold value to obtain a reference sampling point;

taking the product of the sampling clock period and the number of the reference sampling points as the detection delay time, wherein the sampling clock period is the clock period for collecting the radar pulse signals;

and performing delay processing on discrete data points in the data set based on the detection delay time to obtain a processed data set, wherein the processed data set is used for generating a processed analog echo signal.

Optionally, the delaying discrete data points in the data set based on the detection delay duration to obtain a processed data set includes:

delaying the delay clock cycle to which the discrete data point belongs by the detection delay time length to obtain a discrete data point with a changed clock cycle, wherein the discrete data points with the changed clock cycle are arranged according to the sequence of the delay clock cycle, the delay clock cycle is the clock cycle of the sampling clock cycle after delaying a preset time length, the preset time length is 2R/v, R is the distance between a radar pulse signal transmitting point and a target point, and v is the signal propagation speed;

and setting the first N discrete data points of the discrete data points with the changed clock period to zero to obtain a processed data set, wherein the N value is the same as the number of the reference sampling points.

Optionally, the obtaining a plurality of discrete data points of the original analog echo signal of one cycle of the detected signal includes:

performing detection processing based on sampling points of the radar pulse signals to obtain detection signals;

carrying out digital down-conversion processing on the sampling point of the radar pulse signal to obtain a processed sampling point;

delaying the processed sampling point of one detection signal period based on the rising edge time of the detection signal and the preset time length to obtain delay processing data;

respectively carrying out amplitude modulation processing and Doppler modulation processing on the delay processing data to obtain modulation processing data;

and carrying out digital up-conversion processing on the modulation processing data to obtain a plurality of discrete data points of the original analog echo signal of a detection signal period.

Optionally, the method for generating the detection signal includes:

comparing the amplitudes of the plurality of sampling points in the same detection processing clock period with a second preset threshold value respectively to obtain a plurality of comparison results;

obtaining detection values corresponding to the sampling points based on the comparison result to obtain a plurality of detection values; the detection value is 0 or 1; when the detection value is 0, the amplitude of the sampling point is smaller than the second preset threshold value; when the detection value is 1, the amplitude of the sampling point is not less than the second preset threshold value;

performing or operation on the detection values to obtain the amplitude of a detection signal in the detection processing clock period;

the detection signal is generated based on the amplitude of the detection signal in a plurality of successive detection processing clock cycles.

Optionally, the method for generating the detection signal includes:

the amplitudes of the sampling points in the same detection processing clock period are subjected to addition operation to obtain an addition operation result;

setting the amplitude of the detection signal in the detection processing clock period to be 1 under the condition that the addition operation result is larger than a third preset threshold value;

setting the amplitude of the detection signal in the detection processing clock period to be 0 under the condition that the addition operation result is not greater than the third preset threshold value;

the detection signal is generated based on the amplitude of the detection signal in a plurality of successive detection processing clock cycles.

Optionally, the method for determining the rising edge of the detection signal includes:

and if at least one of the detection values corresponding to the sampling points in the target detection processing clock period is 0 and at least one of the detection values is 1, and all the detection values corresponding to the sampling points in the next detection processing clock period after the target detection processing clock period are 1, determining the starting time of the target detection processing clock period as the rising edge of the detection signal.

The invention also provides a programmable logic controller, which is configured to the detection method of the radar echo signal.

The present invention also provides an echo simulation system, comprising: the system comprises an analog-to-digital converter, an FPGA and a digital-to-analog converter; the output end of the analog-to-digital converter is connected with the input end of the FPGA, and the output end of the FPGA is connected with the input end of the digital-to-analog converter;

the analog-to-digital converter transmits a plurality of discrete data points of a raw analog echo signal to the FPGA;

the FPGA is configured as the detection method of the radar echo signal;

and the FPGA transmits the processed data set to the digital-to-analog converter so that the digital-to-analog converter generates a processed analog echo signal based on the processed data set.

The present invention also provides a radar echo signal detecting apparatus, including:

the data acquisition module is used for acquiring a plurality of discrete data points of an original analog echo signal in a detection signal period to obtain a data set; the detection signal is a pulse level signal generated based on a sampling point of the radar pulse signal;

a reference clock period obtaining module, configured to determine, based on a rising edge of the detection signal, a detection processing clock period corresponding to the detection signal, and obtain a reference clock period; determining sampling points of which the amplitudes of the sampling points in the reference clock period do not exceed a first preset threshold value to obtain reference sampling points;

the detection delay time length determining module is used for taking the product of the sampling clock period and the number of the reference sampling points as the detection delay time length; the sampling clock period is the clock period for collecting the radar pulse signal;

the delay processing module is used for carrying out delay processing on discrete data points in the data set based on the detection delay time length to obtain a processed data set; the processed data set is used to generate a processed simulated echo signal.

The present invention also provides a computer-readable storage medium having stored thereon a program which, when executed by a processor, implements the above-described radar echo signal detection method.

The embodiment of the invention provides a radar echo signal detection method, a radar echo signal detection device, a radar echo signal detection system and a storage medium, wherein a plurality of discrete data points of an original analog echo signal in a detection signal period are obtained to obtain a data set; determining a detection processing clock period to which a rising edge of a detection signal belongs to obtain a reference clock period; determining sampling points of which the amplitudes of the sampling points in the reference clock period do not exceed a first preset threshold value to obtain reference sampling points; taking the product of the sampling clock period and the number of reference sampling points as the detection delay time; delay processing is carried out on discrete data points in the data set based on the detection delay time length, and a processed data set is obtained; the processed data set is used to generate a processed simulated echo signal having an accuracy that is higher than an accuracy of the original simulated echo signal. The invention can improve the accuracy of echo simulation, meet the requirement of radar target echo simulation and facilitate the improvement of the reliability of radar performance test.

Of course, it is not necessary for any product or method of practicing the invention to achieve all of the above-described advantages at the same time.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a modulo detection provided by an embodiment of the present invention;

FIG. 2 is a schematic diagram of a radar target distance and an echo delay according to an embodiment of the present invention;

FIG. 3 is a flowchart of a method for detecting a radar echo signal according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of generating an original simulated echo signal according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a detection process according to an embodiment of the present invention;

FIG. 6 is a block diagram of an echo simulation system according to an embodiment of the present invention;

fig. 7 is a structural diagram of a radar echo signal detection device according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In testing the performance of the radar, a detection target echo signal generated by the radar is simulated in many cases. When radar target echo simulation is performed, a high-speed ADC (Analog-to-digital converter) is generally used to collect radar pulse signals, the sampling rate of the ADC is generally above 1GSPS, the ADC converts continuous radar pulse signals into a plurality of discrete radar pulse signals, and then transmits the collected signals to an FPGA (Field-Programmable Gate Array), and the processing frequency of the FPGA is generally within 350 MHz.

In the radar target echo simulation process, a plurality of discrete radar pulse signals are obtained after the radar pulse signals are subjected to analog-to-digital conversion by an ADC (analog-to-digital converter), the acquired signals are subjected to detection processing, so that envelope signals (also called detection signals) are obtained to determine the rising edge time of the radar pulse signals, and the target simulation echo signals can be simulated by delaying the signals based on the rising edge time and then performing signal modulation and other operations.

And when the collected radar pulse signals are detected, a mode detection method is adopted. As shown in fig. 1, since the detection processing clock of the FPGA is limited, the signal collected by the ADC is transmitted to the FPGA, and is generally a plurality of parallel data streams. For example, the sampling rate of the ADC is 1GSPS, the processing clock of the FPGA is 250MHz, and the FPGA divides the ADC data into 4 parallelism degrees for processing, where the 4 parallelism degrees are interleaved and parallel. Assume that the data stream transmitted to the FPGA after the ADC acquisition is: a is₀,a₁,a₂……a_nWherein n is a natural number. The 4 parallelism degrees of the FPGA are respectively as follows:

parallelism 1(din _ 0): a is₀，a₄，a₈……a_4n

Parallelism 2(din _ 1): a is₁，a₅，a₉……a_4n+1

Parallelism 3(din _ 2): a is₂，a₆，a₁₀……a_4n+2

Parallelism 4(din _ 3): a is₃，a₇，a₁₁……a_4n+3

The steps of the modulo detection method are as follows:

1) and performing modulo processing on the data of each parallelism.

The acquired signals are obtained after the radar pulse signals are dispersed, the radar pulse signals are sine wave signals, and the size of the signals is positive or negative, so that the data needs to be subjected to modulo processing, and the negative value is converted into the positive value.

2) And adding the data with the same parallelism after modulus calculation to obtain an accumulated value.

The purpose of the addition operation is to determine a plurality of data of the same detection processing clock period together, so that all the data of the same detection processing clock period are 0. And when the radar pulse signal is not detected, adding the data with the same parallelism after the modulus calculation to obtain a numerical value of 0. When the radar pulse signal is detected, the numerical value obtained by adding the data with the same parallelism after the modulus is solved is not 0.

3) And comparing the accumulated value with a preset threshold value, wherein if the accumulated value is larger than the preset threshold value, the detection signal is at a high level, and if the accumulated value is smaller than the preset threshold value, the detection signal is at a low level, so that the detection signal is generated.

The rising edge time of the detection signal is used as the starting time of the radar pulse signal. However, as can be seen from fig. 1, the acquired radar pulse signal a occurs at the time of the rising edge of the detection signal₀And a₁A value of 0, a₂And a₄A numerical value other than 0. That is, the radar pulse signal start time obtained by the above-described mode detection method is deviated from the actual radar pulse signal start time. The sampling rate of the ADC is 1GSPS, the sampling clock period of the ADC is 1ns, the detection processing frequency of the FPGA is 250MHz, the detection processing clock period of the FPGA is 4ns, and the detection precision is the detection processing clock period of the FPGA, namely the detection precision is +/-2 ns. Therefore, the detection processing frequency of the FPGA is 250MHz, and the 1ns sampling clock period of the ADC cannot be accurately obtained.

When a radar ranging accuracy test is performed, a radar target distance needs to be calculated by using a radar pulse signal starting time obtained by a detection method, as shown in fig. 2, the radar target distance and an echo delay are schematic diagrams, a rising edge time of an input signal is a detected signal rising edge time obtained by the detection method, a distance between a target and a radar is assumed to be R, a corresponding delay is D ═ 2R/v, v is a propagation speed of a radar pulse signal, and optionally v may be a light speed. Based on the above formula, it can be seen that if the accuracy of the start time of the radar pulse signal is not high, the original echo simulation signal obtained during echo simulation will deviate from the actual echo simulation signal, so that the target distance simulated based on the target original echo simulation signal is inconsistent with the actual target distance, which will reduce the reliability of the radar performance test.

Based on the above problem that the accuracy of the radar pulse signal obtained by the mode detection method is not high, which results in the reliability of the radar performance test being reduced, the present invention provides a method for detecting a radar echo signal, as shown in fig. 3, the method includes:

step 301: a plurality of discrete data points of a raw analog echo signal of one detection signal period are obtained to obtain a data set, wherein the detection signal comprises a pulse level signal generated based on a sampling point of a radar pulse signal.

In this embodiment, a method for obtaining a plurality of discrete data points of an original analog echo signal in a detection signal period is described with reference to fig. 4, as shown in fig. 4, an ADC module performs analog-to-digital conversion on a radar pulse signal to obtain a sampling point of the radar pulse signal; performing detection processing on a detection module based on a sampling point of a radar pulse signal to obtain a detection signal; performing Digital Down-conversion processing on a sampling point of a radar pulse signal in a DDC (Digital Down conversion) module to obtain a processed sampling point; delaying the processed sampling point of one detection signal period based on the rising edge time and the preset time length of the detection signal in a delay module to obtain delay processing data; respectively carrying out amplitude modulation processing and Doppler modulation processing on the delay processing data in a modulation module to obtain modulation processing data; performing Digital Up-conversion processing on the modulation processing data at a DUC (Digital Up conversion) module to obtain a plurality of discrete data points of an original analog echo signal of a detection signal period; a plurality of discrete data points are converted into continuous signals by a DAC (Digital to analog converter) module, so as to obtain original analog echo signals.

The detection signal period is based on the detection signal period obtained by performing the modulo detection processing on the radar pulse signal, a plurality of discrete data points of the original analog echo signal are data of one detection signal period after being processed by the DUC module, and because the data in the data set are generated after being processed by the modulo detection processing, the data in the data set have deviation compared with the actual echo analog signal.

In an alternative embodiment, it is assumed that the sampling rate of the ADC is 2GSPS, the sampling clock period of the ADC is 500ps, the detection processing frequency of the FPGA is 250MHz, the detection processing clock period of the FPGA is 4ns, and the detection precision is one detection processing clock period of the FPGA, that is, the detection precision is ± 2 ns. Thus, the ADC collected data received by the FPGA is 8-parallelism data, the schematic diagram of the detection processing is shown in fig. 5, and the 8 parallelisms are parallelism 1(din _0), parallelism 2(din _1), parallelism 3(din _2), parallelism 4(din _3), parallelism 5(din _4), parallelism 6(din _5), parallelism 7(din _6), and parallelism 8(din _7), respectively.

When detecting, a detection signal generation method is: comparing the amplitudes of a plurality of sampling points in the same detection processing clock period with a second preset threshold value respectively to obtain a plurality of comparison results; obtaining detection values corresponding to the sampling points based on the comparison result to obtain a plurality of detection values; the detection value is 0 or 1; when the detection value is 0, the amplitude of the sampling point is smaller than a second preset threshold value; when the detection value is 1, the amplitude of the sampling point is not less than a second preset threshold value; performing OR operation on the plurality of detection values to obtain the amplitude of the detection signal in the detection processing clock period; the detection signal is generated based on the amplitude of the detection signal in a plurality of successive detection processing clock cycles. It should be noted that the second preset threshold is determined according to the minimum amplitude of the multiple sampling points in the same detection processing clock cycle, and in practical application, it is required to ensure that the selected second preset threshold is greater than 0 and less than or equal to the minimum amplitude of the sampling points, so that the sampling points with the amplitude of 0 and the sampling points with the minimum amplitude can be distinguished by using the second preset threshold, so that the detection value is 0 when the amplitude of the sampling points is less than the second threshold, and is 1 when the amplitude of the sampling points is not less than the second threshold.

In this embodiment, the CLK period in fig. 5 is the detection processing clock period of the FPGA, and there are 8 sampling points, 0,1,2,3,4,5,6, and 7 respectively, for the radar pulse signal in one detection processing clock period, and these 8 sampling points are located in the T1 detection processing clock period. As can be seen from fig. 5, the amplitudes of the radar pulse signals corresponding to the sampling points 0 and 1 are 0, the amplitudes of the two sampling points are smaller than a second preset threshold value, and the detection values corresponding to the parallelism 1 and the parallelism 2 are 0; the amplitudes of the radar pulse signals corresponding to the sampling points 2-7 are not 0, the amplitudes of the six sampling points are larger than a second preset threshold value, and the corresponding detection values at the parallelism degrees 3-8 are 1. The detection values of multiple parallelism degrees are combined into a multi-bit number, and the combination principle is as follows: the detected wave value of parallelism 1 is bit0, the detected wave value of parallelism 2 is bit1, and so on, the detected wave value of parallelism n is bit (n-1), and thus the detected wave value at this detection processing clock cycle is "11111100". After or-ing these 8 detected values, an envelope detection signal at the detection processing clock period T1 is obtained.

For a pulse signal, the detection value of the out-of-pulse signal is a multi-bit number with a value of 0, and the detection value of the in-pulse signal is a multi-bit number other than 0. The time when the detection value changes from the constant 0 value to the non-zero value is the rising edge time of the pulse signal. The detection value at the moment is taken for analysis, and then the rising edge position of the current pulse signal reaching the processing system can be found. The above method can obtain a detection value of "00000000" at the detection processing clock cycle T1, a detection value of "11111100" at the detection processing clock cycle T1, and an or operation of these 8 detection values to obtain a value of 1, and the rising edge time corresponding to this detection processing clock cycle is the start time of the radar pulse signal. Of course, the above method can detect the signal value at the detection processing clock cycle T2-T8 as "11111111", the signal value at the detection processing clock cycle T9 as "01111111", and the signal value at the detection processing clock cycle T10 as "000000000000".

The other detection signal generation method comprises the following steps: the amplitude values of a plurality of sampling points in the same detection processing clock period are subjected to addition operation to obtain an addition operation result; setting the amplitude of the detection signal in the detection processing clock period to be 1 under the condition that the addition operation result is larger than a third preset threshold value; setting the amplitude of the detection signal in the detection processing clock period to be 0 under the condition that the addition operation result is not larger than a third preset threshold value; the detection signal is generated based on the amplitude of the detection signal in a plurality of successive detection processing clock cycles. It should be noted that the third preset threshold may be determined according to the minimum amplitude of the multiple sampling points in the same demodulation processing clock cycle, and in practical applications, it is required to ensure that the selected third preset threshold is greater than 0 and smaller than the minimum amplitude of the sampling points, so that, when the amplitudes of only 1 sampling point in the multiple sampling points in the same demodulation processing clock cycle are not 0, all sampling points whose amplitudes are 0 and at least 1 sampling point whose amplitudes are not 0 may be distinguished by using the third preset threshold, so as to set the amplitude of the demodulation signal to 1 when the addition result is greater than the third preset threshold, and set the amplitude of the demodulation signal to 0 when the addition result is not greater than the third preset threshold.

Step 302: and determining a detection processing clock period corresponding to the detection signal based on the rising edge of the detection signal to obtain a reference clock period, and determining a sampling point of which the amplitude of the sampling point under the reference clock period does not exceed a first preset threshold value to obtain a reference sampling point.

As an alternative embodiment, the method for determining the rising edge of the detection signal includes: when at least one detection value corresponding to the sampling point in the target detection processing clock period is 0 and at least one detection value is 1, and detection values corresponding to the sampling point in the next detection processing clock period after the target detection processing clock period are all 1, the start time of the target detection processing clock period is determined as the rising edge of the detection signal.

Taking the detection processing clock cycle where the rising edge of the detection signal is as the reference clock cycle, as shown in fig. 5, the detection processing clock cycle where the rising edge of the detection signal is as T2, taking the detection processing clock cycle T2 as the reference clock cycle, and determining the sampling point whose amplitude of the sampling point under the reference clock cycle T2 is smaller than the first preset threshold, and optionally, taking the sampling point corresponding to the sampling point whose amplitude is 0 as the reference sampling point. In fig. 5, the reference sample points are sample points 0 and 1. It should be noted that the first preset threshold is determined according to the minimum amplitude of the multiple sampling points in the reference clock period, and in practical application, it is required to ensure that the selected first preset threshold is greater than 0 and smaller than the minimum amplitude of the sampling points, so that the sampling points with the amplitude of 0 and the sampling points with the minimum amplitude can be distinguished by using the first preset threshold, so as to obtain the reference sampling points when the amplitudes of the sampling points do not exceed the first threshold, and the amplitudes of the reference sampling points are 0.

Step 303: taking the product of the sampling clock period and the number of reference sampling points as the detection delay time; the sampling clock period is the clock period for collecting radar pulse signals.

The sampling clock period is the sampling clock period of the ADC for collecting radar pulse signals, when the sampling rate of the ADC is 1GSPS, the sampling clock period of the ADC is 1ns, and when the sampling rate of the ADC is 2GSPS, the sampling clock period of the ADC is 500 ps. And extracting a time difference value between the radar pulse arrival signal and the FPGA clock period leading edge (a time difference value between the real arrival time and the rising edge of the signal envelope detection signal processed by the FPGA), namely, taking the product of the number of 0 in the detection value bit number and the ADC sampling clock period as the detection delay time. As can be seen from fig. 5, the detected rising edge time is earlier than the actual radar pulse signal arrival time by 2 × 500ps — 1ns, so that a delay of 1ns is required based on the rising edge time, that is, the delay difference between the arrival signal and the leading edge of the FPGA clock period is: 2 × 500ps ═ 1 ns.

For an 8-bit detection value, the corresponding delay difference (i.e., the detection delay period) is shown in table 1.

TABLE 1 correspondence table of detection values and delay differences

It should be noted that, normally, the data collected by the ADC enters the FPGA in time sequence, and the data to the FPGA is processed in parallel by interleaving. Therefore, in the binary data corresponding to the multi-bit number composed of the detection values, the bit numbers with the value of "1" and the bit numbers with the value of "0" are respectively continuous and uninterrupted. If the discontinuity phenomena of '1' and '0' occur, the quality of the externally input signal is not good or the signal has burrs. At this time, the FPGA skips the detection processing clock cycle and detects the next detection processing clock cycle.

Step 304: delay processing is carried out on discrete data points in the data set based on the detection delay time length, and a processed data set is obtained; the processed data set is used to generate a processed simulated echo signal.

Because the rising edge moment of the detection signal obtained by the modulus detection method has detection delay time, a plurality of discrete data points of the original analog echo signal need to be subjected to delay processing in the same way, and the accuracy of the processed analog echo signal can be improved by performing delay processing on the discrete data points in the data set.

As an optional implementation, step 304 includes: delaying the delay clock period to which the discrete data point belongs by the delay detection delay time length to obtain the discrete data point with the changed clock period, wherein the discrete data point with the changed clock period is arranged according to the sequence of the delay clock period, the delay clock period is the clock period after the sampling clock period delays by the preset time length, the preset time length is 2R/v, R is the distance between the radar pulse signal transmitting point and the target point, and v is the signal propagation speed; setting the first N discrete data points of the discrete data points with the changed clock period to zero to obtain a processed data set; wherein, the N value is the same as the number of the reference sampling points.

Based on the 8-parallelism ADC acquisition data received by the FPGA shown in fig. 5, through the echo simulation process shown in fig. 4, a plurality of discrete data points of the original simulated echo signal can be obtained as shown below:

parallelism 1 (path 1): a is₀，a₈，a₁₆……a_8n

Parallelism 2 (2 nd path): a is₁，a₉，a₁₇……a_8n+1

Parallelism 3 (path 3): a is₂，a₁₀，a₁₈……a_8n+2

Parallelism 4 (4 th path): a is₃，a₁₁，a₁₉……a_8n+3

Parallelism 5 (path 5): a is₄，a₁₂，a₂₀……a_8n+4

Parallelism 6 (way 6): a is₅，a₁₃，a₂₁……a_8n+5

Parallelism 7 (7 th): a is₆，a₁₄，a₂₂……a_8n+6

Parallelism 8 (path 8): a is₇，a₁₅，a₂₃……a_8n+7

As can be seen from fig. 5, the delay difference is 1ns, and the processed data obtained by performing the delay processing in step 304 is as follows:

parallelism 1 (path 1): 0, a₆，a₁₄……a_8n-2

Parallelism 2 (2 nd path): 0, a₇，a₁₅……a_8n-1

Parallelism 3 (path 3): a is₀，a₈，a₁₆……a_8n

Parallelism 4 (4 th path): a is₁，a₉，a₁₇……a_8n+1

Parallelism 5 (path 5): a is₂，a₁₀，a₁₈……a_8n+2

Parallelism 6 (way 6): a is₃，a₁₁，a₁₉……a_8n+3

Parallelism 7 (7 th): a is₄，a₁₂，a₂₀……a_8n+4

Parallelism 8 (path 8): a is₅，a₁₃，a₂₁……a_8n+5

Therefore, high-precision delay processing of the original analog echo signal is completed, and the processed analog echo signal generated based on the processed data set can meet the requirement of radar target echo simulation so as to improve the reliability of radar performance test. In addition, the invention does not increase the hardware cost and is convenient for upgrading.

The invention also provides a programmable logic controller, which is configured to the detection method of the radar echo signal in steps 301 to 304.

The present invention also provides an echo simulation system, as shown in fig. 6, including: analog-to-digital converter 61(ADC), FPGA62, and digital-to-analog converter 63 (DAC); the output end of the analog-to-digital converter is connected with the input end of the FPGA, and the output end of the FPGA is connected with the input end of the digital-to-analog converter. The analog-to-digital converter transmits a plurality of discrete data points of the original analog echo signal to the FPGA; the FPGA is configured as the radar echo signal detection method in the steps 301-304; and the FPGA transmits the processed data set to a digital-to-analog converter, so that the digital-to-analog converter generates a processed analog echo signal based on the processed data set.

As shown in fig. 6, FPGA62 includes DDC unit 621, detection unit 622, delay unit 623, modulation unit 624, DUC unit 625, delay difference unit 626, and micro-delay unit 627.

After receiving the ADC data, the FPGA performs Digital Down Conversion (DDC) processing by the DDC unit 621 and performs detection processing by the detection unit 622. The DDC performs quadrature demodulation on the if signal and outputs a zero if quadrature signal (IQ signal) to reduce a data rate and facilitate subsequent processing. The detection unit outputs an envelope detection signal as a trigger signal of the delay unit, and the envelope detection signal output by the detection unit is transmitted to the delay difference unit to calculate the delay difference.

The delay process is performed after DDC. The effect of the delay is to model the target echo at distance R. The corresponding relation between the radar target distance and the echo delay is as follows: and t is 2R/c, wherein c is the speed of light. The delay is the time it takes for the electromagnetic wave to travel a double-pass distance. The delay module is realized by caching data in the RAM, reading the data in the RAM after delay t, and completing the simulation of the target distance.

The modulation unit completes amplitude modulation and Doppler modulation on the delayed data so as to simulate amplitude change and speed change of the target.

A Digital Up conversion unit (DUC) that performs Digital quadrature Up conversion processing on the modulated IQ data, outputs an intermediate frequency echo signal, and outputs a multi-parallel output signal.

The micro-delay unit completes high-precision delay processing on the echo signals. The delay difference of the detection output is used, and the envelope detection signal is used as the reference of signal delay to carry out delay fine adjustment of the envelope.

The present invention also provides a radar echo signal detecting apparatus, as shown in fig. 7, including:

the data acquisition module 701 is configured to acquire a plurality of discrete data points of an original analog echo signal in a detection signal period to obtain a data set; the detection signal is a pulse level signal generated based on a sampling point of the radar pulse signal.

The data acquisition module 701 includes:

the device comprises a discrete data point obtaining unit, a sampling unit and a detection unit, wherein the discrete data point obtaining unit is used for carrying out detection processing based on sampling points of radar pulse signals to obtain detection signals; carrying out digital down-conversion processing on a sampling point of the radar pulse signal to obtain a processed sampling point; delaying the processed sampling point of one detection signal period based on the rising edge time and the preset time length of the detection signal to obtain delayed processing data; respectively carrying out amplitude modulation processing and Doppler modulation processing on the delay processing data to obtain modulation processing data; and carrying out digital up-conversion processing on the modulation processing data to obtain a plurality of discrete data points of the original analog echo signal of one detection signal period.

The first detection unit is used for comparing the amplitudes of a plurality of sampling points in the same detection processing clock period with a second preset threshold value respectively to obtain a plurality of comparison results; obtaining detection values corresponding to the sampling points based on the comparison result to obtain a plurality of detection values; the detection value is 0 or 1; when the detection value is 0, the amplitude of the sampling point is smaller than a second preset threshold value; when the detection value is 1, the amplitude of the sampling point is not less than a second preset threshold value; performing OR operation on the plurality of detection values to obtain the amplitude of the detection signal in the detection processing clock period; the detection signal is generated based on the amplitude of the detection signal in a plurality of successive detection processing clock cycles.

The second detection unit is used for performing addition operation on the amplitudes of the multiple sampling points in the same detection processing clock period to obtain an addition operation result; setting the amplitude of the detection signal in the detection processing clock period to be 1 under the condition that the addition operation result is larger than a third preset threshold value; setting the amplitude of the detection signal in the detection processing clock period to be 0 under the condition that the addition operation result is not larger than a third preset threshold value; the detection signal is generated based on the amplitude of the detection signal in a plurality of successive detection processing clock cycles.

A reference clock period obtaining module 702, configured to determine, based on a rising edge of the detection signal, a detection processing clock period corresponding to the detection signal, so as to obtain a reference clock period; and determining the sampling points of which the amplitudes of the sampling points in the reference clock period do not exceed a first preset threshold value to obtain reference sampling points.

A reference clock cycle obtaining module 702, comprising:

and a rising edge determination unit configured to determine the start time of the target detection processing clock cycle as a rising edge of the detected signal if at least one of the detected values corresponding to the sampling points in the target detection processing clock cycle is 0 and at least one of the detected values is 1 and all of the detected values corresponding to the sampling points in the subsequent detection processing clock cycle of the target detection processing clock cycle are 1.

A detection delay time length determining module 703, configured to use the product of the sampling clock period and the number of reference sampling points as the detection delay time length; the sampling clock period is the clock period for collecting radar pulse signals.

A delay processing module 704, configured to perform delay processing on discrete data points in the data set based on the detection delay duration to obtain a processed data set; the processed data set is used to generate a processed simulated echo signal.

A delay processing module 704, comprising:

the delay processing unit is used for delaying the delay clock period to which the discrete data point belongs by the detection delay time length to obtain the discrete data point with the changed clock period, wherein the discrete data point with the changed clock period is arranged according to the sequence of the delay clock period, the delay clock period is the clock period of the sampling clock period after delaying the preset time length, the preset time length is 2R/v, R is the distance between a radar pulse signal transmitting point and a target point, and v is the signal propagation speed; and setting the first N discrete data points of the discrete data points with the changed clock period to zero to obtain a processed data set, wherein the N value is the same as the number of the reference sampling points.

An embodiment of the present invention provides a computer-readable storage medium, on which a program is stored, which, when being executed by a processor, implements the above-mentioned method for detecting a radar echo signal.

An embodiment of the present invention provides an electronic device, as shown in fig. 8, an electronic device 80 includes at least one processor 801, at least one memory 802 connected to the processor 801, and a bus 803; the processor 801 and the memory 802 complete communication with each other through the bus 803; the processor 801 is configured to call program instructions in the memory 802 to execute the above-described radar echo signal detection method. The electronic device herein may be a server, a PC, a PAD, a mobile phone, etc.

The present application also provides a computer program product adapted to execute a program of initializing the steps comprised in the detection method of a radar echo signal as described above, when executed on a data processing device.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, systems and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In a typical configuration, a device includes one or more processors (CPUs), memory, and a bus. The device may also include input/output interfaces, network interfaces, and the like.

The memory may include volatile memory in a computer readable medium, Random Access Memory (RAM) and/or nonvolatile memory such as Read Only Memory (ROM) or flash memory (flash RAM), and the memory includes at least one memory chip. The memory is an example of a computer-readable medium.

Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.

All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.

The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims (10)

1. A method for detecting a radar echo signal, comprising:

obtaining a plurality of discrete data points of an original analog echo signal of a detection signal period to obtain a data set, wherein the detection signal comprises a pulse level signal generated based on a sampling point of a radar pulse signal;

determining a detection processing clock period corresponding to the detection signal based on the rising edge of the detection signal to obtain a reference clock period, and determining a sampling point of which the amplitude of the sampling point under the reference clock period does not exceed a first preset threshold value to obtain a reference sampling point;

taking the product of the sampling clock period and the number of the reference sampling points as the detection delay time, wherein the sampling clock period is the clock period for collecting the radar pulse signals;

and performing delay processing on discrete data points in the data set based on the detection delay time to obtain a processed data set, wherein the processed data set is used for generating a processed analog echo signal.

2. The method of claim 1, wherein the delaying discrete data points in the data set based on the detection delay duration to obtain a processed data set comprises:

delaying the delay clock cycle to which the discrete data point belongs by the detection delay time length to obtain a discrete data point with a changed clock cycle, wherein the discrete data points with the changed clock cycle are arranged according to the sequence of the delay clock cycle, the delay clock cycle is the clock cycle of the sampling clock cycle after delaying a preset time length, the preset time length is 2R/v, R is the distance between a radar pulse signal transmitting point and a target point, and v is the signal propagation speed;

and setting the first N discrete data points of the discrete data points with the changed clock period to zero to obtain a processed data set, wherein the N value is the same as the number of the reference sampling points.

3. The method of claim 2, wherein said obtaining a plurality of discrete data points of a raw analog echo signal of a detected signal period comprises:

performing detection processing based on sampling points of the radar pulse signals to obtain detection signals;

carrying out digital down-conversion processing on the sampling point of the radar pulse signal to obtain a processed sampling point;

delaying the processed sampling point of one detection signal period based on the rising edge time of the detection signal and the preset time length to obtain delay processing data;

respectively carrying out amplitude modulation processing and Doppler modulation processing on the delay processing data to obtain modulation processing data;

and carrying out digital up-conversion processing on the modulation processing data to obtain a plurality of discrete data points of the original analog echo signal of a detection signal period.

4. The method for detecting a radar return signal according to claim 1 or 3, wherein the method for generating the detection signal includes:

comparing the amplitudes of the plurality of sampling points in the same detection processing clock period with a second preset threshold value respectively to obtain a plurality of comparison results;

obtaining detection values corresponding to the sampling points based on the comparison result to obtain a plurality of detection values; the detection value is 0 or 1; when the detection value is 0, the amplitude of the sampling point is smaller than the second preset threshold value; when the detection value is 1, the amplitude of the sampling point is not less than the second preset threshold value;

performing or operation on the detection values to obtain the amplitude of a detection signal in the detection processing clock period;

the detection signal is generated based on the amplitude of the detection signal in a plurality of successive detection processing clock cycles.

5. The method for detecting a radar return signal according to claim 1 or 3, wherein the method for generating the detection signal includes:

the amplitudes of the sampling points in the same detection processing clock period are subjected to addition operation to obtain an addition operation result;

setting the amplitude of the detection signal in the detection processing clock period to be 1 under the condition that the addition operation result is larger than a third preset threshold value;

setting the amplitude of the detection signal in the detection processing clock period to be 0 under the condition that the addition operation result is not greater than the third preset threshold value;

the detection signal is generated based on the amplitude of the detection signal in a plurality of successive detection processing clock cycles.

6. The method for detecting a radar echo signal according to claim 4, wherein the method for determining a rising edge of the detected signal includes:

and if at least one of the detection values corresponding to the sampling points in the target detection processing clock period is 0 and at least one of the detection values is 1, and all the detection values corresponding to the sampling points in the next detection processing clock period after the target detection processing clock period are 1, determining the starting time of the target detection processing clock period as the rising edge of the detection signal.

7. A programmable logic controller, characterized in that the programmable logic controller is configured as a method of detection of a radar echo signal according to any of claims 1-6.

8. An echo simulation system, comprising: the system comprises an analog-to-digital converter, an FPGA and a digital-to-analog converter; the output end of the analog-to-digital converter is connected with the input end of the FPGA, and the output end of the FPGA is connected with the input end of the digital-to-analog converter;

the analog-to-digital converter transmits a plurality of discrete data points of a raw analog echo signal to the FPGA;

the FPGA is configured as a method for detecting a radar echo signal according to any one of claims 1 to 6;

and the FPGA transmits the processed data set to the digital-to-analog converter so that the digital-to-analog converter generates a processed analog echo signal based on the processed data set.

9. A radar echo signal detecting apparatus, comprising:

the data acquisition module is used for acquiring a plurality of discrete data points of an original analog echo signal in a detection signal period to obtain a data set; the detection signal is a pulse level signal generated based on a sampling point of the radar pulse signal;

a reference clock period obtaining module, configured to determine, based on a rising edge of the detection signal, a detection processing clock period corresponding to the detection signal, and obtain a reference clock period; determining sampling points of which the amplitudes of the sampling points in the reference clock period do not exceed a first preset threshold value to obtain reference sampling points;

the detection delay time length determining module is used for taking the product of the sampling clock period and the number of the reference sampling points as the detection delay time length; the sampling clock period is the clock period for collecting the radar pulse signal;

the delay processing module is used for carrying out delay processing on discrete data points in the data set based on the detection delay time length to obtain a processed data set; the processed data set is used to generate a processed simulated echo signal.

10. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a program which, when being executed by a processor, implements the method for detecting a radar echo signal according to any one of claims 1 to 6.

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