CN114340171A - Warpage control method of PCB - Google Patents
Warpage control method of PCB Download PDFInfo
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- CN114340171A CN114340171A CN202111679654.8A CN202111679654A CN114340171A CN 114340171 A CN114340171 A CN 114340171A CN 202111679654 A CN202111679654 A CN 202111679654A CN 114340171 A CN114340171 A CN 114340171A
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Abstract
The invention relates to the technical field of PCB manufacturing, in particular to a PCB warpage control method, which comprises the steps that a PCB comprises board layers with different resin contents, when warpage shrinkage imbalance occurs in the PCB, the shrinkage is balanced by adjusting the resin content of the board layers, the shrinkage is the variation distance between the end parts of the PCB before lamination and after lamination, the warpage is the warpage height in the supply direction, and the PCB warpage control method can effectively overcome the problem of board layer warpage caused by PCB lamination.
Description
Technical Field
The invention relates to the technical field of PCB manufacturing, in particular to a warping control method of a PCB.
Background
In conventional PCB fabrication, a material is used to fabricate the PCB by lamination. However, as the transmission signal is faster and faster, the signal transmission requirement can be met by the material with better loss, the signal loss is influenced by the material and is related to the length of the signal wire of each layer, in the conventional PCB wiring design, only 1-2 layers are designed with longer Pcie signal wires, the longer Pcie signal wires need to consume the material with higher level to reduce the loss of the whole group of signal wires, and the signal requirements can be met by the material with conventional level loss due to the fact that the signal wires are shorter in other layers. In actual production, because of the higher material of loss grade is high than conventional grade loss price, for material saving cost, only need select the higher low-loss material base plate of material grade at the longer layer of signal line in the stromatolite design, the conventional loss material base plate of conventional material is selected to other levels, however, because of the low-loss material base plate is different with the material of conventional loss material base plate, the warpage problem appears after the pressfitting easily, after more serious warpage appears in the board, all have great influence to PCB follow-up size collection, the grinding homogeneity of face copper and follow-up PCBA factory subsides dress.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide the PCB warpage control method which can effectively overcome the problem of board layer warpage caused by PCB lamination.
In order to achieve the purpose, the invention provides the following technical scheme:
the PCB comprises board layers with different resin contents, when shrinkage imbalance of the PCB due to warping occurs, the shrinkage is balanced by adjusting the resin contents of the board layers, the shrinkage is the variation distance between the PCB end parts before and after stitching, and the warping amount of the warping is the warping height in the supply direction.
In some embodiments, the ply comprises a substrate and an adhesive layer, and the amount of shrinkage is balanced by adjusting the resin content of the substrate and the adhesive layer.
In some embodiments, the substrate includes a low loss material substrate and a normal loss material substrate, and the shrinkage is balanced by reducing the resin content of the low loss material substrate or by increasing the resin content of the normal loss material substrate when the substrate exhibits shrinkage imbalance for warpage;
when the substrate exhibits shrinkage imbalance for warpage, the shrinkage is balanced by increasing the resin content of the low loss material substrate or by decreasing the resin content of the conventional loss material substrate.
In some embodiments, the calculation formula of the resin adjustment amount of each ply to be adjusted is as follows:
ΔM＝(ΔL/Lis provided with)*MBefore pressing*(aTo be adjusted/aGeneral assembly)/Q
Wherein, Δ M — the resin adjustment amount of the ply to be adjusted;
delta L is the shrinkage between the laminated layers before and after lamination to be adjusted;
Lis provided withThe set length of the laminated board layer is adjusted;
Mbefore pressing-adjusting the resin content before lamination of the plies;
ato be adjusted-the coefficient of thermal expansion of the resin in the ply to be adjusted;
ageneral assembly-the sum of the thermal expansion coefficients of the materials in the PCB;
q is the number of layers to be adjusted.
In some embodiments, the method of measuring the amount of shrinkage comprises the steps of:
s1, manufacturing layer number marks on each plate layer, wherein the layer number marks can be arranged in a straight line when the plate layers are stacked;
s2, recording the layer number identification position on the plate layer, and recording as a first identification position;
s3, after the board layers are laminated, recording the layer number identification position on the laminated board layer, and recording the layer number identification position as a second identification position;
and S4, calculating the difference between the first mark position and the second mark position of each layer number mark to obtain the shrinkage.
In some embodiments, the layer number is identified as a locating circle hole.
In some embodiments, X-rays are used to illuminate the substrate as it is being laminated to obtain the layer number identifying location.
In some embodiments, the substrate is composed of a resin and a glass cloth, the glass cloth being embedded in the resin.
The warpage control method of the PCB has the beneficial effects that:
(1) according to the warpage control method of the PCB, the resin content of the board layers is changed, so that the board layers are balanced in the shrinkage direction, the flatness of the whole PCB can be kept even if the board layers with different resin contents are used, and the PCB with high transmission speed can be manufactured at low cost.
(2) The warping control method of the PCB can manufacture the PCB with flat surface and low cost, and is suitable for large-scale production and application.
Drawings
FIG. 1 is a schematic view of an embodiment of under-substrate warpage.
FIG. 2 is a schematic diagram of warpage-providing on a substrate according to an embodiment.
FIG. 3 is a schematic diagram illustrating calculation of shrinkage before and after bonding of a substrate according to an embodiment.
Fig. 4 is a schematic diagram of layer number marking of the substrate of the embodiment.
Fig. 5 is a schematic illustration of layer number labeling after lamination of layers of an embodiment.
Detailed Description
Preferred embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present invention are shown in the drawings, it should be understood that the present invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It is to be understood that, although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present invention. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
Examples
In the method for controlling warpage of a PCB disclosed in this embodiment, the PCB includes board layers having different resin contents, and when shrinkage imbalance of warpage of the PCB occurs, shrinkage is balanced by adjusting the resin contents of the board layers. As shown in fig. 3, the shrinkage is a variable distance between the PCB end before and after the pressing, and the warpage amount is a warpage height in the supply direction.
According to the warping control method, the resin content of the board layers is changed, so that the board layers compete in the shrinkage direction, the flatness of the whole PCB can be kept even if the board layers with different resin contents are used, and the PCB with high transmission speed can be manufactured at low cost.
Specifically, the sheet layer includes a substrate and an adhesive layer, and the amount of shrinkage can be balanced by adjusting the resin content of the substrate and the adhesive layer.
In this embodiment, the substrates include a low-loss material substrate and a normal-loss material substrate, the resin content of the low-loss material substrate is different from the resin content of the normal-loss material substrate, and when the substrate suffers from shrinkage imbalance of warpage (shown in fig. 1), the shrinkage is balanced by reducing the resin content of the low-loss material substrate or by increasing the resin content of the normal-loss material substrate;
when the substrate experiences a shrinkage imbalance for warpage (shown in fig. 2), the shrinkage is balanced by increasing the resin content of the low-loss material substrate, or by decreasing the resin content of the conventional loss material substrate,
when the difference of the shrinkage is not large, the PCB after lamination does not have obvious warping problem, and resin adjustment can not be carried out.
The resin content in low-loss material base plate or the conventional loss material base plate is changed to this embodiment to make the shrink direction of low-loss material base plate and the shrink direction of conventional loss material base plate balance, make even use low-loss material base plate and conventional loss material base plate also can keep PCB holistic roughness, guaranteed also can manufacture the fast PCB of transmission speed under the low-cost.
In this embodiment, the substrate is composed of resin and glass fiber cloth, the glass fiber cloth is embedded in the resin, and two side surfaces of the substrate are covered with copper foils, and in this embodiment, the thermal expansion coefficients of the components are as shown in table 1:
TABLE 1
In the lamination design, the copper clad material is copper, and the pattern and the area of the copper are not changed, so that the thermal expansion coefficient of the copper is not changed; the components of the substrate are resin and glass fiber cloth, the thickness of the substrate cannot be changed in the original design, but the mixture ratio of the resin and the glass fiber cloth can be changed. Since the resin thermal expansion coefficient is much larger than that of the glass cloth: increasing the resin content in the substrates increases the thermal shrinkage after lamination, whereas decreasing the resin content decreases the thermal shrinkage after lamination of the substrates, as shown in table 2,
TABLE 2
Resin content in the low-loss material substrate or the conventional loss material substrate is changed, so that the shrinkage characteristic of the low-loss material substrate is balanced with that of the conventional loss material substrate, the overall flatness of the PCB can be kept even if the low-loss material substrate and the conventional loss material substrate are used, and the PCB with high transmission speed can be manufactured at low cost.
In this embodiment, the parameters of the PCB before the substrate lamination are shown in table 3:
TABLE 3
The shrinkage is balanced by adjusting the resin content of the low-loss material substrate, and the calculation formula of the resin adjustment amount is as follows:
ΔM＝(ΔL/Lis provided with)*MBefore pressing*(aTo be adjusted/aGeneral assembly)/Q
Wherein, Δ M — the resin adjustment amount of the ply to be adjusted;
delta L is the shrinkage between the laminated layers before and after lamination to be adjusted;
Lis provided withThe set length of the laminated board layer is adjusted;
Mbefore pressing-adjusting the resin content before lamination of the plies;
ato be adjusted-the coefficient of thermal expansion of the resin in the ply to be adjusted;
ageneral assembly-the sum of the thermal expansion coefficients of the materials in the PCB;
q is the number of layers to be adjusted.
The performance of the PCB after lamination adjusted by the above calculation is shown in table 4:
TABLE 4
Of course, the warpage problem can also be overcome by increasing the amount of resin in conventional consumable substrates.
In addition, the shrinkage measuring method includes the steps of:
s1, during the inner layer etching of the PCB manufacturing process, making layer number marks on each board layer, specifically, as shown in fig. 4, making layer number marks in the X direction and the Y direction of the board layer, so that the layer number marks can be conveniently observed on any side; as shown in fig. 5, the layer number marks when the respective ply layers are laminated can be arranged in a straight line;
s2, recording the layer number identification position on the plate layer, and recording as a first identification position;
s3, after the board layers are laminated, recording the layer number identification position on the laminated board layer, and recording the layer number identification position as a second identification position;
and S4, calculating the difference between the first mark position and the second mark position of each layer number mark to obtain the shrinkage.
In this embodiment, the layer number is identified as a positioning round hole. The positioning circular hole is convenient for the rapid manufacture of the inner layer during etching.
In this embodiment, the substrate during lamination is irradiated with X-rays, thereby obtaining the layer number identification position.
The relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present application unless specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description. Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
In the description of the present application, it is to be understood that the orientation or positional relationship indicated by the directional terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal" and "top, bottom", etc., are generally based on the orientation or positional relationship shown in the drawings, and are used for convenience of description and simplicity of description only, and in the case of not making a reverse description, these directional terms do not indicate and imply that the device or element being referred to must have a particular orientation or be constructed and operated in a particular orientation, and therefore, should not be considered as limiting the scope of the present application; the terms "inner and outer" refer to the inner and outer relative to the profile of the respective component itself.
Spatially relative terms, such as "above … …," "above … …," "above … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary term "above … …" can include both an orientation of "above … …" and "below … …". The device may be otherwise variously oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, and therefore, the scope of protection of the present application is not to be construed as being limited.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A warpage control method of a PCB is characterized in that: the PCB comprises board layers with different resin contents, when the PCB is warped and is unbalanced in shrinkage, the shrinkage is balanced by adjusting the resin content of the board layers, the shrinkage is the variation distance between the PCB end before lamination and the PCB end after lamination, and the warped warpage is the warping height in the supply direction.
2. The warpage-controlling method for a PCB as claimed in claim 1, wherein: the sheet layer includes a substrate and an adhesive layer, and the amount of shrinkage is balanced by adjusting resin contents of the substrate and the adhesive layer.
3. The warpage-controlling method for a PCB as claimed in claim 2, wherein: the substrate comprises a low-loss material substrate and a conventional loss material substrate, and when the shrinkage of the substrate for warping is unbalanced, the shrinkage is balanced by reducing the resin content of the low-loss material substrate or increasing the resin content of the conventional loss material substrate;
when the substrate exhibits shrinkage imbalance for warpage, the shrinkage is balanced by increasing the resin content of the low loss material substrate or by decreasing the resin content of the conventional loss material substrate.
4. A warpage control method for a PCB as claimed in any one of claims 1 to 3, wherein: the calculation formula of the resin adjustment amount of each ply to be adjusted is as follows:
ΔM＝(ΔL/Lis provided with)*MBefore pressing*(aTo be adjusted/aGeneral assembly)/Q
Wherein, Δ M — the resin adjustment amount of the ply to be adjusted;
delta L is the shrinkage between the laminated layers before and after lamination to be adjusted;
Lis provided withThe set length of the laminated board layer is adjusted;
Mbefore pressing-adjusting the resin content before lamination of the plies;
ato be adjusted-the coefficient of thermal expansion of the resin in the ply to be adjusted;
ageneral assembly-the sum of the thermal expansion coefficients of the materials in the PCB;
q is the number of layers to be adjusted.
5. The warpage-controlling method for a PCB as claimed in claim 1, wherein: the shrinkage measuring method comprises the following steps:
s1, manufacturing layer number marks on each plate layer, wherein the layer number marks can be arranged in a straight line when the plate layers are stacked;
s2, recording the layer number identification position on the plate layer, and recording as a first identification position;
s3, after the board layers are laminated, recording the layer number identification position on the laminated board layer, and recording the layer number identification position as a second identification position;
and S4, calculating the difference between the first mark position and the second mark position of each layer number mark to obtain the shrinkage.
6. The warpage-controlling method for PCB as claimed in claim 5, wherein: the layer number is identified as a locating circular hole.
7. The warpage-controlling method for PCB as claimed in claim 5, wherein: the substrate is irradiated with X-ray during lamination to obtain the layer number mark position.
8. A warpage control method for a PCB as claimed in any one of claims 1 to 7, wherein: the substrate is composed of resin and glass fiber cloth, and the glass fiber cloth is embedded in the resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111679654.8A CN114340171A (en) | 2021-12-31 | 2021-12-31 | Warpage control method of PCB |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111679654.8A CN114340171A (en) | 2021-12-31 | 2021-12-31 | Warpage control method of PCB |
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| CN114340171A true CN114340171A (en) | 2022-04-12 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117279225A (en) * | 2023-11-22 | 2023-12-22 | 深圳市鑫达辉软性电路科技有限公司 | FPC suitable for intelligent wearing and quick pressing process thereof |
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2021
- 2021-12-31 CN CN202111679654.8A patent/CN114340171A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117279225A (en) * | 2023-11-22 | 2023-12-22 | 深圳市鑫达辉软性电路科技有限公司 | FPC suitable for intelligent wearing and quick pressing process thereof |
| CN117279225B (en) * | 2023-11-22 | 2024-01-26 | 深圳市鑫达辉软性电路科技有限公司 | FPC suitable for intelligent wearing and quick pressing process thereof |
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