CN114334982A

CN114334982A - Memory device

Info

Publication number: CN114334982A
Application number: CN202111653437.1A
Authority: CN
Inventors: 陈肯利; 陈琮文
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2020-11-12
Filing date: 2020-11-12
Publication date: 2022-04-12
Also published as: CN112382632A; CN112382632B

Abstract

The invention provides a memory. The bit line and the insulating line are used for defining a node contact window, the contact plugs filled in the node contact window are enabled to protrude out of the node contact window upwards, the adjacent contact plugs are further spaced by utilizing the spacing structure, and the first gap is formed in the spacing structure, so that the dielectric constant of a dielectric material between the adjacent contact plugs is favorably reduced, and the parasitic effect of the device is effectively improved.

Description

Memory device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a memory.

Background

With the development of semiconductor technology, the density of semiconductor devices in an integrated circuit increases, and the spacing between adjacent semiconductor devices also decreases, so that the parasitic effect generated between adjacent conductive portions is not negligible.

Specifically, for a Dynamic Random Access Memory (DRAM), the DRAM generally includes a Memory cell array including a plurality of Memory cells arranged in an array, and the DRAM further includes a plurality of bit lines, each bit line is electrically connected to a corresponding Memory cell, and the DRAM further includes a storage capacitor for storing charges representing stored information, and the Memory cells may be electrically connected to the storage capacitor through a contact plug, so as to implement a storage function of each Memory cell. As described above, as the size of semiconductor devices is continuously reduced, the density of semiconductor devices is increased, and accordingly, larger parasitic effects may exist between adjacent bit lines, between adjacent contact plugs, and the like, which may affect the performance of the device.

Disclosure of Invention

The invention aims to provide a memory to solve the problem of large parasitic effect in the existing memory.

To solve the above technical problem, the present invention provides a memory, including:

a substrate;

a plurality of bit lines and a plurality of insulating lines formed on the substrate, and the bit lines and the insulating lines intersect to define a plurality of node contact windows;

the contact plugs are filled in the node contact windows, the tops of the contact plugs also protrude upwards out of the node contact windows, and grooves are defined between the protruding tops of the adjacent contact plugs;

and a spacer structure filling the groove to space adjacent contact plugs, wherein the spacer structure covers at least the sidewall and the bottom of the groove, and a first void is further formed in the spacer structure at a corner where the sidewall and the bottom meet.

Optionally, the spacer structure includes a first isolation layer and a second isolation layer, the first isolation layer covers at least a sidewall and a bottom of the groove, and the first void is further formed in the first isolation layer at a corner where the sidewall and the bottom meet, and the second isolation layer is formed on the first isolation layer and fills the groove.

Optionally, a second gap is formed in the second isolation layer.

Optionally, the first void is also in direct contact with the contact plug.

Optionally, the bit line includes a bit line conductive part, a bit line shielding layer covering a top surface of the bit line conductive part, and a bit line sidewall covering a sidewall of the bit line conductive part; the bit line side wall comprises a first side wall, a second side wall and a third gap clamped between the first side wall and the second side wall.

Optionally, the third gap in the bit line sidewall on the same sidewall extends continuously along the extending direction of the bit line.

Optionally, the opening of the third gap directly below the spacer structure is covered by the first isolation layer.

Optionally, the top of the contact plug protrusion also extends laterally onto the top surface of the bit line and/or the insulated line.

Optionally, the convex top of the contact plug is translated relative to the bottom portion of the contact plug onto the top surface of the bit line and/or the insulated line; wherein the top portion is extended in size in translation relative to the bottom portion, and is retracted in size in translation relative to the bottom portion.

Optionally, the groove between the protruded tops of the adjacent contact plugs further extends into the bit line and the insulated line directly below, so that the bottom of the spacer structure extends into the bit line and the insulated line.

Optionally, the memory further includes a storage capacitor, and a lower electrode of the storage capacitor is electrically connected to a top of the contact plug.

In the memory provided by the invention, the bit line and the insulating line are used for defining the node contact window, and the contact plug filled in the node contact window also protrudes upwards from the node contact window, so that the contact area of the top surface of the contact plug is increased. And the adjacent node contact plugs are further spaced by utilizing a spacing structure, and a first gap is formed in the spacing structure, so that the dielectric constant of a dielectric material between the adjacent contact plugs can be reduced, and the parasitic effect of the device is effectively improved.

Drawings

FIG. 1 is a top view of a memory cell according to an embodiment of the present invention, mainly illustrating bit lines and insulated lines;

FIG. 2 is a top view of a memory device according to an embodiment of the present invention, mainly illustrating a contact plug;

FIG. 3 is a top view of a memory device illustrating contact plugs and spacer structures in accordance with an embodiment of the present invention;

FIG. 4 is a schematic cross-sectional view of the memory shown in FIG. 3 in the directions I-I 'and II-II' according to one embodiment of the present invention;

FIG. 5 is an enlarged partial view of the cross-sectional view of FIG. 4;

FIG. 6 is a cross-sectional view of a lower electrode of a storage capacitor of an embodiment of the invention;

FIG. 7 is a flow chart illustrating a method for forming a memory according to an embodiment of the invention;

fig. 8a to 8d are schematic structural diagrams illustrating a method for forming a memory device according to an embodiment of the invention during a manufacturing process thereof.

Wherein the reference numbers are as follows:

100-a substrate;

101-a first source/drain region;

102-second source/drain regions;

110-trench isolation structures;

120-word line;

130-word line shield layer;

200-bit line;

210-a bit line conductive portion;

220-bit line masking layer;

230-bit line side walls;

231-first side wall;

232-second side wall;

233-sacrificial interlayer;

300-insulated wire;

400 a-node contact;

400-contact plug;

410-bottom layer contact;

420-a first intermediate conductive layer;

430-a second intermediate conductive layer;

440-top layer contact;

440 a-a filling section;

440 b-a projection;

500-a spacer structure;

500 a-grooves;

510-a first isolation layer;

520-a second isolation layer;

600-a lower electrode;

g1 — first void;

g2 — second void;

g3-third void.

Detailed Description

The core idea of the invention is to provide a memory, which comprises a substrate, and a plurality of bit lines and a plurality of insulating lines formed on the substrate. The bit lines and the insulating lines intersect to define a plurality of node contact windows on the substrate, and contact plugs are filled in the node contact windows. Furthermore, a spacing structure is formed between the tops of the adjacent contact plugs, and a gap is formed in the spacing structure, so that the dielectric constant of the spacing structure is favorably reduced, and the parasitic effect between the adjacent contact plugs is further improved.

The memory and the forming method thereof according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Fig. 1 is a top view mainly illustrating bit lines and insulated lines of a memory according to an embodiment of the present invention, fig. 2 is a top view mainly illustrating contact plugs of a memory according to an embodiment of the present invention, fig. 3 is a top view mainly illustrating contact plugs and spacer structures of a memory according to an embodiment of the present invention, and fig. 4 is a cross-sectional view of the memory according to an embodiment of the present invention shown in fig. 3 in directions I-I 'and II-II'.

As shown in fig. 1 and 4, a plurality of active regions AA are formed in the substrate 100. A first source/drain region 101 and a second source/drain region 102 are formed in the plurality of active regions AA, for example, to constitute a memory transistor. Adjacent active areas AA may be separated from each other by a trench isolation structure 110, wherein the trench isolation structure 110 specifically includes an insulating material filled in an isolation trench, and the insulating material includes, for example, silicon oxide and/or silicon nitride.

Further, a plurality of word lines 120 are formed in the substrate 100, the word lines 120 extend along a second direction (X direction) and intersect with the corresponding active regions AA, and a portion of the word lines 120 intersecting with the active regions AA is located between the first source/drain region 101 and the second source/drain region 102, so as to form a gate structure of the memory transistor.

Referring specifically to fig. 4, the word line 120 is formed in a word line trench in the substrate 100, and the top position of the word line 120 is not higher than the top position of the word line trench. And a word line shielding layer 130 is further filled in the space above the word line groove and the word line 120, and the word line shielding layer 130 covers the word line 120.

With continued reference to fig. 1 and 4, a plurality of bit lines 200 in the memory are formed on the substrate 100. The bit lines 200 extend along a first direction (Y direction) and spatially intersect the corresponding active regions AA, and the portions of the bit lines 200 intersecting the active regions AA constitute, for example, bit line contacts electrically connected to the active regions AA. In this embodiment, the bit line contact is electrically connected to the first source/drain region 101 of the active area AA.

And bit line contacts of the bit lines 200, which intersect the active regions AA, are further embedded in the substrate 100. That is, the bottom of the bit line contact is lower than the top surface of the substrate 100. In this way, the bit line contact portion of the bit line 200 can be sufficiently contacted with the first source/drain region 101, and the contact resistance between the bit line 200 and the first source/drain region 101 can be reduced.

Fig. 5 is a partially enlarged view of the cross-sectional view shown in fig. 4, and in conjunction with fig. 4 and fig. 5, the bit line 200 includes a bit line conductive portion 210, a bit line shielding layer 220, and bit line sidewalls 230. The bit line conductive part 210 is formed on the substrate 100 and electrically connected to the corresponding active area AA, the bit line shielding layer 220 covers a top surface of the bit line conductive part 210, and the bit line sidewall 230 covers at least a sidewall of the bit line conductive part 210. That is, the bit line shielding layer 220 and the bit line sidewall spacers 230 are used to electrically isolate the bit line conductive part 210, so as to form the bit line 200 with external insulation.

In this embodiment, the bit line conductive part 210 of the bit line 200 may have a plurality of conductive layers stacked in sequence. For example, the bit line conductive part 210 includes a first conductive layer, a second conductive layer and a third conductive layer stacked in sequence from bottom to top, where the first conductive layer includes, for example, doped polysilicon, the second conductive layer includes, for example, titanium nitride, and the third conductive layer includes, for example, tungsten.

With continued reference to fig. 5, the bit line sidewall spacers 230 may be of a stacked structure. For example, the bit line sidewall spacers 230 include a first sidewall 231 and a second sidewall 232 that are sequentially disposed from inside to outside. In this embodiment, the bit line sidewall spacers 230 further include a third gap G3 sandwiched between the first sidewall 231 and the second sidewall 232.

As shown in fig. 1 and 5, the third gap G3 in the bit line sidewall 230 on the same bit line sidewall extends continuously along the extending direction of the bit line, i.e., the third gap G3 extends continuously between the first sidewall 231 and the second sidewall 232. In this embodiment, the bit line conductive part 210 includes a first conductive layer, a second conductive layer, and a third conductive layer stacked in this order from bottom to top, and a bottom position of the third gap G3 is not lower than a top surface of the first conductive layer, and a top position of the third gap G3 is higher than the third conductive layer.

With continued reference to fig. 1 and 4, the insulating line 300 is formed on the surface of the substrate 100, and the extending direction of the insulating line 300 is different from the extending direction of the bit line 200, so that the insulating line 300 and the bit line 200 can intersect on the top surface of the substrate 100 to define a node contact window 400 a. In this embodiment, the extension direction of the insulating line 300 is the same as the extension direction of the word line WL, and both extend along the second direction (X direction), and the insulating line 300 is formed directly above the word line WL.

Further, the top surfaces of the bit line 200 and the insulating line 300 are flush. For example, when the insulating line 300 is formed in conjunction with a planarization process, the bit line 200 may be utilized as a polish stop layer. In this embodiment, the top surface of the insulating line 300 is flush with the top surface of the bit line shielding layer 220 of the bit line 200.

Referring to fig. 1, in the present embodiment, the insulated wire 300 includes a plurality of insulated wire segments sequentially arranged along the second direction and separated from each other, the insulated wire segments also extend along the extending direction of the insulated wire (i.e., the insulated wire segments also extend along the second direction), and the insulated wire segments are formed between the adjacent bit lines 200, so that both ends of the insulated wire segments are respectively connected to the adjacent bit lines 200, and the node contact windows 400a can be surrounded by the insulated wire segments and the adjacent bit lines 200.

In this embodiment, the bottom of the node contact window 400a further extends into the substrate 100, so that a larger area of the active region AA can be exposed in the node contact window 400a (i.e., at least a portion of the active region AA is exposed in the node contact window). And, by making the bottom of the node contact 400a lower than the top surface of the substrate, it is advantageous to achieve electrical connection between the contact plug 400 filled in the node contact 400a and the active area AA. In this embodiment, the node contact window 400a exposes the second source/drain region 102 in the active region AA.

Referring to fig. 2 and 4 with emphasis, the memory includes a plurality of contact plugs 400, each contact plug 400 is correspondingly formed in one node contact window 400a, so that a plurality of the contact plugs 400 are connected with the second source/drain regions 102 corresponding to the node contact windows 400a in a one-to-one correspondence.

Further, the top of the contact plugs 400 also protrudes upward from the node contact windows, and a groove is defined between the protruding tops of adjacent contact plugs 400. That is, the top surface of the contact plug 400 is higher than the top surfaces of the bit line 200 and the insulating line 300. Furthermore, the protruding top of the contact plug 400 also extends laterally to the top surface of the bit line 200 and/or the insulated line 300, which is beneficial to increase the contact area of the top surface of the contact plug 400. That is, the contact plug 400 includes a lower portion filled in the node contact and an upper portion protruding from the node contact, and the upper portion of the contact plug 400 constitutes a top portion of the contact plug 400 protruding therefrom and defines the groove between the upper portions of the adjacent contact plugs 400.

In this embodiment, it is emphasized that, with reference to fig. 4 and 5, the contact plug 400 includes a bottom contact 410 and a top contact 440, wherein the material of the bottom contact 410 includes, for example, polysilicon, and the material of the top contact 440 includes, for example, tungsten.

Specifically, the bottom contact 410 is filled in the node contact to electrically contact the active area AA, and the top position of the bottom contact 410 is lower than the top position of the node contact; and, the top layer contact 440 is formed above the bottom layer contact 410, and the bottom (i.e., the filling portion 440a) of the top layer contact 440 is filled in the node contact, and the top (i.e., the protrusion 440b) of the top layer contact 440 protrudes out of the node contact and laterally extends onto the top surface of the bit line 200 and/or the insulated line 300.

In an alternative, the top of the protrusion of the contact plug 400 is translated onto the top surface of the bit line 200 and/or the insulated line 300 relative to the bottom portion of the contact plug 400. It is considered that, in the present embodiment, the protruding portion 440b of the top layer contact 440 is partially translated onto the top surface of the bit line 200 and/or the insulated wire 300 with respect to both the filling portion 440a of the top layer contact 440 and the bottom layer contact 410.

With continued reference to fig. 5, in the present embodiment, the dimension D1 extending by the top portion of the contact plug 400 translated with respect to the bottom portion may also be made larger than the dimension D2 retracting by the top portion translated with respect to the bottom portion (D1 > D2).

For example, as shown in fig. 2, the protrusion 440b of the top layer contact 440 translates in the first direction (Y direction) relative to the filling portion 440a such that the protrusion 440b extends over the insulated wire 300, and a dimension D1 of the protrusion 440b extending out at an extending end relative to the filling portion 440a is greater than a retracted dimension D2 of the protrusion 440b at a position facing away from the extending end relative to the filling portion 440 a. And, the protrusion 440b of the top layer contact 440 can also translate along the second direction (X direction) relative to the filling portion 440a, such that the protrusion 440b also extends to cover the bit line 200, and the extension dimension D1 of the protrusion 440b relative to the filling portion 440a at the extension end is greater than the retraction dimension D2 of the protrusion 440b relative to the filling portion 440a at the end facing away from the extension end.

In an optional scheme, the contact plug 400 further includes a first intermediate conductive layer 420 and a second intermediate conductive layer 430 between the bottom layer contact 410 and the top layer contact 440. Wherein the first intermediate conductive layer 420 is formed on the top surface of the bottom layer contact 410, and the first intermediate conductive layer 420 is, for example, a metal silicide layer (for example, the first intermediate conductive layer 420 may be specifically a cobalt metal silicide layer). By providing the metal silicide layer, the contact resistance between the bottom contact 410 and the conductive material above the bottom contact can be effectively reduced. And, the second intermediate conductive layer 430 covers the top surface of the first intermediate conductive layer 420, and the second intermediate conductive layer 430 also covers the sidewalls of the node contact windows higher than the first intermediate conductive layer 420. In this embodiment, the second intermediate conductive layer 430 covers sidewalls of the insulated wire 300 and sidewalls of the bit line 200.

Referring next to fig. 3 and 4, the memory further includes a spacer structure 500, the spacer structure 500 filling a groove defined by the convex tops of the adjacent contact plugs 400 to space the adjacent contact plugs 400 (specifically, the spacer structure 500 is filled between the convex tops of the adjacent contact plugs 400). Wherein the spacer structure 500 covers at least the sidewall and the bottom of the groove, and a first gap G1 is formed at a corner where the sidewall and the bottom meet. In this embodiment, the first gap G1 directly contacts the insulated wire 300 and/or the bit line 200.

It should be appreciated that the recess defined by the raised top of the contact plug 400 is at least partially located above the bit line 200 and the insulated line 300. Specifically, when the top of the contact plug 400 does not laterally extend, the defined recess corresponds to the bit line 200 or the insulated line 300, and the first gap G1 located at the corner of the recess directly contacts the bit line 200 or the insulated line 300, and may also directly contact the contact plug 400; alternatively, when the convex top of the contact plug 400 extends laterally, a portion of the defined recess corresponds to directly above the node contact, and another portion corresponds to directly above the bit line 200 or the insulated line 300, in which case the first gap G1 at the corner of the recess may also directly contact the bit line 200 or the insulated line 300, respectively, and the first gap G1 at the corner of the recess may also directly contact the contact plug 400.

Specifically, the spacer structure 500 includes a first isolation layer 510 and a second isolation layer 520, the first isolation layer 510 covers at least the sidewall and the bottom of the groove, and the first gap G1 is further formed in the first isolation layer 510 at the corner where the sidewall and the bottom meet. And, the second isolation layer 520 is formed on the first isolation layer 510 and fills the groove. In this embodiment, the second isolation layer 520 further has a second gap G2 formed therein, so as to further reduce the dielectric constant of the dielectric material between the adjacent contact plugs 500 and improve the parasitic effect between the adjacent contact plugs 500.

In addition, as described above, the top opening of the third gap G3 in the bitline sidewall 230 of the bitline 200 extends to the bottom of the groove defined by the top of the adjacent contact plug 400, which is at least partially located directly above the bitline 200. In this embodiment, the first isolation layer 510 in the groove covers the third gap G3, i.e., the opening of the third gap G3 directly below the spacer structure 500 is covered by the first isolation layer 510.

With continued reference to fig. 4 and 5, the recess between the protruded tops of the adjacent contact plugs 400 further extends into the bit line 200 and the insulated line 300 directly below, so that the bottom of the spacer structure 500 may further extend into the bit line 200 and the insulated line 300. In this way, electrical isolation between adjacent contact plugs 400 is ensured.

In a further aspect, referring specifically to fig. 6, the memory further includes a storage capacitor, and a bottom electrode 600 of the storage capacitor is electrically connected to the top of the contact plug 400. In this embodiment, the second isolation layer 520 of the spacer structure 500 fills the groove between the adjacent contact plugs 400 and also covers the contact plugs 400, and the lower electrode 600 penetrates through the second isolation layer 520 to be electrically connected to the top surface of the top of the protrusion of the contact plug 400.

Based on the memory as described above, a method of forming the memory will be described in detail below with reference to the accompanying drawings. Fig. 7 is a schematic flow chart of a method for forming a memory according to an embodiment of the invention, and fig. 8a to 8d are schematic structural diagrams of the method for forming a memory according to an embodiment of the invention in a manufacturing process thereof.

First, step S100 is performed, and referring to fig. 8a in particular, a substrate 100 is provided, and a plurality of bit lines 200 and a plurality of insulating lines 300 are formed on the substrate 100, wherein the bit lines 200 and the insulating lines 300 intersect to define a plurality of node contact windows 400 a.

Wherein a plurality of active regions AA are formed in the substrate 100. Specifically, a plurality of trench isolation structures 110 may be formed in the substrate 100 to define a plurality of active regions AA. And, the first and second source/

drain regions

101 and 102 in the active area AA may be formed by an ion implantation process. In this embodiment, each of the second source/drain regions 102 corresponds to one node contact window 400 a.

In a specific embodiment, the bit line 200 may be formed on the substrate 100 first, and then the insulating line 300 may be formed on the substrate 100. Further, the top surface of the bit line 200 and the top surface of the insulating line 300 may be made flush.

Wherein the bit lines 200 continuously extend along the first direction. And, the insulated wire 300 includes a plurality of insulated wire segments sequentially arranged along the second direction, and each insulated wire segment also extends between adjacent bit lines 200 along the second direction to connect with the bit lines 200, so as to surround the node contact 400 a. It is understood that the insulated wires 300 extend discontinuously along the second direction, and bit lines 200 are spaced between adjacent insulated wire segments in the same insulated wire 300.

In this embodiment, the substrate 100 of the second source/drain region 102 may be further etched using the pattern defined by the bit line 200 and the insulating line 300, so that the bottom of the node contact window 400a is further embedded into the substrate 100.

With continued reference to fig. 8a, the bit line 200 includes bit line conductive portions 210, bit line masking layers 220, and bit line sidewalls 230. The bit line shielding layer 220 and the bit line sidewall spacers 230 cover the bit line conductive parts 210 from the top surfaces and sidewalls of the bit line conductive parts 210, respectively, to insulate the bit lines 200 from the outside.

Further, the bit line sidewall spacers 230 include a first sidewall 231 and a second sidewall 232 that sequentially cover the sidewalls of the bit line conductive portion 210. In this embodiment, a sacrificial interlayer 233 is further sandwiched between the first sidewall 231 and the second sidewall 232, and the sacrificial interlayer 233 can be removed in a subsequent process to release the corresponding space.

Next, step S200 is performed, and referring to fig. 8b in particular, a contact plug 400 is formed, wherein the contact plug 400 fills the node contact 400a, and the top of the contact plug 400 protrudes upward from the node contact 400a, and a groove 500a is defined between the protruding tops of adjacent contact plugs 400.

Specifically, the method for forming the contact plug 400 may include the following steps.

First, the bottom contact 410 is filled in the node contact 400a to electrically connect with the active area AA. Wherein a top surface of the bottom layer contact 410 is lower than top surfaces of the bit line 200 and the insulating line 300, and a material of the bottom layer contact 410 includes, for example, polysilicon.

In a second step, a first intermediate conductive layer 420 is formed on the top surface of the bottom contact 410. The first intermediate conductive layer 420 is, for example, a metal silicide layer. Specifically, the method for forming the first intermediate conductive layer 420 includes, for example: first, a metal layer is deposited on the substrate 100, the metal layer covering the top surface of the bottom contact 410 and covering the bit line 200 and the insulated line 300; next, performing a thermal annealing process to react the metal in the metal layer and the polysilicon in the bottom contact 410, thereby forming the metal silicide layer on the top surface of the bottom contact 410 in a self-aligned manner; and then removing the unreacted part in the metal layer.

A third step of forming a second intermediate conductive layer 430, wherein the second intermediate conductive layer 430 covers the first intermediate conductive layer 420, the bit line 200 and the insulated line 300.

A fourth step of forming a conductive material layer filling the node contact windows and further covering the top surfaces of the bit lines 200 and the insulating lines 300. The conductive material layer may be a planarized film layer, so that the top surface of the conductive material layer is substantially flat.

In the fifth step, the conductive material layer is patterned to form a top layer contact 440.

Specifically, a patterning process may be performed using a mask layer, including: a mask layer is formed on the conductive material layer, wherein the mask layer has a plurality of mask patterns corresponding to the contact plugs (in the embodiment, the mask patterns correspond to the top layer contacts), and the mask patterns cover at least part of the node contact windows and also extend to cover adjacent bit lines and/or insulating lines. In this embodiment, the mask pattern is horizontally offset with respect to the node contact 400a such that a portion directly under the mask pattern is covered between the node contact and the bit line 200 and/or a portion directly under the mask pattern is covered between the node contact and the insulated line 300. In this manner, when the conductive material layer is patterned by using the mask layer, the formed top layer contact 440 is partially translated onto the bit line 200 and/or the insulated wire 300.

Further, the conductive material layer is etched by using the mask layer, and the etching stops on the bit line 200 and the insulating line 300, so that the top layer contacts 440 in different node contact windows are mutually disconnected. That is, it is equivalent to that the bottom position of the groove 500a between the tops of the adjacent contact plugs 400 stops on the bit line 200 and the insulated line 300.

In addition, referring to fig. 8b, the insulating line 300 and the bit line 200 (specifically, the bit line shielding layer) exposed in the recess 500a may be further etched downward, so as to prevent the conductive material from remaining and ensure that the adjacent contact plugs 400 are disconnected from each other; on the other hand, the top of the sacrificial interlayer 233 in the bit line sidewall spacers 230 may also be exposed.

In a further embodiment, referring to fig. 8c specifically, the sacrificial interlayer in the bit line sidewall 230 may be removed through the groove 500a, so that a third gap G3 may be formed between the first sidewall 231 and the second sidewall 232, and a top opening of the third gap G3 is correspondingly communicated with the groove 500a above the third gap G3.

Next, step S300 is performed, and referring to fig. 8d in particular, a spacer structure 500 is formed in the groove 500a to space the adjacent contact plugs 400. Wherein the spacer structure 500 covers at least the sidewall and the bottom of the groove, and a first gap G1 is further formed in the spacer structure at the corner where the sidewall and the bottom meet, and the first gap G1 directly contacts the bit line 200 and/or the insulated wire 300.

Specifically, the method for forming the spacer structure may include: first, a first isolation layer 510 is formed, the first isolation layer 510 covers the bottom and the sidewalls of the groove 500a, and a first gap G1 is further formed in the first isolation layer 510 at the corner where the sidewalls and the bottom meet. The first isolation layer 510 may be formed by a deposition process with poor coverage, so as to form a first gap G1 in the first isolation layer 510. In this embodiment, the first isolation layer 510 further covers the top opening of the third gap G3 in the bit line sidewall. Then, a second isolation layer 520 is formed in the groove 520, and in this embodiment, a second gap G2 is further formed in the second isolation layer 520.

In a further aspect, the method for forming the memory further includes: a storage capacitor is formed. The method specifically comprises the following steps: a lower electrode of the storage capacitor is formed, and the bottom of the lower electrode is electrically connected to the top surface of the contact plug 400.

It should be noted that, although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.

It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.

It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims

1. A memory, comprising:

a substrate;

the bit lines and the insulating lines are formed on the substrate and intersect to define a plurality of node contact windows, and the bit lines comprise bit line side walls formed on the side walls of the bit lines;

the contact plugs are filled in the node contact windows, the tops of the contact plugs also protrude upwards out of the node contact windows, and grooves are defined between the protruding tops of the adjacent contact plugs; and the number of the first and second groups,

2. The memory of claim 1, wherein the spacer structure comprises a first spacer layer and a second spacer layer, the first spacer layer covering at least a sidewall and a bottom of the recess, and the first void further formed in the first spacer layer at a corner where the sidewall and the bottom meet, and the second spacer layer formed on the first spacer layer and filling the recess.

3. The memory of claim 2, wherein the second isolation layer has a second void formed therein.

4. The memory of claim 1, wherein the first void is also in direct contact with the contact plug.

5. The memory of claim 1, wherein the bit line comprises a bit line conductive portion, a bit line shield layer covering a top surface of the bit line conductive portion, and bit line sidewalls covering sidewalls of the bit line conductive portion;

the bit line side wall comprises a first side wall, a second side wall and a third gap clamped between the first side wall and the second side wall.

6. The memory of claim 5, wherein the third voids in the bit line sidewall spacers on the same sidewall extend continuously along the extension direction of the bit line.

7. The memory of claim 5, wherein an opening in the third void directly below the spacing structure is covered by the spacing structure.

8. The memory of claim 1, wherein the top of the contact plug protrusion also extends laterally onto a top surface of the bit line and/or the insulated line.

9. The memory of claim 8, wherein a top portion of the contact plug protrusion translates relative to a bottom portion of the contact plug onto a top surface of the bit line and/or the insulated line;

wherein the top portion is extended in size in translation relative to the bottom portion, and is retracted in size in translation relative to the bottom portion.

10. The memory of claim 1, wherein the recess between the convex tops of adjacent contact plugs further extends into the bit line and the insulated line directly below, such that the bottom of the spacer structure extends into the bit line and the insulated line.

11. The memory of claim 1, further comprising a storage capacitor, and wherein a lower electrode of the storage capacitor is electrically connected to a top of the contact plug.