CN114333950A - Storage device - Google Patents

Abstract

The invention provides a storage device, which comprises a storage unit array and a voltage generating circuit. The voltage generating circuit is electrically connected with the memory cell array and comprises an active voltage circuit and a sensing circuit. The active voltage circuit is used for outputting an operating voltage to the memory cell array when the memory device is in an active mode. The sensing circuit is used for sensing the operating voltage when the storage device is in a standby mode and starting the active voltage circuit to pull up the operating voltage shortly after the operating voltage drops to be lower than a critical value.

Description

Storage device

Technical Field

The present invention relates to electronic circuits, and more particularly, to a memory device.

Background

As electronic technology has evolved, nonvolatile storage, which can provide long-term and large-volume data storage functions, has become a main data storage medium, and flash memory is one of the mainstream storage devices. In order to improve the energy efficiency of the electronic device, the flash memory has an active mode (active mode) when the electronic device is to access data, and a standby mode (standby mode) with low power consumption.

However, in order to quickly switch the flash memory from the standby mode back to the active mode, the voltage generator circuit still needs to operate to provide a high voltage to the word line coupled to the memory array in the standby mode.

In order to save power, a flash memory circuit is usually configured with two voltage generation circuits for an active mode and a standby mode, wherein the voltage generation circuit for the standby mode has lower power consumption. Thus, although the power consumption of the flash memory can be reduced, the additional voltage generation circuit increases the circuit area of the memory and the electronic components required to be used.

Disclosure of Invention

Accordingly, the present invention provides a memory device having advantages of reduced circuit area, simplified circuit components and reduced standby current.

The embodiment of the invention provides a storage device, which comprises a storage array and a voltage generation circuit. The voltage generating circuit is electrically connected with the memory cell array and comprises an active voltage circuit and a sensing circuit. The active voltage circuit is used for outputting an operating voltage to the memory cell array when the memory device is in an active mode. The sensing circuit is used for sensing the operating voltage when the storage device is in a standby mode and starting the active voltage circuit to pull up the operating voltage shortly after the operating voltage drops to be lower than a critical value.

Based on the above, the memory device provided by the embodiment of the invention has the sensing circuit to detect the change of the operating voltage in the standby mode, and the sensing circuit briefly activates the active voltage circuit to pull up the operating voltage whenever the operating voltage drops below the threshold value. Therefore, the circuit of the memory device can be simplified, and the effect of reducing the circuit area is also achieved.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the invention;

FIG. 2 is a circuit diagram of a voltage generation circuit according to an embodiment of the present invention;

fig. 3 is a signal waveform diagram of a voltage generation circuit according to an embodiment of the invention.

Detailed Description

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the invention. Referring to fig. 1, the memory device 100 may be a NOR flash memory, but the invention is not limited thereto. The memory device 100 includes at least a memory cell array 102, a controller 104, and a voltage generation circuit 106. The controller 104 is electrically connected to the memory cell array 102 and the voltage generating circuit 106. The controller 104 may control the execution of an active mode or a standby mode for the memory cell array 102. The voltage generation circuit 106 correspondingly provides an operating voltage to the word lines of the memory cell array 102 according to the active mode or the standby mode. The memory device 100 may further include a word line decoding circuit, a bit line decoding circuit, a driving circuit, a sense amplifying circuit, etc. which are not shown in fig. 1, and those skilled in the art should understand the configuration relationship and implementation of the above components.

Fig. 2 is a circuit diagram of a voltage generation circuit according to an embodiment of the invention. Referring to fig. 2, the circuit structure of fig. 2 can be used to illustrate the voltage generating circuit 106. The voltage generation circuit 106 includes an active voltage circuit 110 and a sensing circuit 120. The active voltage circuit 110 is used for outputting an operation voltage RV to the memory cell array 102 when the memory device 100 is in an active mode. The operation voltage RV is exemplified herein by a read voltage. When the memory device 100 is in the standby mode, the active voltage circuit 110 outputs the operating voltage RV as well, but the difference is that the active voltage circuit 110 is continuously in an enable state in the active mode to stably output the operating voltage RV, but the active voltage circuit 110 is only intermittently in the enable state in the standby mode, so that power can be saved. In the standby mode, the sensing circuit 120 senses the operation voltage RV and briefly activates the active voltage circuit 110 to pull up the operation voltage RV after the operation voltage RV drops below a threshold.

The active voltage circuit 110 includes a charge pump 112 and a voltage regulator 114, wherein the charge pump 112 is electrically connected to the voltage regulator 114. The charge pump 112 outputs an operating voltage RV, and the voltage regulating circuit 114 is used for maintaining the voltage value of the operating voltage RV.

The voltage regulation circuit 114 of fig. 2 includes a high voltage switch HVSW, a transistor T, a voltage divider circuit 116 including a plurality of resistors and at least one transistor, a bandgap reference circuit BGR, and a voltage comparison amplifier 118. The high voltage switch HVSW is coupled between the output terminal of the active voltage circuit 110 and the control terminal of the transistor T. The transistor T and the voltage divider circuit 116 are connected in series between the output terminal of the active voltage circuit 110 and ground (ground). The voltage comparison amplifier 118 receives the output signal of the bandgap reference circuit BGR and the divided voltage of the voltage dividing circuit 116 to output the boost enable signal EN _ PUMP. The charge PUMP 112 boosts the operation voltage RV according to the boost enable signal EN _ PUMP.

It is noted that the circuit architecture of the voltage regulating circuit 114 in fig. 2 is only an example, and the present invention is not limited to the implementation of the voltage regulating circuit 114.

The sensing circuit 120 includes a capacitor C, a sensing transistor DT, a start transistor AT, and a switching transistor ST. One end of the capacitor C is coupled to the output end of the active voltage circuit 110 to receive the operating voltage RV, and the other end is coupled to a sensing node D. The sensing transistor DT has one terminal receiving a reference voltage VDD through a transistor P1, another terminal coupled to the reaction node a, and a control terminal coupled to the sensing node D. In other words, the voltage at one end of the capacitor C is the operating voltage RV, and the other end is coupled to the control end of the sensing transistor DT, so that the voltage at the sensing node D varies with the operating voltage RV during the sensing period, and when the operating voltage RV is lower than the threshold value, the sensing transistor is turned on and the sensing period ends.

The enable transistor AT has one terminal receiving the reference voltage VDD through the transistor P2, another terminal coupled to the reaction node a, and a control terminal coupled to the sensing node D. The switch transistor ST has one terminal coupled to the sensing node D and the other terminal coupled to the reaction node A, and a control terminal coupled to the control terminal of the transistor P2 for receiving the control signal PG 0. In the present embodiment, the sensing transistor DT, the start transistor AT, the switch transistor ST, the transistor P1, and the transistor P2 are PMOS transistors, but are not limited thereto.

The sensing circuit 120 enters the start-up period after the sensing period ends. During the start-up period, the switch transistor ST is turned on to correspondingly turn on the start-up transistor AT and turn off (cut off) the sensing transistor DT, and the active voltage circuit 110 is also turned on to pull the operation voltage RV back to the target voltage value.

The sensing circuit 120 further includes a discharge switch 122 and a pull-down circuit 124. One end of the discharge switch 122 is coupled to the reaction node a, and the other end is grounded, wherein the discharge switch 122 is turned on during the start-up period to output the leakage current and is turned off during the sensing period. One end of the pull-down circuit 124 is coupled to the reaction node a, and the other end is grounded, wherein the pull-down circuit 124 is turned off during the start-up period and turned on during the sensing period to pull down the voltage of the reaction node a.

Specifically, in the present embodiment, the discharge switch 122 includes a transistor NB and a transistor N0. The transistors NB and N0 are connected in series between the reaction node a and ground, wherein the control terminals of the transistors NB and N0 receive the control signal NBIAS and NG0, respectively. The skilled person can determine the current magnitude of the leakage current by selecting an appropriate transistor NB. The pull-down circuit 124 of the present embodiment is implemented by a single transistor. The control terminal of the pull-down circuit 124 receives the control signal NG 1. The transistors NB, N0 and the pull-down circuit 124 are all NMOS transistors, but not limited thereto.

Fig. 3 is a signal waveform diagram of a voltage generation circuit according to an embodiment of the invention. The signal waveform diagram of fig. 3 is applied to the embodiments of fig. 1 and 2, and the following description will be made with reference to fig. 3 in conjunction with fig. 2.

Between time point t1 and time point t2 is the sensing period DETECT. At a time point t1, the operating voltage RV has been boosted to the target voltage value V0 by the charge pump 112. In the sensing period DETECT, the active voltage circuit 110 is not activated, i.e., is in a disabled state, and thus the operating voltage RV gradually starts to decrease. The sensing circuit 120 monitors the change of the operating voltage RV.

In addition, the switch transistor ST, the start transistor AT, the transistor P2, the discharge switch 122, and the pull-down circuit 124 are in the off state during the sensing period DETECT. The capacitor C couples the operating voltage RV to the sensing node D, and thus the voltage of the sensing node D varies with the operating voltage RV. At the beginning (time point t1), the sense transistor DT is in the off state. The absolute value of the threshold voltage (threshold voltage) of the sense transistor DT is denoted by Vth 1. At time t2, the voltage at the sensing node D drops below VDD-Vth1, so the sensing transistor DT is turned on, which also indicates that the operating voltage RV is below a threshold value at this moment.

Between time t2 and time t3, the voltage at the reaction node A is pulled up by the reference voltage VDD through the sensing transistor DT and the transistor P1. The switching transistor ST, the start-up transistor AT, the transistor P2, the discharge switch 122, and the pull-down circuit 124 are all maintained in the off state AT this time.

Between time point t3 and time point t4 is the activation period ACT. In the active period ACT, the control signal PG0, the control signal NBIAS, and the control signal NG0 are all switched to the enabled state in response to the voltage rise at the reaction node a, and the switching transistor ST, the transistor P2, and the discharge switch 122 are turned on. The pull-down circuit 124 remains off. Since the switching transistor ST is turned on, the reaction node a is in common with the sensing node D, and the start-up transistor AT and the sensing transistor DT are connected in a diode connection form. The absolute value of the threshold voltage of the start-up transistor AT is denoted by Vth 2. Specifically, the absolute value Vth1 of the threshold voltage of the sense transistor DT of the present embodiment is larger than the absolute value Vth2 of the threshold voltage of the start transistor AT, so the start transistor AT is turned on, and the sense transistor DT is not turned on. The voltages of the reaction node A and the sensing node D are maintained AT the enabling voltage VDD-Vth2 by the enabling transistor AT. Meanwhile, the discharge switch 122 allows the reaction node a to output a leakage current to the ground.

In the active period ACT, the reaction node a outputs an enable signal EN through the inverter INV. The enable signal EN is used to enable the active voltage circuit 110, such as the charge pump 112 and the voltage divider circuit 116, the voltage comparator amplifier 118 and the bandgap reference circuit BGR in the voltage regulator circuit 114. The voltage regulation circuit 114 is enabled to perform a voltage regulation function. The voltage comparison amplifier 118 outputs the boost enable signal EN _ PUMP to cause the charge PUMP 112 to pull the operating voltage RV back to the target voltage value V0. In other words, by activating the transistor AT, the voltages of the reaction node A and the sensing node D are changed to the activation voltage VDD-Vth2 to activate the active voltage circuit 110.

In short, the operation voltage RV decays from the target voltage V0, and the active voltage circuit 110 increases the operation voltage RV back to the target voltage V0 when the operation voltage RV is lower than the threshold. The magnitude of the ripple (ripple) of the operating voltage RV is determined by the difference Δ Vth between the threshold voltages of the sense transistor DT and the enable transistor AT, where Δ Vth is Vth1-Vth 2. The critical value is V0- Δ Vth.

The sensing period DETECT is returned again between the time point t4 and the time point t 5. At the beginning of the sensing period DETECT (time t4), the discharging switch 122 is turned off and the pull-down circuit 124 is turned on during the initial period In. Fig. 3 shows an enable period of the control signal NG1 as an initial period In. The initial period In is shorter than the sensing period DETECT. The discharge switch 122 pulls down the voltage of the reaction node a to ground during the initial period In to initialize the voltage of the reaction node a. After the initial period In, the discharge switch 122 is turned off again.

When the operating voltage RV rises to be substantially equal to the target voltage value V0 (time point t4), the control signal PG0, the control signal NBIAS, and the control signal NG0 are switched back to the disabled state, so that the discharge switch 122 is turned off, and the switching transistor ST, the transistor P2, and the discharge switch 122 are also switched to the off state. The above embodiments of detecting and activating during the sensing period ACT are repeated. Whether to re-enter the active period ACT to activate the active voltage circuit 110 is determined by whether the sensing transistor DT is turned on or not.

Specifically, the active period ACT is shorter than the sensing period DETECT. In addition, the on-time of the sensing transistor DT is also very short, just as short as the sensing period DETECT.

In the standby mode, since the sensing circuit 120 only briefly activates the active voltage circuit 110, and the active voltage circuit 110 is not activated for most of the time, the whole circuit does not consume much power, and the power saving requirement can be achieved. In addition, the sensing circuit 120 does not need to have a circuit component with high power consumption, such as a voltage comparison amplifier or a charge pump, and also does not need to have a voltage division circuit composed of a plurality of resistors, so that the advantages of reducing standby current and reducing circuit area are achieved.

In summary, the embodiments of the present invention provide a memory device. The storage device does not need to configure a low-power-consumption voltage generation circuit aiming at the standby mode, but can achieve the effect of outputting the operating voltage with low power consumption by intermittently starting the voltage generation circuit of the active mode through the sensing circuit, so that the original voltage generation circuit can also be applied to the standby mode. The memory device of the embodiment of the invention has the advantages of reduced circuit area, simplified circuit components and reduced standby current.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (10)

1. A memory device, comprising:

an array of memory cells; and

a voltage generating circuit electrically connected to the memory cell array and including:

an active voltage circuit for outputting an operating voltage to the memory cell array when the memory device is in an active mode; and

a sensing circuit to sense the operating voltage when the memory device is in a standby mode and to briefly activate the active voltage circuit to pull up the operating voltage after the operating voltage drops below a threshold value.

2. The memory device of claim 1, wherein the sensing circuit comprises:

a capacitor having one end coupled to the output end of the active voltage circuit and the other end coupled to a sensing node; and

a sensing transistor having one end for receiving a reference voltage, the other end coupled to the reaction node, a control end coupled to the sensing node,

wherein, during a sensing period, a voltage on the sensing node varies with the operating voltage, and the sensing transistor is turned on when the operating voltage is lower than the critical value.

3. The memory device of claim 2, wherein the sensing circuit comprises:

a start-up transistor having one end for receiving the reference voltage, the other end coupled to the reaction node, and a control end coupled to the sensing node;

a switch transistor having one end coupled to the sensing node and the other end coupled to the reaction node,

wherein, during a start-up period, the switching transistor is turned on to correspondingly turn on the start-up transistor and turn off the sensing transistor, and the active voltage circuit is turned on to pull the operating voltage back to a target voltage value.

4. The storage device of claim 3, wherein an absolute value of a threshold voltage of the sense transistor is greater than an absolute value of a threshold voltage of the enable transistor.

5. The memory device of claim 3, wherein during the start-up period, the voltages of the reaction node and the sense node are changed to a start-up voltage by the start-up transistor to start up the active voltage circuit, and during the sense period, the active voltage circuit is not started up.

6. The memory device of claim 3, wherein the sensing circuit further comprises:

a discharge switch having one end coupled to the reaction node and the other end grounded, wherein the discharge switch is turned on during the start-up period to output a leakage current and turned off during the sensing period; and

a pull-down circuit having one end coupled to the reaction node and the other end grounded, wherein the pull-down circuit is turned off during the start-up period and turned on during the sensing period to pull down a voltage of the reaction node.

7. The memory device of claim 6, wherein at the beginning of the sensing period, the discharge switch is turned off and the pull-down circuit is turned on for an initial period, wherein the initial period is shorter than the sensing period.

8. The storage device of claim 3, wherein the startup period is shorter than the sensing period.

9. The memory device of claim 3, wherein a magnitude of a ripple of the operating voltage is determined by a difference in threshold voltages of the sense transistor and the enable transistor when the memory device is in the standby mode.

10. The memory device of claim 9, wherein the threshold value is the target voltage value minus the difference value.

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