JP2003297091A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which current consumption of a read circuit incorporating a boosting power source circuit is suppressed more than conventional one. <P>SOLUTION: This semiconductor memory device 200 is provided with a sense amplifier 9 having a function reading information stored in a memory cell being storage elements of a memory array 7, a boosting power source circuit 201 having a function boosting voltage supplied from the outside and supplying it to the memory cell to read information, a control circuit 105 for making the boosting power source circuit 201 start boosting the voltage after the start of a read cycle, and a Vg voltage detecting circuit 11 detecting that voltage boosted by the boosting power source circuit 201 reaches the prescribed value required for reading the information stored in the memory cell and starting read operation of the sense amplifier 9 when the relevant phenomenon is detected. Further, the control circuit 105 stops boosting by the boosting power source circuit 201 after the prescribed time required for read operation elapses from the time when the detection is performed by the Vg voltage detecting circuit 11. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a technique for reducing current consumption of a semiconductor memory device including a read circuit having a boosted power supply circuit.

[0002]

2. Description of the Related Art As one of reading methods of a semiconductor memory device mounted in a microcomputer device, one of a plurality of memory cells arranged in a matrix is selected by a word line and a bit line and selected. A method of detecting stored information from a cell current of a memory cell by a sense amplifier is generally used. Further, there is a semiconductor memory device having a built-in booster power supply circuit for boosting a voltage supplied from the outside in order to supply power to the internal circuit of such a semiconductor memory device (for example, refer to Patent Document 1).

FIG. 1 shows the configuration of a semiconductor memory device having a conventional boost power supply circuit. In the figure, the microcomputer device 1
30 includes a CPU 121 that controls the entire microcomputer and a semiconductor memory device 120. Semiconductor memory device 1
Reference numeral 20 denotes a booster power supply circuit 113, a memory cell array 7 in which memory cells storing 1-bit information are arranged in a matrix, word lines 111 arranged in the Y direction of the memory cell array 7, and the differential amplifier circuit 4. Voltage V supplied
g and the row decoder 6 for selecting an arbitrary word line 111 according to the address information AddY from the CPU 121,
Bit lines 11 arranged in the X direction of the memory cell array 7
2 and the column decoder 8 that selects an arbitrary bit line 112 according to the address information AddX from the CPU 121.
, A sense amplifier 9 for reading 1-bit memory cell information selected by the row decoder 6 and the column decoder 8, a data latch 110 for latching read data from the sense amplifier 9, and a signal (SLO from the CPU 121.
W and NDS) and a pulse generation circuit 5 for controlling the operation of the sense amplifier 9.

The boosting power supply circuit 113 includes a reference voltage generating circuit 1, a boosting pump circuit 2 for generating a voltage Vp higher than a voltage VDD supplied from the outside, a generated voltage VREF of the reference voltage generating circuit 1 and a boosted voltage Vp. Vp voltage detection circuit 3 for controlling the operation of the booster pump circuit 2 according to the comparison of the reference voltage VRE and the generated voltage Vp of the booster pump circuit 2 are used as the reference voltage VRE.
And a differential amplifier circuit 4 that generates a voltage Vg that is twice that of F.

In the above configuration, when the addresses AddX and AddY are input to the row decoder 6 and the column decoder 8 during reading, the row decoder 6 selects one word line 111 by the address AddY and the column decoder 8 selects one bit line 112 by the address AddX. The sense amplifier 9 detects the storage content of the memory cell selected by the word line 111 and the bit line 112, and outputs an H level or L level signal DOUT according to the storage content. Then, the data latch 110 latches the signal DOUT and outputs Data.

When the above read operation is performed in a long cycle on the order of several μs, in order to reduce current consumption,
Generally, the sense amplifier 9 is activated only during the read operation from the memory cell. Also, the Vg voltage is
It is constantly generated by the boosting power supply circuit 113 for normal reading. FIG. 2 shows an operation sequence of each circuit when reading is performed in a long cycle.

In the figure, the CPU 1 is operated at time T2.
When the read control signal NDS output by 21 switches from the H level to the L level, the output SAAV of the pulse generation circuit 5 switches from the L level to the H level in response to this, and the sense amplifier 9 to which the SAAV is input is activated. . As a result, the sense amplifier 9 reads the stored information of the selected memory cell and outputs it from DOUT.
After that, the pulse generation circuit 5 switches the output SAAV from the H level to the L level at the timing of time T3, and the data latch 110 latches the output from DOUT in response to this, and continues to output until the latch time of the next cycle. The sense amplifier 9 stops its operation when the SAAV is switched to the L level at T3.

The voltage Vg generated by the boosting power supply circuit 113
Is stably generated by the reference voltage generating circuit 1 and the differential amplifier circuit 4. Voltage Vp generated in boost pump circuit 2
Is generated by controlling the operation / stop of the booster pump circuit 2 according to the detection result of the Vp voltage detection circuit 3, so that the waveform has a certain width. When the read operation is performed in a long cycle, the read by the sense amplifier 9 is activated only when reading from the memory cell, and after reading, the output information is latched and then stopped. In this case, the current consumption is smaller than that in the reading method in which the reading circuit is always operated.

[0009]

[Patent Document 1] Japanese Patent Laid-Open No. 10-302492

[0010]

However, as described above, the boosting power supply circuit 113 always operates during the cycle to generate the Vg voltage, and there is a problem that unnecessary current is consumed. Since the step-up power supply circuit 113 consumes particularly large current, the problem of unnecessary current consumption still remains.

Therefore, an object of the present invention is to provide a semiconductor memory device in which the current consumption of the read circuit incorporating the booster power supply circuit is further suppressed as compared with the conventional one.

[0012]

A semiconductor memory device that achieves the above object is a semiconductor memory device having a memory array, and a read means having a function of reading information stored in a memory cell and a memory cell. Boosting means having a function of boosting a voltage supplied from the outside to supply to the memory cell for reading the read information; start control means for causing the boosting means to start boosting after the start of the read cycle; A detecting unit that detects an event that the voltage boosted by the boosting unit has reached a predetermined value required for reading the information stored in the memory cell, and causes the reading unit to start the reading operation when the event is detected; , The boosting means stops boosting after a predetermined time required for the reading operation has elapsed since the event was detected by the detecting means And a stop control means.

It should be noted that the boosting means cannot instantly boost the voltage to a predetermined value, but after the boosting is started by the start control means, the voltage value is raised with the lapse of time, and as a result, the boosting is eventually completed. The applied voltage reaches a predetermined value. Here, the predetermined value is a value higher than the power supply voltage value, such as several times the power supply voltage value supplied from the outside. Further, when the detection means detects that the predetermined value has been reached, for example, a voltage (a stepped-down voltage, that is, a voltage divided by a resistor) indicating a fraction of the voltage obtained as a result of boosting is taken out for comparison, and It is performed by comparing the extracted voltage with a constant voltage lower than the power supply voltage value.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. <Semiconductor Memory Device 200> FIG. 3 shows the configuration of the semiconductor memory device according to the embodiment of the present invention. In the figure, a semiconductor memory device 200 includes a booster power supply circuit 201, a memory cell array 7 in which memory cells for storing 1-bit information are arranged in a matrix, and word lines 111 arranged in the Y direction of the memory cell array 7. The voltage Vg supplied from the boosting power supply circuit 201 and the address information AddY from the CPU
A row decoder 6 for selecting an arbitrary word line by and
A bit line 112 arranged in the X direction of the memory cell array 7, a column decoder 8 for selecting an arbitrary bit line 112 according to address information AddX from the CPU,
Sense amplifier 9 for reading information of 1-bit memory cell selected by the row decoder 6 and the column decoder 8.
A data latch 110 for latching the read data of the sense amplifier 9, a Vg voltage detection circuit 11 for detecting that the Vg voltage has become almost twice VREF, and a N
The latch circuit 107 stores the first rising edge of the detection output signal SAS of the Vg voltage detection circuit 11 after DS goes low and the output signal SASS of the latch circuit 107 after NDS goes low for a predetermined time. SAAV
A pulse generation circuit 12 that generates a signal, a reference voltage generation circuit 1, a Vp voltage detection circuit 3, a differential amplifier circuit 100, and Vg.
A control circuit 105 for controlling the voltage detection circuit 11 and the pulse generation circuit 12, and N-channel transistors 103, 10
4 and.

The boosting power supply circuit 201 has a reference voltage VREF.
Generating a reference voltage generating circuit 1 and a boosting pump circuit 2
And a differential amplifier circuit 100 that generates a voltage Vg that is twice the reference voltage VREF by using the voltage Vp that is generated by the boost pump circuit 2 and the voltage Vg and the voltage Vp are compared, and the boost pump according to the comparison result. The Vp voltage detection circuit 3 that controls the operation of the circuit 2, the level shifter 106, and the P-channel transistors 101 and 1 that supply the power supply voltage VDD to Vp and Vg.
02 and.

FIG. 4 is a time chart for explaining the operation of the semiconductor memory device 200 configured as above.
The read operation of the semiconductor memory device 200 shown in FIG.
It corresponds to the low speed mode of the microcomputer device, and the SLOW signal is always at the H level. The read operation in the low speed mode is controlled by the external signal NDS. When NDS is at H level, it is in a standby state in which reading is not performed, and when it is at L level, a reading operation is performed. NDS
One read cycle is from the time T1 when the L level is switched to the H level to the next time T1.

When NDS changes from the L level to the H level at the timing of time T1, the control circuit 105 outputs the signal RF.
ACT is switched from L level to H level and output.
By this switching, the reference voltage generating circuit 1 is activated, and the value of the reference voltage VREF becomes stable until the time T2. Next, when NDS changes from the H level to the L level at the timing of time T2, the control circuit 105 outputs the signal D
S is switched from L level to H level and output. Due to this switching, the Vp voltage detection circuit 3 and the differential amplifier circuit 1
00 and the Vg voltage detection circuit 11 are activated, and the pulse generation circuit 12 enters a waiting state for the SASS signal from the latch circuit 107.

The Vp voltage detection circuit 3 is activated while the signal DS is at the H level, operates or stops the boosting pump circuit 2 according to the detection result, and sets Vp to Vg + Vt (Vt is determined according to the characteristics of the transistor, for example. It is about 1 V.) More specifically, the Vp voltage detection circuit 3 is
When <Vg + Vt, a signal is generated for the boost pump circuit 2 to activate the boost pump circuit 2. As a result, the booster pump circuit 2 receives the signal from the Vp voltage detection circuit 3 when Vp <Vg + Vt and is activated, and the power supply voltage VD
It operates until the voltage Vp> Vg + Vt is higher than the voltage D (see the voltage relationship diagram in FIG. 5).

The differential amplifier circuit 100 is activated while the signal DS is at the H level, and the Vg voltage is used as a power source and the Vg voltage is VR.
The Vg voltage is increased so as to be twice the EF. The Vg voltage detection circuit 11 is activated while the signal DS is at H level,
It is detected that the Vg voltage has reached the target value of VREF voltage × 2 times, and when it is detected, the signal SAS is changed from L level to H level.
The level is switched and output (time T3).

When the signal SAS switches from L level to H level, the latch circuit 107 stores it and switches SASS from L level to H level and outputs it. The pulse generation circuit 12 receives the signal SASS at the H level and outputs the signal SA
AV is switched from L level to H level and output. The pulse generation circuit 12 switches the signal SAAV from the H level to the L level and outputs the signal SAAV after a predetermined time elapses after switching the signal SAAV to the H level. This predetermined time is
This is a necessary and sufficient period for the sense amplifier 9 to take out the voltage from the selected memory cell.

At time T3, the row decoder 6 and the column decoder 8 are supplied with the Vg voltage that has reached the target value, and are designated by the addresses AddY and AddX 1
The word line 111 and the bit line 112 of the book are selected. The sense amplifier 9 is activated in response to the signal SAAV being at the H level, and the selected word line 11 is activated.
The voltage from the memory cell at the intersection of 1 and the bit line 112 is amplified and output from DOUT.

Data latch 110 outputs DOUT output by sense amplifier 9 in response to signal SAAV switching from H level to L level at time T4.
Value is latched, and the latched value is continuously output as Data. Here, the term “latch” means to keep holding a specific value. The data latch 110 holds the value of DOUT output from the sense amplifier 9 from time T4 to time T4 of the next cycle, and continues to output it as Data.

Sense amplifier 9 stops its operation in response to signal SAAV switching from H level to L level at time T4. Further, control circuit 105 switches and outputs signal DS from H level to L level in response to signal SAAV switching from H level to L level at time T4. By switching the signal DS, the Vp voltage detection circuit 3, the differential amplifier circuit 100, Vg
The voltage detection circuit 11 stops its operation.

As described above, the semiconductor memory device 200
Receives the clocking of the signal NDS at time T1 → T2
→ T3 → T4 → T1 → T2 → T3 → T4 → T1. ． ． And the read operation is repeated. In this repetition, from time T4 to the next time T1, the semiconductor memory device 20
Since all the circuits in 0 are stopped, there is no current consumption during that time. Also, from time T4 to the next time T2, V
Since all the circuits that supply or extract charges to p and Vg are stopped, the Vp and Vg voltages are at time T4.
The Hi-z (high impedance) state is maintained while the voltage level at that time is maintained.

During this Hi-z state, the electric charges are slightly discharged by the junction leak (leakage current from the connection point), so that the Vp and Vg voltages are lowered. However, at time T2 of the next cycle, Vp and Vg reach the target values if the voltage is boosted by the discharged amount. Therefore, the boosting operation time becomes shorter than the voltage rising from VDD, and the current consumption of the boosting power supply circuit 201 is significantly reduced. <N-Channel Transistors 103, 104> When the Vp and Vg voltages drop to the ground level due to the voltage drop due to leakage between time T4 and time T2 of the next cycle, the boost pump circuit 2 and the difference between Raising the Vp and Vg voltages from the ground level to the target value by the dynamic amplifier circuit 100 requires a large amount of current consumption. In order to reduce such current consumption, there are transistors 103 and 104. The transistors 103 and 104 are diode-connected to the power supply voltages VDD and Vp and Vg, respectively, and have a function of suppressing a voltage drop due to leakage of Vp and Vg to Vdd-Vt. <Latch circuit 107> Here, the latch circuit 107 is required because if the SAS once changes to the H level at time T3, the SAS becomes the L level again due to noise on Vg (in FIG. And the pulse generation circuit 12 that operates by receiving the SAS.
Switches SAAV to L level without waiting for time T4. This is because the sense amplifier time for reading the stored information in the memory cell is insufficient and normal reading cannot be performed.

As described above, the semiconductor memory device according to the present embodiment detects that the Vg voltage has reached the target value, performs the reading for a predetermined time, and stops all the circuits except the reading time. Since the current consumption is reduced and the electric charges of Vp and Vg are held in a state where the voltage drop is small until the next read, the current consumption required for boosting is suppressed. The latch circuit 107 guarantees the time required for the sense amplifier operation. <Differential Amplifier Circuit 100> Next, a circuit configuration for preventing the voltage Vg generated by the differential amplifier circuit 100 from exceeding the target value (VREF × 2) will be described.

FIG. 6 shows the configuration of the differential amplifier circuit 100.
In the figure, the differential amplifier circuit 100 includes P-channel transistors 13, 16, 17, 22, 24, N-channel transistors 15, 23, 25, a resistance element 18, and a level shifter 20. In this configuration, 2
The areas surrounded by the two dotted lines respectively indicate the stop setting circuit 30.
0 and capacity switching circuit 301. The P-channel transistors 13, 16, 17 and the N-channel transistor 1
The portion composed of 5, 23 and the resistance element 18 is a conventional differential amplifier circuit.

First, the boosting power supply circuit 20 at time T2
A measure for avoiding the problem that Vg rises above the target value due to Vp being unnecessarily supplied to Vg at the time of startup of No. 1 will be described. Before the time T2, the signal DS is at the L level, so that P
The drain of the channel transistor 22 is conductive, and the drains of the N channel transistors 23 and 25 are blocked. In this state, nodes N1 and V
The potentials of ghf1 are Vp and Vg, respectively.

When the signal DS changes from the L level to the H level at time T2, the P-channel transistor 22 cuts off between the drain and the source, and the N-channel transistor 2
3 and 25 are electrically connected between the drain and the source. As a result, the voltage of the node Vghf1 drops from Vg toward Vg / 2. The node N1 whose voltage was Vp at time T2 does not drop to the potential for making the P-channel transistors 16 and 17 conductive until Vghf1 <VREF. Therefore, the stop setting circuit 300 causes the time T
Since the comparison operation is normally performed immediately after the differential amplifier circuit 100 is started in the second example, the Vg voltage does not rise above the target value when the circuit is started. <Capability Switching Circuit 301> Next, a countermeasure against overshoot in the charge supply from Vp to Vg will be described.

The differential amplifier circuit 100 must be operated even in the high speed mode in which the read operation of one address is performed in a short cycle such as several tens of ns (see FIG. 7). In the high speed mode, a current load on Vg occurs at the falling edge of NDS, and the Vg level decreases accordingly. Since the decrease in the Vg level needs to be restored by the next read cycle after several tens of ns, the total capability of the P-channel transistors 16 and 17 for supplying charges from Vp to Vg is increased for that purpose.

On the other hand, the read operation of one address is performed for several μs.
In the case of the low speed mode which is performed in the long cycle as described above, if both P-channel transistors 16 and 17 that supply charges from Vp to Vg are used, the Vg level rises faster due to excess capacity, and the response of the differential circuit catches up. Since it does not exist, the target voltage is exceeded and an overshoot state occurs, and reading occurs with the high voltage. In order to avoid this overshoot, in the low speed mode, the P channel transistor 24 is cut off so that the P channel transistor 16 is not used, and Vp to V
The capacity switching circuit 301 is configured so that only the P-channel transistor 17 is used to supply electric charge to g. <Vg voltage detection circuit 11> Next, the Vg voltage detection circuit 11
A circuit configuration for not outputting an erroneous detection result immediately after the circuit operation and a circuit configuration for surely detecting the Vg level at the target voltage will be described.

FIG. 8 shows the configuration of the Vg voltage detection circuit 11. In the figure, the Vg voltage detection circuit 11 includes P-channel transistors 30, 37, 38 and 39, N-channel transistors 31, 32, 33, 34, 36 and 40, a resistance element 41, a level shifter 47, inverters 43 and 4.
5, 48 and a NAND circuit 44. In the figure, the portions surrounded by two dotted lines are the offset circuit 400 and the stop setting circuit 401, respectively. P-channel transistors 30, 38, N-channel transistors 31, 3
The portion constituted by 2, 33, 40 and the resistance element 41 is a conventional differential amplifier circuit. <Stop Setting Circuit 401> First, a measure for preventing an erroneous detection result from being output when the circuit is activated at time T2 will be described.

Before time T2, the P-channel transistor 37 receives the fact that the signal DS is at L level.
The N-channel transistor 36 and the N-channel transistor 36 are electrically connected between the drain and the source, and the P-channel transistor 39 and the N-channel transistors 33 and 40 are electrically disconnected between the drain and the source. At this time, the potentials of the node N2 and Vghf2 are both 0V.

Since the node N2 is at 0V, the drain and source of the P-channel transistor 38 become conductive, and this conduction makes the node N4 high level.
The signal SAS output from the inverter 48 becomes L level. Further, since the node Vghf2 is 0V,
The drains and sources of the N-channel transistors 32 and 34 are cut off.

When the signal DS changes from the L level to the H level at time T2, the P channel transistor 37
The drain of the N-channel transistor 36 and the source of the N-channel transistor 36 are cut off, and the drain of the P-channel transistor 39 and the N-channel transistors 33 and 40 are turned on. The state of each node immediately after time T2 is the same as the state of each node when the Vg level is lower than the target value VREF × 2. In this state, the signal SAS outputs the L level immediately after the time T2, and the signal SAS is set to the H level even though Vg does not reach the target value.
There is no malfunction such as switching to the level. <Offset Circuit 400> Next, a circuit configuration for surely detecting the Vg level at the target value will be described.

Differential amplifier circuit 100 and Vg voltage detection circuit 1
Both reference voltages of 1 are VREF. Differential amplifier circuit 10
0 operates to control Vg so that Vg = VREF × 2, which is a target value, but the voltage is stabilized at a voltage lower than the target value by 0.01 V due to variations in characteristics of circuit elements and fluctuations in current load. In such a case, when the detection level of the Vg voltage detection circuit 11 is Vg = VREF × 2, the signal SAS output from the Vg voltage detection circuit 11 does not permanently change from the L level to the H level. Signal SA
Since S does not change to H level, the sense amplifier 9
Is a malfunction that the cycle ends without operating. To avoid this, the N-channel transistor 31
An N-channel transistor 34 having the same capability as is connected in parallel with an N-channel transistor 34. By doing so, the balance of the differential circuit is slightly inclined, and the detection level of the Vg voltage detection circuit 11 is Vg = VREF × 2-0.05V and Vg = V
It can be slightly decreased by 0.05 V from REF × 2. The reduction range is 0.05 V here, but N
It can be adjusted by changing the capability of the channel transistor 34.

It should be noted that a circuit in which the positive and negative of the voltage are inverted with respect to the circuit shown in the embodiment may be constructed. In this case, the N-channel transistor and the P-channel transistor shown in the embodiment are P-channel transistors, respectively. ,
It may be replaced with an N-channel transistor.

[0038]

The semiconductor memory device of the present invention is a semiconductor memory device having a memory array, and has a reading means having a function of reading information stored in a memory cell, and a read means for reading information stored in the memory cell. To this end, boosting means having a function of boosting a voltage supplied from the outside and supplying the boosted voltage to the memory cell, start control means for causing the boosting means to start boosting after the start of the read cycle, and boosting means boosted by the boosting means. A detection unit that detects an event that the voltage has reached a predetermined value required to read the information stored in the memory cell, and causes the reading unit to start a read operation when the event is detected; Stop control means for causing the boosting means to stop boosting after a lapse of a predetermined time required for the reading operation from the time when the event is detected.

With this configuration, the semiconductor memory device starts boosting the voltage to be supplied to the memory cell after the start of the read cycle, starts the read operation when the boosted voltage reaches a predetermined value, and then performs the read operation. The boosting is stopped after a predetermined time has elapsed from the start of the operation. This predetermined time is the time required for the reading means to perform the actual read operation. In this way, the boosting period of the voltage to be supplied to the memory cell is shortened to the required minimum in accordance with the read operation period, so that the current consumption is reduced compared to the case where the boosting period is set unnecessarily long. Has the effect of being reduced. In particular, if one cycle is a relatively long cycle such as several μs or more, the period during which the read operation is not performed is longer than the period required for the read operation during one cycle, so if the voltage is constantly boosted during one cycle. If this is done, unnecessary current will be consumed for a long period when the read operation is not performed. In this respect, the semiconductor memory device of the present invention boosts the voltage slightly before the start time of the actual read operation and stops the boost operation at the same time as the end of the read operation. No unnecessary current is consumed during periods when it is not done.

Further, in the semiconductor memory device, the reading means includes a sense amplifier having a function of amplifying and outputting a cell current of a memory cell selected from a plurality of memory cells, and the boosting means includes the present semiconductor. A reference voltage generation circuit that generates a constant voltage equal to or lower than the power supply voltage based on a power supply voltage input from the outside of the storage device, a boosting pump circuit having a function of generating a voltage higher than the power supply voltage, and the boosting pump circuit. A differential voltage having a function of generating an output voltage, which is a predetermined multiple of the reference voltage and higher than the power supply voltage, on the basis of the voltage generated by the reference voltage generation circuit and which is supplied to the memory cell. Using the voltage generated by the amplifier circuit and the differential amplifier circuit as a reference, the reference is compared with the voltage generated by the booster pump circuit, and the result of the comparison is compared. By performing control in accordance with the start and stop of the boosting operation of the boosting pump circuit Te, and a first voltage detection circuit having a function of converging a voltage generated in the booster pump circuit within a predetermined range. The detection means compares the voltage generated by the reference voltage generation circuit with a comparison voltage obtained by stepping down the output voltage generated by the differential amplification circuit to generate the differential amplification circuit. The start control means includes a second voltage detection circuit that detects an event that the output voltage has reached a preset voltage higher than the power supply voltage, and activates the sense amplifier when the event is detected. Activating the first voltage detection circuit and the differential amplifier circuit after the start of the read cycle to cause the boosting means to start boosting, and
The second voltage detection circuit is activated after the start of the read cycle, and the stop control means is configured to activate the second amplifier circuit after the predetermined time has elapsed since the sense amplifier was activated. The first voltage detection circuit and the first voltage detection circuit are brought into a functionally stopped state to stop the boosting by the boosting means, and further, after the predetermined time has elapsed after the sense amplifier was activated, the second voltage is detected. Disables the voltage detection circuit.

Each element in this configuration corresponds to FIG. 3, wherein the boosting means is the boosting power supply circuit 201, the reference voltage generating circuit is the reference voltage generating circuit 1, the boosting pump circuit is the boosting pump circuit 2, and the boosting pump circuit is the boosting pump circuit 2. The differential amplifier circuit is a differential amplifier circuit 100, the first voltage detection circuit is a Vp voltage detection circuit 3, and the second voltage detection circuit is a Vg voltage detection circuit 1.
1. The start control means and the stop control means correspond to the control circuit 105, respectively.

The semiconductor memory device further includes a sense amplifier stop control circuit for stopping the function of the sense amplifier when the predetermined time elapses after the event is detected by the second voltage detection circuit. And a sense amplifier output latch circuit that stores the output of the sense amplifier for a certain period after the function of the sense amplifier is stopped. In the semiconductor memory device, the step-up pump circuit has the highest power consumption, and the sense amplifier has the second highest power consumption. Therefore, in addition to stopping the boosting means including the boosting pump circuit at the end of the read operation, by stopping the sense amplifier, a further effect of reducing power consumption can be obtained. The semiconductor memory device is provided with a sense amplifier output latch circuit so that the output of the sense amplifier can be obtained even after the sense amplifier is stopped.

Further, in the semiconductor memory device, the second voltage detection circuit outputs a predetermined signal when activating the sense amplifier, and the semiconductor memory device outputs from the second voltage detection circuit. And a sense amplifier activation signal latch circuit for storing the predetermined signal to be stored in the sense amplifier for a certain period of time and transmitting the stored signal to the sense amplifier. When the second voltage detection circuit detects an event that the output voltage of the differential amplifier circuit is boosted and eventually reaches the target value, the second voltage detection circuit outputs the predetermined signal, and the sense amplifier receives the output of this signal. Activate. Here, the semiconductor memory device further includes a sense-up activation signal latch circuit that latches the output of the predetermined signal, and activates the sense amplifier in accordance with the output of the latch circuit to output the signal to the output of the differential amplifier circuit. Even if noise is generated and the output of the predetermined signal vibrates due to the influence of the noise, the sense amplifier operates stably without being affected by the vibration. As a result, there is no malfunction due to noise in the boosted voltage, and stable reading can be realized.

In the semiconductor memory device, the differential amplifier circuit further uses the comparison voltage obtained by resistance-dividing the output voltage of the differential amplifier circuit when the function of the differential amplifier circuit is stopped. , The first N-channel transistor that acts to make the output voltage the same as the output voltage, and the through current of the differential circuit portion of the differential amplifier circuit that are cut off when the differential amplifier circuit stops functioning. The second N-channel transistor and the gate of the P-channel transistor are connected to a node serving as an output voltage of the differential amplifier circuit, and when the differential amplifier circuit stops functioning, the node is the booster pump circuit. And a P-channel transistor that works so as to be short-circuited to the voltage generated by.

This configuration corresponds to the stop setting circuit 300 of FIG. 6, in which the first N-channel transistor is the N-channel transistor 25, the second N-channel transistor is the N-channel transistor 23, and the P-channel transistor is the P-channel transistor 22. Corresponds to each. According to this configuration, when the differential amplifier circuit is stopped, it is possible to set the intermediate node potential in consideration of the next change in operation. As a result, the voltage generated by the differential amplifier circuit does not inadvertently exceed the set voltage at the start of operation, and stable operation from the start of operation can be realized.

In the semiconductor memory device, the differential amplifier circuit is further provided with a plurality of charge supply Ps each connected to supply the charge generated by the booster pump circuit to the differential amplifier circuit. A cutoff control which is directly connected to a channel transistor and a part of the plurality of charge supply P-channel transistors, and operates to cut off or not to cut off the charge supply P-channel transistor according to the read mode. P-channel transistor for use.

This configuration corresponds to the capacity switching circuit 301 of FIG. 6, and the plurality of charge supplying P-channel transistors are P-channel transistors 16 and 17, and the cutoff control P-channel transistor is the P-channel transistor 24.
Respectively correspond to. According to this configuration, in the read mode of high-speed operation such that the read cycle is several tens of nanoseconds, all of the plurality of P-channel transistors for charge supply are used to enhance the charge supply capability and suppress the voltage drop due to the load circuit. In a low-speed read mode such as a read cycle of several tens of μs, a part of the plurality of P-channel transistors for charge supply is used to suppress the charge supply ability, and an overshoot that unintentionally exceeds the set voltage is performed. Has the effect of disappearing. As a result, stable voltage generation can be realized in both high speed operation and low speed operation.

In the semiconductor memory device, the second voltage detection circuit has a differential circuit portion including a first P-channel transistor and a second P-channel transistor connected in a current mirror. , The second voltage detection circuit is further connected in parallel to the first P-channel transistor whose gate and drain are connected, and when the function of the second voltage detection circuit is stopped,
A third P that acts to short the drain to the power supply voltage.
A channel transistor and a first N-channel transistor that is connected to the second P-channel transistor and that acts to ground the drain of the second P-channel transistor when the function of the second voltage detection circuit is stopped. A second through-current that acts to interrupt the through current of the differential circuit section when the second voltage detection circuit stops functioning.
Is connected to the node side of the output voltage of the differential amplifier circuit, and the comparison voltage obtained by resistance-dividing the output voltage of the differential amplifier circuit is detected by the second voltage detection circuit. A fourth P-channel transistor which functions to bring the voltage to the ground voltage when the circuit stops functioning, and a P-channel transistor and an N-channel transistor connected in series for converting the output of the differential circuit section into a logic signal. The N-channel transistor of the
And a cutoff unit that cuts off the voltage detection circuit when the voltage detection circuit stops functioning.

In this configuration, the first P-channel transistor and the second P-channel transistor correspond to the two P-channel transistors 30 in FIG. 8, the third P-channel transistor corresponds to the P-channel transistor 37, and the first P-channel transistor 37 corresponds to the first P-channel transistor 30. N channel transistor corresponds to the N channel transistor 36, the second N channel transistor corresponds to the N channel transistor 33, the fourth P channel transistor corresponds to the P channel transistor 39, and the P channel transistor in the cutoff section. Corresponds to the P-channel transistor 38, and the N-channel transistor in the cutoff section is the N-channel transistor 40.
Corresponding to.

According to this structure, when the second voltage detection circuit is stopped, it is possible to set the intermediate node potential in view of the next operation change. As a result, the second voltage detection circuit does not inadvertently output a detection signal at the start of operation, and a normal detection operation can be realized from the start of operation. Also, in the semiconductor memory device, the second voltage detection circuit includes a first differential circuit N channel for receiving the comparison voltage obtained by resistance-dividing the output voltage of the differential amplification circuit. The first differential circuit N-channel transistor so that the total capacity of the transistor is larger than that of the second differential circuit N-channel transistor that receives the voltage generated by the reference voltage generation circuit. Are connected in parallel.

With this configuration, the voltage generated by the differential amplifier circuit is stabilized at a slightly lower level, and the second voltage detection circuit does not permanently output the detection signal. As a result, the second voltage detection circuit does not malfunction and a normal detection operation can be realized.
Further, the semiconductor memory device further applies an electric charge to a node of a voltage generated by the boosting pump circuit from an external power supply to the node when the node is below a power supply voltage when the boosting pump circuit stops functioning. It includes a transistor that is diode connected to supply.

According to this structure, the voltage node at the output point of the booster pump circuit in the high impedance state is
Although the voltage drops due to leakage current, the minimum voltage is V
It can be suppressed to DD-Vt. As a result, at the time of the next voltage power supply circuit operation, VDD-Vt, not from the ground level.
Since the voltage can be boosted from, it is possible to realize lower current consumption compared to boosting from the ground level.

Further, the semiconductor memory device further includes an external power supply for the node of the output voltage generated by the differential amplifier circuit, when the node is below the power supply voltage when the function of the differential amplifier circuit is stopped. From a diode-connected transistor to supply charge to the node. According to this configuration, the voltage node at the output point of the booster pump circuit in the high impedance state causes a voltage drop due to the leakage current, but the minimum voltage is VDD-
It can be suppressed to Vt. As a result, the voltage can be boosted from VDD-Vt instead of the ground level when the next voltage power supply circuit operates, so that lower current consumption can be realized as compared with boosting from the ground level.

[Brief description of drawings]

FIG. 1 shows a configuration of a semiconductor memory device including a conventional boost power supply circuit.

FIG. 2 shows an operation sequence of each circuit when reading is performed in a long cycle.

FIG. 3 shows a configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 4 is a time chart showing the operation of the semiconductor memory device 200.

FIG. 5 shows the relationship between Vp, Vg, VDD and VREF.

FIG. 6 shows a configuration of a differential amplifier circuit 100.

FIG. 7 is a time chart showing the operation of the semiconductor memory device 200 during high speed operation.

FIG. 8 shows a configuration of a Vg voltage detection circuit 11.

[Explanation of symbols]

1 Reference voltage generation circuit 2 Boost pump circuit 3 Vp voltage detection circuit 4 Differential amplifier circuit 5 pulse generation circuit 6 Row decoder 7 memory cell array 8 column decoder 9 sense amplifier 11 Vg voltage detection circuit 12 pulse generation circuit 100 differential amplifier circuit 101 P-channel transistor 102 P-channel transistor 103 N-channel transistor 104 N-channel transistor 105 control circuit 106 level shifter 107 Latch circuit 110 data latch 111 word lines 112 bit line 113 Boost power supply circuit 120 semiconductor memory device 121 CPU 130 Microcomputer device 200 semiconductor memory device 201 Boost power supply circuit

Claims (10)

[Claims] 1. A semiconductor memory device having a memory array, the reading means having a function of reading information stored in a memory cell, and externally supplied for reading the information stored in the memory cell. Boosting means having a function of boosting the voltage and supplying the voltage to the memory cell, start control means for causing the boosting means to start boosting after the start of the read cycle, and the voltage boosted by the boosting means is stored in the memory cell. Detecting an event that has reached a predetermined value required for reading the information, and causing the reading means to start the reading operation when the event is detected; and a time when the event is detected by the detecting means. And a stop control means for stopping the boosting of the boosting means after a predetermined time required for the read operation has elapsed. Apparatus. 2. The reading means includes a sense amplifier having a function of amplifying and outputting a cell current of a memory cell selected from a plurality of memory cells, and the boosting means is provided from outside the semiconductor memory device. A reference voltage generation circuit that generates a constant voltage equal to or lower than the power supply voltage based on the input power supply voltage, a boost pump circuit that has a function of generating a voltage higher than the power supply voltage, and a voltage generated by the boost pump circuit. Based on a voltage generated by the reference voltage generation circuit as a reference, a differential amplifier circuit having a function of generating an output voltage that is a predetermined number times the reference voltage and higher than the power supply voltage and supplying the output voltage to the memory cell, Using the voltage generated by the differential amplifier circuit as a reference, the reference is compared with the voltage generated by the booster pump circuit, and the booster pump circuit boosts voltage according to the comparison result. A first voltage detection circuit having a function of converging the voltage generated by the booster pump circuit within a certain range by performing control related to start and stop of operation, wherein the detection means includes the reference voltage generation circuit. By comparing the voltage generated by the differential amplifier circuit with a comparison voltage obtained by stepping down the output voltage generated by the differential amplifier circuit, the preset output voltage generated by the differential amplifier circuit is higher than the power supply voltage. A second voltage detection circuit that detects an event that the voltage has reached a predetermined voltage and activates the sense amplifier when the event is detected, wherein the start control means includes the first voltage detection circuit after the start of a read cycle. By activating the voltage detection circuit and the differential amplifier circuit, the boosting means is started to boost, and further, the second voltage detection circuit is activated after the start of the read cycle, The stop control means sets the step-up pump circuit, the differential amplifier circuit, and the first voltage detection circuit to a function stop state after the predetermined time has elapsed since the sense amplifier was activated. The boosting means stops boosting, and further, the second voltage detection circuit is brought into a disabled state after the lapse of the predetermined time after the sense amplifier is activated. The semiconductor memory device according to 1. 3. The semiconductor memory device further includes sense amplifier stop control for stopping the function of the sense amplifier when the predetermined time has elapsed from the time when the event was detected by the second voltage detection circuit. 3. The semiconductor memory device according to claim 2, further comprising a circuit and a sense amplifier output latch circuit that stores the output of the sense amplifier for a certain period after the function of the sense amplifier is stopped. 4. The semiconductor memory device according to claim 2, wherein the second voltage detection circuit outputs a predetermined signal when activating the sense amplifier, and the semiconductor memory device includes: 3. The semiconductor memory device according to claim 2, further comprising a sense amplifier activation signal latch circuit that stores the predetermined signal that is output for a certain period of time and transmits a signal that is a storage result to the sense amplifier. 5. In the semiconductor memory device, the differential amplifier circuit further uses the comparison voltage obtained by resistively dividing the output voltage of the differential amplifier circuit when the function of the differential amplifier circuit is stopped. At
A first N-channel transistor that operates so as to have the same output voltage, and a first N-channel transistor that operates to cut off a through current of a differential circuit portion of the differential amplifier circuit when the differential amplifier circuit stops functioning. The N-channel transistor of 2 and the gate of the P-channel transistor are connected to a node serving as an output voltage of the differential amplifier circuit, and when the function of the differential amplifier circuit is stopped, the node is the booster pump circuit. 3. The semiconductor memory device according to claim 2, further comprising a P-channel transistor that works so as to be short-circuited with the generated voltage. 6. In the semiconductor memory device, the differential amplifier circuit is further provided with a plurality of charge supply circuits, each of which is connected to supply a charge generated by the booster pump circuit to the differential amplifier circuit. A P-channel transistor and a part of the plurality of charge-supplying P-channel transistors that are directly connected to each other, and function to switch off or not to block the charge-supplying P-channel transistor according to the read mode. The semiconductor memory device according to claim 2, further comprising a control P-channel transistor. 7. In the semiconductor memory device, the second voltage detection circuit has a differential circuit section including a first P-channel transistor and a second P-channel transistor connected in a current mirror. However, the second voltage detection circuit is further connected in parallel to the first P-channel transistor whose gate and drain are connected, and when the function of the second voltage detection circuit is stopped, the drain is connected. Connected to the second P-channel transistor and a third P-channel transistor that works so as to short-circuit the power supply voltage to the second P-channel transistor.
A first N-channel transistor that functions to ground the drain of the channel transistor, and a second N-channel transistor that functions to cut off a shoot-through current of the differential circuit section when the second voltage detection circuit stops functioning. A channel transistor is connected to the node side of the output voltage of the differential amplifier circuit, and the comparison voltage obtained by resistance-dividing the output voltage of the differential amplifier circuit is used as the comparison voltage of the second voltage detection circuit. A fourth P-channel transistor that functions to bring the voltage to the ground voltage when the function is stopped, and a P-channel transistor and a N-channel transistor connected in series for converting the output of the differential circuit unit into a logic signal. 3. The N-channel transistor according to claim 2, further comprising a cutoff unit that cuts off the N-channel transistor when the function of the second voltage detection circuit is stopped. Conductor memory device. 8. The semiconductor memory device according to claim 1, wherein the second voltage detection circuit is for a first differential circuit which receives the comparison voltage obtained by resistance-dividing the output voltage of the differential amplification circuit. With respect to the N-channel transistor, the first differential-circuit N-type transistor has a total capacity larger than that of the second differential-circuit N-channel transistor that receives the voltage generated by the reference voltage generation circuit. 3. The semiconductor memory device according to claim 2, wherein channel transistors are connected in parallel. 9. The semiconductor memory device further includes a node of a voltage generated by the boosting pump circuit, when the node is below a power supply voltage when the boosting pump circuit stops functioning, the node is switched from an external power supply to the node. 3. The semiconductor memory device according to claim 2, further comprising a transistor which is diode-connected so as to supply electric charge to. 10. The semiconductor memory device, further comprising: when the node of the output voltage generated by the differential amplifier circuit is below the power supply voltage when the node of the differential amplifier circuit stops functioning. 3. The semiconductor memory device according to claim 2, further comprising a transistor which is diode-connected so as to supply charges to the node from an external power supply.