KR20090071750A - Pump circuit of semiconductor memory apparatus and pumping method using the same - Google Patents

Abstract

A pump circuit of a semiconductor memory device and a pumping method using the same are provided to reduce current consumption for a pumping operation by reducing a size of an inverter and a capacitor. A pump circuit of a semiconductor memory device includes a first pumping unit(100) and a second pumping unit(200). The first pumping unit generates a primary pumping voltage in response to a first switching signal and a first pumping signal(ppes1). The first pumping unit generates a secondary boosting voltage by pumping the primary pumping voltage in response to a second switching signal and a second pumping signal(ppes2). The first pumping unit generates a boosting voltage(Vpp) in response to a third switching signal. The second pumping unit delays the second pumping signal, and generates a delay pumping signal(DLY-PP). The first pumping unit additionally pumps the secondary boosting voltage in response to the delay pumping signal.

Description

Pump circuit of semiconductor memory device and pumping method using same {Pump Circuit of Semiconductor Memory Apparatus and Pumping Method using the same}

The present invention relates to a semiconductor memory device, and more particularly, to a pump circuit having a low current consumption and a pumping method using the same.

The semiconductor memory device operates by receiving an external voltage Vdd, a ground voltage Vss, and the like supplied from the outside. Each of the voltages supplied from the outside is used after being converted into a voltage of a level required by each region inside the semiconductor memory device. In the semiconductor memory device, a core voltage Vcore, a bulk bias voltage Vbb, a boost voltage Vpp, and the like are used according to the needs of respective internal regions, and each internal circuit is used to generate an internal voltage using an externally supplied voltage. There is a voltage generating circuit. Among the internal voltages of the semiconductor memory device, the core voltage Vcore is generated by transforming the external voltage Vdd, and generally has a value slightly lower than the external voltage Vdd in normal operation. The core voltage Vcore is mainly used for a bit line sense amplifier amplification circuit. The boost voltage Vpp is used to compensate for the loss of the threshold voltage Vt of a cell transistor or to control a gate of a bit line isolation transistor or a word line driving circuit for controlling a gate of the cell transistor. Used. The bulk bias voltage Vbb is used to increase the data retention time by increasing the threshold voltage Vt of the cell transistor.

1 is a block diagram of a boosted voltage generation circuit according to the prior art.

Referring to FIG. 1, the boosted voltage generation circuit includes a detector 10, an oscillator 20, and a pump circuit 30. When the power up signal is enabled, the detector 10 detects the change in the boosted voltage VPP and compares it with the boosted reference voltage Vppref to generate a corresponding sensed signal det. The oscillator 20 generates a pulsed oscillation signal by oscillating the sensing signal det sensed by the detector, and decodes and outputs the oscillation signal. The pump circuit 30 performs a pumping operation in response to the decoding signals SW <1: 3> and ppes <1: 2> to generate a stable boosted voltage VPP.

2 is a circuit diagram of a pump circuit according to the prior art.

Referring to FIG. 2, the conventional pump circuit 30 may include a first switching unit 110 for supplying and cutting off the external voltage Vdd to the first node N1 in response to the first switching signal SW1. In response to the second switching signal SW1, in response to the second switching unit 120 and the third switching signal SW3 for supplying and blocking the voltage of the first node N1 to the second node N2. A third switching unit 130 for controlling the output of the second node N2 as a boosted voltage Vpp, and controlling whether to pump in response to the first pumping signal ppes1, In response to the first pump unit 140 and the second pumping signal pps2 for supplying and blocking voltage to the node N1, the pumping unit controls the pumping, and supplies and cuts off the voltage to the second node N2. It includes a second pump unit 150 for controlling.

In the pump circuit 30 according to the related art, when the first switching signal SW1 is turned on, the external voltage Vdd is supplied to the first node N1, and the first pump signal 30 responds to the first pumping signal ppes1. Primary pumping is performed as much as the size of the capacitor and provided to the first node N1. When the second switching signal SW2 is turned on, the voltage of the first node N1 is provided to the second node N2, and in response to the second pumping signal pps2, as much as the size of the second capacitor C2. Perform secondary pumping. Subsequently, the second switching signal SW2 is turned off and the third switching signal SW3 is turned on to output the voltage of the second node N2 as a boosted voltage Vpp. The first pumping signal ppes1 and the second pumping signal ppes2 are oscillation signals for pumping the first and second capacitors through the inverters IV1 to IV4, respectively. Here, the inverters IV1 to IV4 and the first and second capacitors are designed to be large in size.

Here, the first to third switching signals SW <1: 3> and the first and second pumping signals pp2 detect a boost voltage Vpp for pumping and output the output signal in the form of a pulse in the oscillator. The signal is generated by generating a signal and decoding the generated oscillator signal.

The conventional pump circuit 30 is supplied with an external voltage Vdd at the beginning of the semiconductor memory device using a single stage pump, and is further pumped once to generate a boosted voltage Vpp. Using the single-stage pump, a problem arises that the pumping is not complete at low voltage (Low Vdd). That is, for example, the power-up signal is normally enabled at 1.1V to 1,3V. When a single-stage pump is used, since the boost voltage (Vpp) of 2.2V to 2.6V is not generated, it is generally 3.1V to 3.3. Full operation is not possible in a boosted voltage generation circuit operating at V. Therefore, in general, the low voltage (Low Vdd) using a two-stage pump using a low voltage (Low Vdd) in order to achieve a normal operation.

However, the two-stage pump circuit uses a large inverter and capacitor at a high external voltage (High Vdd), which causes a large current consumption to perform a pumping operation, and may cause a malfunction of the circuit.

An object of the present invention is to implement a circuit capable of reducing current consumption when a high external voltage Vdd is used as a pump circuit of a semiconductor memory device.

The present invention provides a pump circuit of a semiconductor memory device, comprising: first pumping means for generating a primary pumping voltage in response to a pumping signal, and generating a boosted voltage in response to a switching signal, and delaying the pumping signal to delay the pumping signal. And generating second pumping means, wherein the first pumping means further pumps the boosted voltage in response to the delayed pumping signal.

According to the present invention, when a high external voltage Vdd is used as a pump circuit of a semiconductor memory device, the size of an inverter and a capacitor is reduced, and a pumping operation is added, thereby reducing current consumption.

3 is a block diagram of a pump circuit of a semiconductor memory device according to the present invention.

In a conventional pump circuit, a large current is consumed in generating a boosted voltage by using a large capacitor, a pumping element. However, the present invention implements a circuit to reduce the current consumption and generate a stable boosted voltage by reducing the size of the capacitor, pumping using an input pumping signal, and pumping the pumped signal further by delaying the pumping signal. It was.

Referring to FIG. 3, the pump circuit of the semiconductor memory device generates a primary pumping voltage in response to the first switching signal SW1 and the first pumping signal ppes1, and the second switching signal SW2 and the second pumping signal. a first pumping means 100 for pumping the primary pumping voltage in response to pp2 to generate a second boosted voltage, and generating a boosted voltage VPP in response to a third switching signal SW3, and the first pumping means 100. Second pumping means 200 for delaying the two pumping signal to generate a delayed pumping signal (DLY_PP).

The first pumping means 100 further pumps the secondary boosted voltage in response to the delay pumping signal DLY_PP.

Here, the switching signals SW1, SW2, and SW3, and the first and second pumping signals ppes1 and ppes2 are pulse signals generated by decoding signals output from the oscillator that is the front end of the pump.

The first pumping means 100 uses a capacitor of a small size in order to satisfy the purpose of reducing current consumption even if the loading time for generating the boosted voltage Vpp is long.

The first pumping means 100 charges an external voltage Vdd to the first node N1 using the first switching signal SW1, and responds to the first pumping signal ppes1. A primary pumping operation is performed to provide a primary boosted voltage to the first node N1. The secondary pumping operation is performed by the second pumping signal pps2 to provide the secondary boosted voltage to the second node N2. The second switching signal SW2 provides the voltage of the first node N2 to the second node N2, and the third switching signal SW3 supplies the voltage of the second node N2. Output as a boosted voltage (Vpp).

The second pumping means 200 performs an additional pumping operation of the voltage generated by the first pumping means 100 by delaying the second pumping signal ppes2.

4 is a circuit diagram of a pump circuit of a semiconductor memory device according to the present invention.

Referring to FIG. 4, the pump circuit of the semiconductor memory device may further include a first pumping means 100 performing primary and secondary pumping operations, and a third pumping operation in the first pumping means 100. A second pumping means 200 is performed.

The first pumping means 100 may include a first switching unit 110 and a second switching signal for supplying and blocking the external voltage Vdd to the first node N1 in response to the first switching signal SW1. In response to SW1, a second switching unit 120 for supplying and cutting off the voltage of the first node N1 to the second node N2, and the second node in response to a third switching signal SW3. The third switching unit 130 for controlling the output of the voltage N2 as the boosted voltage Vpp, and whether or not to pump the pump in response to the first pumping signal ppes1, to the first node (N1) A first pump unit 140 for supplying and blocking voltage, a second pumping control unit in response to the second pumping signal ppes2, and controlling the supply and blocking of the voltage to the second node N2 2 includes a pump unit 150.

The first switching unit 110 has a first NMOS transistor NM1 having a gate connected to the first switching signal SW1, a drain thereof connected to a power supply voltage VDD, and a source connected to the first node N1. It is composed of

When the first switching signal SW1 is disabled at the low level, the first switching unit 110 turns off the first NMOS transistor NM1 and turns the power supply voltage VDD to the first node. Block supply to N1). When the first switching signal SW1 is enabled at a high level, the first switching unit 110 turns on the first NMOS transistor NM1 and sets the external voltage Vdd to the first node N1. ).

The second NMOS transistor has a gate connected to the second switching signal SW2, a drain connected to the first node N1, and a source connected to the second node N2. It consists of (NM2).

When the first switching signal SW1 is disabled at the low level, the second switching unit 120 turns off the second NMOS transistor NM1 and resets the voltage of the first node N1 to the second node. Blocks provision to node N2. When the second switching signal SW2 is enabled at a high level, the second switching unit 120 turns on the second NMOS transistor NM2 and sets the voltage of the first node N1 to the second node. Provided to node N2.

The third NMOS 130 has a gate connected to the third switching signal SW3, a drain connected to the second node N2, and a source connected to the output voltage of the boosted voltage Vpp. A transistor NM3 is provided.

When the third switching signal SW3 is disabled at the low level, the third switching unit 130 blocks the providing of the voltage of the second node N2 to the boosting voltage Vpp output terminal. When the third switching signal SW3 is enabled at a high level, the third switching unit 130 outputs the voltage of the second node N2 as the boosted voltage Vpp.

The first pump unit 140 and the second pumping unit 150 have the same configuration, the output of the first pump unit 140 is provided to the first node (N1), the second pumping unit The output of 150 is provided to the second node N2. For example, only the first pumping unit 140 will be described.

The first pump unit 140 is connected in series with each other to receive and buffer the first pumping signal ppes1, and includes a first buffer 141 including first and second inverters IV1 and IV2, and the second pump unit 140. It includes a first capacitor (C1) is controlled whether the pumping operation in response to the output signal of the inverter (IV2). The first buffer 140 is connected to the first and second inverters IV1 and IV2 in series, and the first capacitor C1 is connected to an output terminal of the second inverter IV2 and the first node N1. ) Is connected between.

The first pump unit 140 does not perform a pumping operation when the first pumping signal pps1 is at a low level, and when the first pumping signal ppes1 is enabled at a high level, the first pump unit 140. The pumping operation is performed as much as the size of the capacitor C1 and provided to the first node N1.

Similarly, when the second pumping signal pps2 is at a low level, the second pump unit 150 also performs a pumping operation when the second pumping signal pps2 is at a high level without performing a pumping operation. Provided to 2 nodes N2.

The second pumping means 200 includes an even number of inverters IV6 to IV9 in the form of an interchain connected in series with each other by delaying the second pumping signal ppes2 for a predetermined time.

The second pumping means 200 performs the second pumping of the second pumping signal ppes2 and additionally performs the third pumping because the loading time reaching the boosted voltage Vpp is long.

In more detail, it is assumed that the pump circuit pumps the amount of voltage pumped by the first capacitor C1 and the second capacitor C2 by an external voltage Vdd. The pump circuit of the present invention charges the external voltage Vdd to the first node N1 when the first switching signal SW1 is enabled at a high level. The first node N1 rises to the level of the external voltage Vdd. When the first pumping signal pps1 is enabled at a high level, the first pumping operation is performed as much as the size of the first capacitor C1. The first node N1 rises to twice the external voltage Vdd. Subsequently, when the second switching signal SW2 is enabled, the first switching signal SW1 is disabled. The voltage of the first node N1 is provided to the second node N2. Subsequently, when the second pumping signal pps2 is enabled at a high level, the second switching signal SW2 is disabled and performs a secondary pumping operation by the size of the second capacitor C2. Thereafter, when the delay pump signal DLY_PP is enabled at a high level delayed by a predetermined time, the third pumping operation is performed. The second node N2 rises to a level of three times the external voltage Vdd. When the third switching signal SW3 is enabled, the voltage of the second node is output as a boosted voltage Vpp.

When the above operation is continuously performed with a minute delay, the first node N1 is charged with the level of the external voltage Vdd when the first switching signal SW1 is enabled, and the When the first switching signal SW1 is disabled and the first pumping signal ppes1 is enabled, the first switching signal SW1 is occupied by twice the external voltage Vdd.

When the second switching signal SW2 is enabled, the second node Vdd is charged with a double external voltage VDD, the second switching signal SW2 is disabled, and the second pumping is performed. When signal pps2 is enabled, it is occupied by three times the external voltage Vdd.

5 is a timing diagram of a pump circuit according to the present invention.

Referring to FIG. 5, in the pump circuit, the first switching signal SW1, the third switching signal SW3, and the second pumping signal pps2 have the same phase, and the second switching signal SW2 is delayed. The pump signal DLY_PP and the first pumping signal ppes1 have a phase opposite to that of the first switching signal SW1, the third switching signal SW3, and the second pumping signal ppes2.

In the pump circuit of the present invention, when the first switching signal SW1 is enabled and the second pumping signal pps2 is enabled at a high level, the first node N1 is connected to an external voltage Vdd. The second node N2 is charged with a triple external voltage Vdd. When the third switching signal SW3 is enabled at a high level, the pump circuit outputs a voltage occupied by the triple external voltage Vdd as a boosted voltage Vpp. Subsequently, when the second switching signal SW2 and the first pumping signal ppes1 are enabled at a high level, the first switching signal SW1, the third switching signal SW3, and the second pumping are performed. The signal pps2 and the delay pump signal DLY_PP are disabled. The first node N1 is charged with a double external voltage Vdd by the first pumping signal ppes1. The second switching signal SW2 provides a voltage occupied by the double external voltage Vdd to the second node N2. Subsequently, the first switching signal SW1 is enabled at a high level, and the second pumping signal pps2 is enabled at a high level. The first node N1 is occupied by an external voltage Vdd. The second node N2 is occupied by three times the external voltage Vdd. When the third switching signal SW3 is enabled at a high level, the voltage of the second node N2 is generated as the boosted voltage Vpp.

When the above operation is repeated, when the first switching signal SW1, the second pumping signal pps2, and the third switching signal SW3 are enabled, the first node N1 may turn on an external voltage ( Vdd), and the second node N2 generates a voltage occupied by three times the external voltage Vdd as the boosted voltage Vpp. Subsequently, when the second switching signal SW2 and the first pumping signal ppes1 are enabled, the first node N1 is charged with a double external voltage Vdd, and the second node ( Vdd) is occupied by the voltage of the first node N1.

6 is a pump circuit of a semiconductor memory device according to another embodiment of the present invention.

Referring to FIG. 6, the pump circuit of another embodiment may further include a third pumping means 300 that performs a pumping action between the first pumping means 100 and the second pumping means 200 shown in FIG. 3. It has a configuration.

The third pumping means 300 includes a third capacitor C3 having a small size. The third capacitor C3 serves to perform an amplification operation and is a means for performing additional pumping to a size smaller than that of the second capacitor C2 shown in FIG. 3.

The pump circuit of another embodiment generates a primary pumping voltage in response to the first switching signal SW1 and the first pumping signal ppes1, and responds to the second switching signal SW2 and the second pumping signal ppes2. And a second pumping means 100 for generating a boosted voltage in response to the third switching signal SW3 and a second pumping signal ppes2 in response to the second pumping signal pps2. In addition, the second pumping means 200 for outputting the delay pumping signal (DLY_PP) for performing the pumping operation, and the pumping operation to the secondary pumping voltage in response to the delay pumping signal (DLY_PP), the secondary pumping Third pumping means 300 for outputting an additional pumping signal (add_pp) for performing a pumping operation to further the voltage.

Specifically, in order to perform the pumping operation with the boosted voltage VPP, the first and second pumping means 100 and 200 are the same as the operation shown in FIG. The third pumping means 300 receives the delay pumping signal DLY_PP and performs a third pumping operation to output an additional pumping signal add_pp that rises to the boosted voltage VPP. The second capacitor C2 receiving the additional pumping signal add_pp increases to a boosted voltage VPP by performing a quaternary pumping operation.

By further pumping as compared to FIG. 3, the time for reaching the boosted voltage VPP is shortened.

7A is a principle of operation of a conventional pump circuit, and FIG. 7B is a principle of pump operation of a pump circuit according to the present invention.

FIG. 7A is a conventional pump circuit, which uses a large sized capacitor to quickly pump to a boosted voltage Vpp, but consumes a lot of power. Figure 7b is a pump circuit according to the present invention by using a small size capacitor, the loading time to reach the boost voltage (Vpp) is long, but additional pumping to reduce the loading time, to the boost voltage (Vpp) Indicates that the pumping time can be reduced.

The pump circuit of the semiconductor memory device according to the present invention uses the small size capacitors C1 and C2 to reduce power consumption and delay the second pumping signal pps2 to perform the third or fourth pumping operation. As a result, the loading time of reaching the boosted voltage (Vpp) can be shortened.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a block diagram of a boosted voltage generation circuit according to the prior art;

2 is a circuit diagram of the pump circuit shown in FIG.

3 is a block diagram of a pump circuit of a semiconductor memory device according to the present invention;

4 is a circuit diagram of a pump circuit of a semiconductor memory device according to the present invention;

5 is a timing diagram of a semiconductor memory device according to the present invention;

6 is a pump circuit of a semiconductor memory device according to another embodiment of the present invention; and

7 is a principle of operation of the conventional pump circuit and of the pump circuit of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: first pumping means 110: first switching unit

120: second switching unit 130: third switching unit

140: first pump unit 150: second pump unit

200: second pumping means 210: delay unit

220: signal combination unit 300: third pumping means

Claims (7)

First pumping means for generating a primary pumping voltage in response to the pumping signal and generating a boosted voltage in response to the switching signal, and A second pumping means for delaying said pumping signal to produce a delayed pumping signal, And the first pumping means further pumps the boosted voltage in response to the delay pumping signal. The method of claim 1, The first pumping means, A switching unit for controlling whether a voltage is supplied to a first node in response to the switching signal; And a pump unit configured to provide the primary pumping voltage to the first node in response to the pumping signal. The method of claim 2, The pump unit, When the pumping signal is enabled, providing the boosted voltage to the first node, And if the pumping signal is disabled, stop providing the boosted voltage to the first node. The method of claim 3, wherein The pump unit, A buffer for buffering and outputting the pumping signal; and And a first capacitor coupled between the output end of the buffer and the first node. The method of claim 4, wherein The second pumping means, Consists of a delay, A pump circuit of a semiconductor memory device characterized in that it is connected to an output terminal of said delayer and a connection terminal of said buffer and said first capacitor. The method of claim 5, wherein And a third pumping means connected between an output end of said delayer and a connection end of said buffer and said first capacitor. The method of claim 6, The third pumping means, A pump circuit of a semiconductor memory device, characterized in that the second capacitor.

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