CN107481745B - Negative booster circuit, semiconductor device and electronic device - Google Patents
Negative booster circuit, semiconductor device and electronic device Download PDFInfo
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- CN107481745B CN107481745B CN201610402677.7A CN201610402677A CN107481745B CN 107481745 B CN107481745 B CN 107481745B CN 201610402677 A CN201610402677 A CN 201610402677A CN 107481745 B CN107481745 B CN 107481745B
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Abstract
The invention provides a negative boost circuit, a semiconductor device and an electronic apparatus. The negative boost circuit includes a first transmission circuit configured to transmit a reference signal to a first boost node; a first delay circuit configured to generate a first voltage boost signal based on a feedback signal of the first transmission circuit and a first boost enable signal; a first voltage boost circuit configured to convert a voltage of the first boost node to a first-order negative bias voltage based on the first voltage boost signal, wherein the first delay circuit is configured to have a first predetermined delay between a feedback signal of the first transfer circuit and the first voltage boost signal. The negative booster circuit of the present invention has a more efficient negative booster circuit, and the semiconductor device and the electronic apparatus of the present invention have better read operation performance.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a negative booster circuit, a semiconductor device and an electronic device.
Background
With the development of semiconductor process technology, flash memories (flash memories) with faster access speed have been developed for memory devices. Flash memory has the characteristics of being capable of storing, reading and erasing information for many times, and the stored information does not disappear after power failure, so flash memory has become a nonvolatile memory widely used in personal computers and electronic devices.
The PMOS type flash memory requires a negative boost circuit (negative boost circuit) for generating a negative bias voltage (e.g., -1.2V) using a 0V or VDD (operating voltage, e.g., 1.2V) bias voltage for a read operation. In low power applications, a two-stage negative boost circuit (dual stage negative boost circuit) is commonly used, and the basic principle is as follows: after the enable signal is applied, first, under the action of the first bias signal, the first stage of boosting is carried out to generate a first negative bias, and after the first stage of boosting is completed, the second stage of boosting is carried out to boost the first negative bias to a target negative bias. However, in the current two-stage negative boost circuit, there is a problem that the enabling of the transmission transistor and the bias applying action are overlapped in the first stage and the second stage of boosting, namely, the bias is already applied before the transmission transistor is turned off, which makes the final negative bias (or boost effect) not ideal.
Therefore, it is necessary to provide a new negative boost circuit to solve the above problems.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
To overcome the problems, an aspect of the present invention provides a negative boost circuit for generating a negative bias voltage, the negative boost circuit comprising: a first transmission circuit configured to transmit a reference signal to a first boost node; a first delay circuit configured to generate a first voltage boost signal based on a feedback signal of the first transmission circuit and a first boost enable signal; a first voltage boost circuit configured to convert a voltage of the first boost node to a first-order negative bias voltage based on the first voltage boost signal, wherein the first delay circuit is configured to have a first predetermined delay between a feedback signal of the first transfer circuit and the first voltage boost signal.
Further, the first transmission circuit includes a first transmission transistor and a first voltage feedback node, a source end of the first transmission transistor is connected to the reference signal, a drain end of the first transmission transistor is connected to the first boost node, and a gate end of the first transmission transistor is connected to the first voltage feedback node.
Further, the first transmission circuit further includes a first switch transistor and a second switch transistor, a source end of the first switch transistor is connected to a working power supply, a drain end of the first switch transistor is connected to the first voltage feedback node, a gate end of the first switch transistor is connected to a first transmission enable signal, a source end of the second switch transistor is connected to the first voltage feedback node, a drain end of the second switch transistor is connected to the first voltage boost node, a gate end of the second switch transistor is connected to the first transmission enable signal, and the first transmission enable signal is configured to turn off the first switch transistor and turn on the second switch transistor.
Further, the first boost circuit includes a first boost capacitor, a first end of the first boost capacitor is connected to the first boost node, a second end of the first boost capacitor is connected to the first voltage boost signal, and the first delay circuit is configured to change the first voltage boost signal from a high level to a low level after the first transmission transistor is turned off, so that the voltage of the first boost node is changed into a first-order negative bias.
Further, the first delay circuit comprises a first phase inverter, a second phase inverter, a nor gate and a third phase inverter, wherein the input end of the first phase inverter is connected with the first voltage feedback node, the output end of the first phase inverter is connected with the input end of the second phase inverter, the output end of the second phase inverter is connected with the first input end of the nor gate, the second input end of the nor gate is connected with the first lifting enable signal, the output end of the nor gate is connected with the input end of the third phase inverter, and the output end of the third phase inverter outputs the first voltage lifting signal.
Further, still include: a second transmission circuit configured to transmit a signal of the first boost node to a second boost node; a second delay circuit configured to generate a second voltage boost signal based on a feedback signal of the second transmission circuit and a second boost enable signal; a second voltage boost circuit configured to convert the voltage of the second boost node from the first-order negative bias to a second-order negative bias based on the second voltage boost signal, wherein the second delay circuit is configured to have a second predetermined delay between the feedback signal of the second transmission circuit and the second voltage boost signal.
Further, the second transmission circuit includes a second transmission transistor, a third switching transistor, a fourth switching transistor, a second voltage feedback node, and a third voltage feedback node, a source end of the second transmission transistor is connected to the first boost node, a drain end of the second transmission transistor is connected to the second boost node, a gate end of the second transmission transistor is connected to the second voltage feedback node, a source end of the third switching transistor is connected to the first boost node, a drain end of the third switching transistor is connected to the third voltage feedback node, a gate end of the third switching transistor is connected to a second transmission enable signal, a source end of the fourth switching transistor is connected to the second voltage feedback node, a drain end of the fourth switching transistor is connected to the second boost node, and a gate end of the fourth switching transistor is connected to the third voltage feedback node, the second pass enable signal is configured to turn off the second pass transistor.
Further, the second transmission circuit further includes a fifth switching transistor and a sixth switching transistor, a source end of the fifth switching transistor is connected to a working power supply, a drain end of the fifth switching transistor is connected to the third voltage feedback node, a gate end of the fifth switching transistor is connected to the second transmission enable signal, a source end of the sixth switching transistor is connected to the working power supply, a drain end of the sixth switching transistor is connected to the second voltage feedback node, a gate end of the sixth switching transistor is connected to the third transmission enable signal, and levels of the second transmission enable signal and the third transmission enable signal are opposite.
Further, the second boost circuit includes a second boost capacitor, a first end of the second boost capacitor is connected to the second boost node, a second end of the second boost capacitor is connected to the second voltage boost signal, and the second delay circuit is configured to convert the second voltage boost signal from a high level to a low level after the second transmission transistor is turned off, so that the voltage of the second boost node is converted to a second-order negative bias.
Further, the second delay circuit includes a fourth inverter, a fifth inverter and a nand gate, wherein an input end of the fourth inverter is connected to the third voltage feedback node, an output end of the fourth inverter is connected to an input end of the fifth inverter, an output end of the fifth inverter is connected to a first input end of the nand gate, a second input end of the nand gate is connected to the second lifting enable signal, and an output end of the nand gate outputs the second voltage lifting signal.
The first and second lift-off enable signals are configured to have a set delay therebetween.
According to the negative boost circuit, the effect of the first voltage boost signal occurs after the connection between the first transmission circuit and the reference signal is turned off, and the effect of the second voltage boost signal occurs after the connection between the second transmission circuit and the first boost node is turned off, so that the turn-off time of the transmission circuit and the effect time of the voltage boost signal are not overlapped, the boost of each step is lower than that of the current circuit, the power efficiency and the effective current are improved, and better negative boost is realized.
Another aspect of the present invention provides a semiconductor device including the negative boost circuit described above and a memory cell to which the negative boost circuit is connected.
The semiconductor device provided by the invention has a more efficient negative booster circuit, so that the reading operation performance is improved.
Still another aspect of the present invention provides an electronic device including the semiconductor device described above and an electronic component connected to the semiconductor device.
The electronic device provided by the invention has similar advantages due to the semiconductor device.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1 illustrates a circuit schematic of a present two-stage negative boost circuit;
FIG. 2 shows a block diagram of a negative boost circuit according to the present invention;
FIG. 3 shows a circuit schematic of a negative boost circuit in accordance with an embodiment of the present invention;
FIG. 4 shows a schematic diagram of simulation results for the negative boost circuit shown in FIG. 3;
fig. 5 shows a schematic structural diagram of an electronic device according to an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity to indicate like elements throughout.
It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Fig. 1 shows a conventional two-stage negative boost circuit (dual stage negative boost circuit).
As shown in fig. 1, the negative boost circuit includes a first transmission circuit 101, a first voltage boost circuit 102, a second transmission circuit 103, a second voltage boost circuit 104, and a delay circuit 105.
The first transfer circuit 101 includes a first transfer transistor N1, first and second switching transistors P3 and N3, a first voltage feedback node 1N0 and a first boost node 1N1 for transferring a reference voltage to a first boost node IN 1. Illustratively, the reference voltage is a ground voltage VSS (e.g., 0 v). The first transfer transistor N1 is an NMOS transistor having a drain terminal connected to the reference voltage, a source terminal connected to the first boost node 1N1, and a gate terminal connected to the first voltage feedback node 1N 0. The first switch transistor P3 is a PMOS transistor, and has a source terminal connected to the working power supply VDD, a drain terminal connected to the first voltage feedback node 1N0, and a gate terminal connected to the first transmission enable signal EN. The second switch transistor N3 is an NMOS transistor, and has a drain connected to the first voltage feedback node 1N0, a source connected to the first boost node, and a gate connected to the first transmission enable signal EN.
The first voltage boost circuit 102 includes a first boost capacitor, illustratively a PMOS capacitor P1, with a source-drain short serving as a PMOS capacitor having one end (or gate) connected to the first boost node 1N1 and the other end (or source-drain) connected to the first boost enable signal KICK 1.
In case that the first transmission enable signal EN is at a low level (L or 0), the first switching transistor P3 is turned on, the first voltage feedback node 1N0 is at a high level, the first transmission transistor N1 is turned on, and the second switching transistor N3 is turned off, so that the first boosting node is at 0V (or ground voltage), and the first boosting enable signal KICK1 is at a high level (e.g., VDD). When boosting is required, the level of the first transmission enable signal EN is changed from a low level to a high level, and simultaneously the first boost enable signal KICK1 is changed from a high level (e.g., VDD) to a low level (e.g., 0V), such that the first switching transistor P3 is turned off, the second switching transistor N3 is turned on, the first voltage feedback node 1N0 and the first boost node 1N1 are turned on, the level at the first voltage feedback node 1N0 is gradually decreased, and is changed from VDD to 0V, such that the first transmission transistor N1 is turned off, and then the level of the first boost node 1N1 is gradually decreased, and is changed from 0V to a first-order negative bias (e.g., -0.5V). That is, after the first transfer enable signal transitions to the high level, the first lift enable signal KICK1 transitions from the high level to the low level (e.g., from VDD to 0V), and the level of the first pumping node 1N1 transitions from 0V to the first-order negative bias (e.g., -0.5V).
In this process, since the level transition of the first voltage feedback node 1N0 is a gradual process, the situation may occur that the first pass transistor N1 is not turned off yet and the first lift enable signal KICK1 has transitioned, so that the first-order negative bias voltage is lower than the ideal value (e.g., the ideal value is-0.5V, and can only reach-0.45V actually).
The second transmission circuit 103 includes a second transmission transistor N2, third and fourth switching transistors N4 and N5, a fifth switching transistor P4, a sixth switching transistor P5, a second voltage feedback node 1N2, a second voltage feedback node 1N3, and a second boosting node 1N4, and transmits a signal of the first boosting node 1N1 to the second boosting node 1N 4.
Illustratively, the second pass transistor N2 is an NMOS transistor having a source terminal connected to the first boost node 1N1, a gate terminal connected to the second voltage feedback node 1N2, and a drain terminal connected to the second boost node 1N 4. The third switching transistor N4 is an NMOS transistor, and has a source terminal connected to the first boost node 1N1, a drain terminal connected to the third voltage feedback node 1N3, and a gate terminal connected to the second transmission enable signal 1N 2. The fourth switching transistor N5 is an NMOS transistor, and has a source terminal connected to the second voltage feedback node 1N2, a drain terminal connected to the second boosting node 1N4, and a gate terminal connected to the third voltage feedback node 1N 3. The fifth switching transistor P4 is a PMOS transistor, and has a source terminal connected to the working power supply VDD, a drain terminal connected to the third voltage feedback node 1N3, and a gate terminal connected to the second transmission enable signal EN 2. The sixth switching transistor P5 is a PMOS transistor, and has a source terminal connected to the operating power supply VDD, a drain terminal connected to the second voltage feedback node 1N2, and a gate terminal connected to the third transmission enable signal EN2 b. Wherein the second transfer enable signal EN2 and the third transfer enable signal EN2b are opposite in level (or opposite in phase).
The second voltage boost circuit 104 includes a second boost capacitor P2, which is illustratively a PMOS capacitor having a source-drain short functioning as a capacitor, one end (or gate end) connected to the second boost node and the other end (or source-drain end) connected to the second boost enable signal KICK 2.
In the case that the first transmission enable signal EN is low (L or 0), the second transmission enable signal EN2 is at a high level, the third transmission enable signal EN2b is at a low level, and the second lift enable signal KICK2 is at a high level (e.g., VDD). at this time, the fifth switching transistor P4 is turned off, the sixth switching transistor P5 is turned on, the third switching transistor N4 is turned on, the fourth switching transistor N5 is turned off, and the second voltage feedback node 1N2 is at a VDD level. The second voltage feedback node 1N3 and the first boost node 1N1 are at the same level, VSS.
When the first transfer enable signal EN is high, the level of the first pumping node 1N1 is changed from 0V (i.e., VSS) to the first-order negative bias (e.g., -0.5V) as described above, and the third voltage feedback node 1N3 is turned on with the first pumping node 1N1, thereby also changing from 0V (i.e., VSS) to the first-order negative bias (e.g., -0.5V). After a set delay (realized by the delay circuit 105), that is, after the level of the first boosting node 1N1 is changed to a first-order negative bias (for example, -0.5V), the level of the second transfer enable signal EN2, the third transfer enable signal EN2b, and the second lift enable signal KICK2 are changed by the set delay, even if the second transfer enable signal EN2 is changed from a high level to a low level, the third transfer enable signal EN2b is changed from a low level to a high level, the second lift enable signal KICK2 is changed from a low level to a high level, so that the fifth switching transistor P4 is turned on, the sixth switching transistor P5 is turned off, the third switching transistor N4 is turned off, the level of the third voltage feedback node 1N3 is raised from a low (-0.5V) to VDD, the fourth switching transistor N5 is turned on, and then the level of the second voltage feedback node 1N2 is lowered from a high level, and the second transfer transistor N2 is turned off, then, the level of the second pumping node 1N4 gradually decreases, and changes from the first-order negative bias (-0.5V) to the second-order negative bias (e.g., -1.0V). That is, after the first transfer enable signal EN2 is transited to the high level for a period of time, during the transition of the second lift enable signal KICK2 from the high level to the low level (for example, from VDD to 0V), the level of the second BOOST node 1N4 is transited from the first-order negative bias to the second-order negative bias (for example, -1.0V), so that the output terminal BOOST outputs the target negative bias.
In this process, since the level transition of the second voltage feedback node 1N2 and the third voltage feedback node 1N3 is a gradual process, the situation may occur that the second pass transistor N2 is not turned off and the second lift enable signal KICK2 has transitioned, so that the second-order negative bias voltage is lower than the ideal value (e.g., the ideal value is-1.0V, and actually only-0.9V can be reached).
The present invention is improved to solve the problem of the current two-stage negative boost circuit, and as shown in fig. 2, the negative boost circuit of the present invention includes a first transmission circuit 201, a first delay circuit 203, and a first voltage boost circuit 205. Wherein the first transmission circuit 201 is configured to transmit the reference signal to the first boost node 1N1, the first delay circuit 203 is configured to generate a first voltage boost signal KICK1 'based on the feedback signal of the voltage feedback node 1N0 of the first transmission circuit 201 and the first boost enable signal 1, and the first voltage boost circuit 205 is configured to convert the voltage of the first boost node 1N1 into a first-order negative bias under the action of the first voltage boost signal KICK 1'. Wherein the first delay circuit 203 is configured to have a first predetermined delay between the feedback signal of the first transmission circuit 201 and the first voltage rising signal, so that the first voltage rising circuit 205 does not convert the voltage of the first voltage boosting node 1N1 into a first-order negative bias voltage until the connection between the first transmission circuit 201 and the reference signal is turned off.
Further, the negative boost circuit of the present invention further includes a second transmission circuit 202, a second delay circuit 204, and a second voltage boost circuit 206. Wherein the second transmitting circuit 202 is configured to transmit the signal of the first boosting node 1N1 to the second boosting node 1N 4; the second delay circuit 204 is configured to generate a second voltage boost signal based on the feedback signal of the voltage feedback node 1N3 of the second transmission circuit 202 and the second boost enable signal; the second voltage boost circuit 206 is configured to convert the voltage of the second boost node 1N4 from the first-order negative bias to a second-order negative bias under the action of the second voltage boost signal. Wherein the second delay circuit 204 is configured to have a second predetermined delay between the feedback signal of the second transmission circuit 202 and the second voltage boost signal, so that the second voltage boost circuit 206 converts the voltage of the second boost node 1N4 into a second-order negative bias after the connection between the second transmission circuit 202 and the first boost node is turned off.
According to the negative boost circuit, the effect of the first voltage boost signal occurs after the connection between the first transmission circuit and the reference signal is turned off, and the effect of the second voltage boost signal occurs after the connection between the second transmission circuit and the first boost node is turned off, so that the turn-off time of the transmission circuit and the effect time of the voltage boost signal are not overlapped, the boost of each step is lower than that of the current circuit, the power efficiency and the effective current are improved, and better negative boost is realized.
It is understood that the negative boost circuit according to the present invention may include two-step boost, or may include only one-step boost or more-step boost, i.e. include one or more circuits like the first transmission circuit 201, the first delay circuit 203 and the first voltage boost circuit 205, or the second transmission circuit 202, the second delay circuit 204 and the second voltage boost circuit 206.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Example one
FIG. 3 shows a circuit schematic of a negative boost circuit in accordance with an embodiment of the present invention; fig. 4 is a diagram showing simulation results of the negative boost circuit shown in fig. 3. The negative boost circuit of the present invention is described in detail below with reference to fig. 3 and 4.
As shown in fig. 3, the negative boost circuit of the present embodiment is a two-stage boost circuit, wherein the first-stage boost circuit includes a first transmission circuit 201, a first delay circuit 203, and a first voltage boost circuit 205. The second stage boost circuit includes a second pass circuit 202, a second delay circuit 204, and a second voltage boost circuit 206. The two-stage boost circuit is described in detail below.
As shown IN fig. 3, the first transfer circuit 201 includes a first transfer transistor N1, a first switching transistor P3 and a second switching transistor N3, a first voltage feedback node 1N0 and a first boosting node 1N1 for transferring the reference voltage to a first boosting node IN 1. Illustratively, the reference voltage is a ground voltage VSS (e.g., 0 v). The first transfer transistor N1 is an NMOS transistor having a drain terminal connected to the reference voltage, a source terminal connected to the first boost node 1N1, and a gate terminal connected to the first voltage feedback node 1N 0. The first switch transistor P3 is a PMOS transistor, and has a source terminal connected to the working power supply VDD, a drain terminal connected to the first voltage feedback node 1N0, and a gate terminal connected to the first transmission enable signal EN. The second switch transistor N3 is an NMOS transistor, and has a drain connected to the first voltage feedback node 1N0, a source connected to the first boost node, and a gate connected to the first transmission enable signal EN.
The first delay circuit 203 comprises a first inverter 1NV1, a second inverter 1NV2, a NOR gate NOR and a third inverter 1NV3, wherein an input terminal of the first inverter 1NV1 is connected to the first voltage feedback node 1N0, an output terminal of the first inverter 1NV1 is connected to an input terminal of the second inverter 1NV2, an output terminal of the second inverter 1NV2 is connected to a first input terminal of the NOR gate NOR, a second input terminal of the NOR gate NOR is connected to the first lift enable signal 1, an output terminal of the NOR gate NOR is connected to an input terminal of the third inverter 1NV3, and an output terminal of the third inverter 1NV3 outputs the first voltage lift signal KICK 1'. The first lift enable signal 1 is configured to input a low level after the first transmission enable signal EN transitions to a high level. The first lift enable signal 1 may be at a high level or a low level in a case where the first transmission enable signal EN is at a low level.
The first voltage boost circuit 205 includes a first boost capacitor, illustratively a PMOS capacitor P1, with a source-drain short serving as a PMOS capacitor having one end (or gate) connected to the first boost node 1N1 and the other end (or source-drain) connected to the first boost enable signal KICK 1.
In case that the first transfer enable signal EN is at a low level (L or 0), the first switching transistor P3 is turned on, the first voltage feedback node 1N0 is at a high level, the first transfer transistor N1 is turned on, and the second switching transistor N3 is turned off, so that the first boost node is at 0V (or ground voltage), and at this time, the first voltage boost signal KICK 1' is at a high level (e.g., VDD) because the input signal at the first input terminal of the NOR gate NOR is at a high level, no matter what level the first boost enable signal 1 is at.
When the first transmission enable signal EN transits from a low level to a high level and, at the same time, the first lift enable signal 1 transits to a low level, in this case, the first switch transistor P3 is turned off, the second switch transistor N3 is turned on, the first voltage feedback node 1N0 and the first voltage boost node 1N1 are turned on, and the level at the first voltage feedback node 1N0 gradually decreases to transition from VDD to 0V, so that the first transmission transistor N1 is turned off. Then, due to the large capacitance of the first lifting capacitor P1, the first voltage lifting signal KICK 1' gradually changes from a high level (e.g., VDD) to a low level (e.g., 0V), so that the level of the first voltage boosting node 1N1 gradually decreases and changes from 0V to a first-order negative bias (e.g., -0.5V). That is, after the first transmission enable signal EN transits from the low level to the high level, the first voltage boost signal KICK 1' transits from the high level to the low level (e.g., transited from VDD to 0V), and the level of the first boost node 1N1 transits from 0V to the first-order negative bias (e.g., -0.5V).
In this process, since the level transition of the first voltage rising signal KICK1 'is performed after the level transition of the first voltage feedback node 1N0 is completed, there is no case where the first transfer transistor N1 is not turned off yet and the first voltage rising signal KICK 1' has already transitioned, so that the first-order negative bias voltage is closer to an ideal value (e.g., -0.5V, which can actually reach-0.49V).
Further, the second transmission circuit 202 includes a second transmission transistor N2, a third switching transistor N4, a fourth switching transistor N5, a fifth switching transistor P4, a sixth switching transistor P5, a second voltage feedback node 1N2, a second voltage feedback node 1N3, and a second boosting node 1N4, for transmitting the signal of the first boosting node 1N1 to the second boosting node 1N 4.
Illustratively, the second pass transistor N2 is an NMOS transistor having a source terminal connected to the first boost node 1N1, a gate terminal connected to the second voltage feedback node 1N2, and a drain terminal connected to the second boost node 1N 4. The third switching transistor N4 is an NMOS transistor, and has a source terminal connected to the first boost node 1N1, a drain terminal connected to the third voltage feedback node 1N3, and a gate terminal connected to the second transmission enable signal 1N 2. The fourth switching transistor N5 is an NMOS transistor, and has a source terminal connected to the second voltage feedback node 1N2, a drain terminal connected to the second boosting node 1N4, and a gate terminal connected to the third voltage feedback node 1N 3. The fifth switching transistor P4 is a PMOS transistor, and has a source terminal connected to the working power supply VDD, a drain terminal connected to the third voltage feedback node 1N3, and a gate terminal connected to the second transmission enable signal EN 2. The sixth switching transistor P5 is a PMOS transistor, and has a source terminal connected to the operating power supply VDD, a drain terminal connected to the second voltage feedback node 1N2, and a gate terminal connected to the third transmission enable signal EN2 b. Wherein the second transfer enable signal EN2 and the third transfer enable signal EN2b are opposite in level (or opposite in phase).
The second delay circuit 204 includes a fourth inverter 1NV4, a fifth inverter 1NV5, and a NAND gate NAND, wherein an input of the fourth inverter 1NV4 is connected to the third voltage feedback node 1N3, an output of the fourth inverter is connected to an input of the fifth inverter 1NV5, an output of the fifth inverter 1NV5 is connected to a first input of the NAND gate NAND, a second input of the NAND gate NAND is connected to the second lift enable signal 2, an output of the NAND gate outputs the second voltage lift signal KICK 2', and the second lift enable signal 2 is configured to input a high level after the first transmission enable signal EN is transitioned to the high level and a delay is set (implemented by the delay circuit 207). The second lift enable signal 2 may be at a high level or a low level in the case of making the first transmission enable signal EN at a low level.
The second voltage boost circuit 206 includes a second boost capacitor P2, illustratively a PMOS capacitor with source-drain short functioning as a capacitor, having one end (or gate) connected to the second boost node and the other end (or source-drain) connected to the second voltage boost signal KICK 2'.
In case that the first transmission enable signal EN is low (L or 0), the second transmission enable signal EN2 is high level, the third transmission enable signal EN2b is low level, the fifth switching transistor P4 is turned off, the sixth switching transistor P5 is turned on, the third switching transistor N4 is turned on, the fourth switching transistor N5 is turned off, and the second voltage feedback node 1N2 is VDD level. The second voltage feedback node 1N3 and the first voltage boost node 1N1 are at the same level, VSS, and no matter what the level of the second boost enable signal 2 is, the output terminal is always at high level (i.e. the second voltage boost signal buck 2' is at high level) because the third simultaneous second boost enable signal buck 2 is at high level (e.g. VDD) and at low level because the nand gate first input signal is at low level.
When the first transfer enable signal EN is high, the level of the first pumping node 1N1 is changed from 0V (i.e., VSS) to the first-order negative bias (e.g., -0.5V) as described above, and the third voltage feedback node 1N3 is turned on with the first pumping node 1N1, thereby also changing from 0V (i.e., VSS) to the first-order negative bias (e.g., -0.5V). After the delay time is set (by the delay circuit 207), that is, after the level of the first boosting node 1N1 is changed to the first-order negative bias (for example, -0.5V), the level of the second transfer enable signal EN2, the third transfer enable signal EN2b, and the second lift enable signal 2 is changed by the set delay time, even if the second transfer enable signal EN2 is changed from high level to low level, the third transfer enable signal EN2b is changed from low level to high level, the second lift enable signal 2 is inputted to high level, so that the fifth switching transistor P4 is turned on, the sixth switching transistor P5 is turned off, the third switching transistor N4 is turned off, the level of the third voltage feedback node 1N3 is increased from low (-0.5V) to VDD, the fourth switching transistor N5 is turned on, then the level of the second voltage feedback node 1N2 is decreased from high, and the second transfer transistor N2 is turned off, then, the level of the second pumping node 1N4 gradually decreases, and changes from the first-order negative bias (-0.5V) to the second-order negative bias (e.g., -1.0V). That is, after the first transmission enable signal EN2 is transited to the high level for a period of time, during the transition of the second voltage rising signal KICK 2' to the low level (for example, from VDD to 0V), the level of the second voltage rising node 1N4 is transited from the first-order negative bias to the second-order negative bias (for example, -1.0V), so that the output terminal BOOST outputs the target negative bias.
In this process, since the level transition of the second voltage rising signal KICK2 'is performed after the level transition of the third voltage feedback node 1N1 is completed, there is no case where the second pass transistor N2 is not turned off yet and the second voltage rising signal KICK 2' has already transitioned, so that the second-order negative bias voltage is closer to an ideal value (e.g., the ideal value is-1.0V, which can actually reach-0.98V).
Fig. 4 is a diagram showing simulation results of the negative boost circuit shown in fig. 3. As shown in fig. 4, which shows the BOOST voltage curve 1 of the circuit shown in fig. 1, the BOOST voltage curve 2 of the circuit shown in fig. 3, the voltage node 1N0, 1N1 and the voltage curves of the bias signals KCIK1 'and KICK 2' in the circuit shown in fig. 3. As can be seen from fig. 4, in the negative boost circuit of the present embodiment, there is a flexible delay (flexbledelay) between the voltage boost signal (KCIK1 ', KICK 2') and the voltage feedback point signal (1N0, 1N3), so that the level transition of the voltage boost signal always occurs after the pass transistor is turned off, thereby improving the power efficiency, and making the target bias closer to the ideal value, for example, in the present embodiment, the generated negative bias is-0.981V, while the current negative bias generated by the negative bias circuit is-0.907V, which improves the efficiency by about 10%.
Furthermore, in the present embodiment, the delay between the voltage boost signal (KCIK1 ', KICK 2') and the voltage feedback point signal (1N0, 1N3) is determined by the first delay circuit and the second delay circuit, for example, based on the number of inverters in the circuit, which can be set by those skilled in the art as needed, conveniently and flexibly.
Example two
The invention also provides a semiconductor device which comprises a negative booster circuit and a storage unit connected with the negative booster circuit. Exemplarily, in the present embodiment, the memory cell is a PMOS type memory cell.
The negative booster circuit comprises a first transmission circuit, a first delay circuit and a first voltage boosting circuit. The first transmission circuit is configured to transmit a reference signal to a first boosting node, the first delay circuit is configured to generate a first voltage boosting signal based on a feedback signal of a voltage feedback node of the first transmission circuit and a first boosting enabling signal, and the first voltage boosting circuit is configured to convert the voltage of the first boosting node into a first-order negative bias under the action of the first voltage boosting signal. Wherein the first delay circuit is configured to have a first predetermined delay between the feedback signal of the first transmission circuit and the first voltage boost signal, such that the first voltage boost circuit does not transition the voltage of the first boost node to a first-order negative bias voltage until after the connection between the first transmission circuit and the reference signal is turned off.
Furthermore, the negative boost circuit of the invention further comprises a second transmission circuit, a second delay circuit and a second voltage boost circuit. Wherein the second transmission circuit is configured to transmit the signal of the first boost node to the second boost node; the second delay circuit is configured to generate a second voltage boost signal based on a feedback signal of a voltage feedback node of the second transmission circuit and the second boost enable signal; the second voltage raising circuit is configured to convert the voltage of the second boost node from the first-order negative bias to a second-order negative bias under the action of the second voltage raising signal. Wherein the second delay circuit is configured to have a second predetermined delay between the feedback signal of the second transmission circuit and the second voltage boost signal, so that the second voltage boost circuit converts the voltage of the second boost node into a second-order negative bias voltage after the connection between the second transmission circuit and the first boost node is turned off.
The semiconductor device of the present embodiment has a more efficient negative boost circuit, and thus the read operation of the device is more efficient.
EXAMPLE III
Still another embodiment of the present invention provides an electronic apparatus including the above semiconductor device and an electronic component connected to the semiconductor device. The semiconductor device comprises the negative booster circuit and a storage unit connected with the negative booster circuit. Exemplarily, in the present embodiment, the memory cell is a PMOS type memory cell.
The electronic component may be any electronic component such as a discrete device and an integrated circuit.
The electronic device of this embodiment may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice pen, an MP3, an MP4, and a PSP, and may also be any intermediate product including the semiconductor device.
Fig. 5 shows an example of a mobile phone. The exterior of the cellular phone 500 is provided with a display portion 502, operation buttons 503, an external connection port 504, a speaker 505, a microphone 506, and the like, which are included in a housing 501.
The electronic device provided by the embodiment of the invention has the semiconductor device with the more efficient negative booster circuit, so that the reading operation of the device is more efficient. The electronic device also has similar advantages.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (11)
1. A negative boost circuit for generating a negative bias voltage, comprising:
a first transmission circuit configured to transmit a reference signal to a first boost node, the first transmission circuit including a first transmission transistor, a first voltage feedback node, a first switch transistor, and a second switch transistor, a source terminal of the first transmission transistor being connected to the reference signal, a drain terminal of the first transmission transistor being connected to the first boost node, a gate terminal of the first transmission transistor being connected to the first voltage feedback node, a source terminal of the first switch transistor being connected to a working power supply, a drain terminal of the first switch transistor being connected to the first voltage feedback node, a gate terminal of the first switch transistor being connected to a first transmission enable signal, a source terminal of the second switch transistor being connected to the first voltage feedback node, a drain terminal of the second switch transistor being connected to the first boost node, the gate terminal of the second switch transistor is connected with the first transmission enabling signal, the first transmission enabling signal is configured to enable the first switch transistor to be turned off, and the second switch transistor to be turned on;
a first delay circuit configured to generate a first voltage boost signal based on a feedback signal of the first transmission circuit and a first boost enable signal;
a first voltage boost circuit configured to convert a voltage of the first boost node to a first-order negative bias voltage based on the first voltage boost signal,
wherein the first delay circuit is configured to have a first predetermined delay between the feedback signal of the first transmission circuit and the first voltage rise signal.
2. The negative boost circuit of claim 1, wherein said first boost circuit includes a first boost capacitor having a first terminal coupled to said first boost node and a second terminal coupled to said first voltage boost signal,
the first delay circuit is configured to transition the first voltage boost signal from a high level to a low level after the first pass transistor is turned off to transition the voltage of the first boost node to a first-order negative bias.
3. The negative boost circuit of claim 2, wherein the first delay circuit comprises a first inverter, a second inverter, a nor gate and a third inverter, wherein an input of the first inverter is connected to the first voltage feedback node, an output of the first inverter is connected to an input of the second inverter, an output of the second inverter is connected to a first input of the nor gate, a second input of the nor gate is connected to the first boost enable signal, an output of the nor gate is connected to an input of the third inverter, and an output of the third inverter outputs the first voltage boost signal.
4. The negative boost circuit of any one of claims 1-3, further comprising:
a second transmission circuit configured to transmit a signal of the first boost node to a second boost node;
a second delay circuit configured to generate a second voltage boost signal based on a feedback signal of the second transmission circuit and a second boost enable signal;
a second voltage boost circuit configured to convert the voltage of the second boost node from the first-order negative bias to a second-order negative bias based on the second voltage boost signal,
wherein the second delay circuit is configured to cause a second predetermined delay between the feedback signal of the second transmission circuit and the second voltage boost signal.
5. The negative boost circuit of claim 4, wherein the second pass circuit comprises a second pass transistor, a third switching transistor, a fourth switching transistor, a second voltage feedback node, and a third voltage feedback node,
a source terminal of the second transmission transistor is connected with the first boost node, a drain terminal of the second transmission transistor is connected with the second boost node, a gate terminal of the second transmission transistor is connected with the second voltage feedback node,
a source end of the third switching transistor is connected with the first boost node, a drain end of the third switching transistor is connected with the third voltage feedback node, a gate end of the third switching transistor is connected with a second transmission enable signal,
a source end of the fourth switching transistor is connected with the second voltage feedback node, a drain end of the fourth switching transistor is connected with the second boost node, a gate end of the fourth switching transistor is connected with the third voltage feedback node,
the second pass enable signal is configured to turn off the second pass transistor.
6. The negative boost circuit of claim 5, wherein the second transmission circuit further comprises a fifth switching transistor and a sixth switching transistor,
a source end of the fifth switching transistor is connected with a working power supply, a drain end of the fifth switching transistor is connected with the third voltage feedback node, a gate end of the fifth switching transistor is connected with the second transmission enabling signal,
a source end of the sixth switching transistor is connected with a working power supply, a drain end of the sixth switching transistor is connected with the second voltage feedback node, a gate end of the sixth switching transistor is connected with a third transmission enabling signal,
the second transmission enable signal and the third transmission enable signal are opposite in level.
7. The negative boost circuit of claim 6, wherein said second boost circuit comprises a second boost capacitor having a first terminal coupled to said second boost node and a second terminal coupled to said second voltage boost signal,
the second delay circuit is configured to transition the second voltage boost signal from a high level to a low level after the second pass transistor is turned off, so that the voltage of the second boost node is converted to a second-order negative bias.
8. The negative boost circuit of claim 7, wherein said second delay circuit comprises a fourth inverter, a fifth inverter and a nand gate, wherein an input of said fourth inverter is connected to said third voltage feedback node, an output of said fourth inverter is connected to an input of said fifth inverter, an output of said fifth inverter is connected to a first input of said nand gate, a second input of said nand gate is connected to said second boost enable signal, and an output of said nand gate outputs said second voltage boost signal.
9. The negative boost circuit of claim 8, further comprising a third delay circuit configured to have a set delay between the first boost enable signal and the second boost enable signal.
10. A semiconductor device comprising the negative boost circuit according to any one of claims 1 to 9 and a memory cell connected to the negative boost circuit.
11. An electronic device comprising the semiconductor device according to claim 10 and an electronic component connected to the semiconductor device.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5010259A (en) * | 1988-12-28 | 1991-04-23 | Mitsubishi Denki Kabushiki Kaisha | Voltage boosting circuit and operating method thereof |
| US5469110A (en) * | 1994-06-27 | 1995-11-21 | Industrial Technology Research Institute | Charge pumping circuit using non-overlapping clock control |
| CN101034847A (en) * | 2006-03-07 | 2007-09-12 | 罗姆股份有限公司 | Voltage step-up circuit and electric appliance therewith |
| KR20090071750A (en) * | 2007-12-28 | 2009-07-02 | 주식회사 하이닉스반도체 | Pump circuit of semiconductor memory apparatus and pumping method using the same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3702166B2 (en) * | 2000-02-04 | 2005-10-05 | 三洋電機株式会社 | Charge pump circuit |
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2016
- 2016-06-07 CN CN201610402677.7A patent/CN107481745B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5010259A (en) * | 1988-12-28 | 1991-04-23 | Mitsubishi Denki Kabushiki Kaisha | Voltage boosting circuit and operating method thereof |
| US5469110A (en) * | 1994-06-27 | 1995-11-21 | Industrial Technology Research Institute | Charge pumping circuit using non-overlapping clock control |
| CN101034847A (en) * | 2006-03-07 | 2007-09-12 | 罗姆股份有限公司 | Voltage step-up circuit and electric appliance therewith |
| KR20090071750A (en) * | 2007-12-28 | 2009-07-02 | 주식회사 하이닉스반도체 | Pump circuit of semiconductor memory apparatus and pumping method using the same |
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