CN114333935A

CN114333935A - Memory device, system, and method of operating a memory device

Info

Publication number: CN114333935A
Application number: CN202111672655.XA
Authority: CN
Inventors: 贾建权; 蒋颂敏; 罗哲; 闵园园; 崔莹; 李姗; 张安; 李达; 刘红涛; 靳磊
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-12-31
Filing date: 2021-12-31
Publication date: 2022-04-12

Abstract

The application discloses a memory device, a system and an operation method of the memory device, belonging to the technical field of storage, applying a first voltage to a first end of the memory string, applying a second voltage less than the first voltage to a word line coupled to a first memory cell of the memory string, since the voltage difference between the first voltage and the second voltage is greater than or equal to the tunneling voltage of the first memory cell, the invalid data it stores can be erased and, in addition, a third voltage less than the first voltage is applied to the word line to which the second memory cell of the memory string is coupled, since the voltage difference between the first voltage and the third voltage is less than the tunneling voltage of the second memory cell, to protect the valid data stored therein from being erased, furthermore, effective data does not need to be migrated, so that the time for migrating the effective data back and forth is saved, and the erasing efficiency of the storage block is improved.

Description

Memory device, system, and method of operating a memory device

Technical Field

The present application relates to the field of memory technologies, and in particular, to a memory device, a system, and a method for operating the memory device.

Background

With the development of semiconductor processes, three-dimensional (3-dimensional, 3D) memory devices have been widely used. In the related art, a storage block of a three-dimensional storage device stores some data, such as photos, and when a photo in the storage block is to be deleted, the three-dimensional storage device erases the corresponding data in the storage block. The data to be erased in the storage block is invalid data, and other data to be reserved is valid data.

In the data erasing process, the three-dimensional storage device firstly migrates the effective data in the storage block to a selected reserved space block (over provisioning block), then performs data erasing on the storage block, and finally migrates the effective data in the reserved space block back to the original storage position.

In the erasing manner using the memory block as a unit, the effective data in the memory block needs to be migrated back and forth, so that the time length for erasing the data is increased, and the data erasing efficiency is reduced.

Disclosure of Invention

Embodiments of the present application provide a memory device, a system, and a method for operating a memory device, which can improve data erasure efficiency of the memory device. The technical scheme is as follows:

in a first aspect, a memory device is provided, the memory device comprising a memory array and peripheral circuitry;

the memory array comprises a memory string and a plurality of word lines, wherein the memory string comprises at least one first memory cell and at least one second memory cell, the first memory cell is a memory cell in the memory string, invalid data are stored in the memory string, and the second memory cell is a memory cell in the memory string, valid data are stored in the memory string;

the plurality of word lines are respectively coupled to the storage array;

the peripheral circuitry is coupled to the plurality of word lines and configured to:

applying a first voltage to a first end of the memory string, the first end being one of coupled to a bit line contact corresponding to the memory string or coupled to a source contact corresponding to the memory string;

applying a second voltage to a word line to which the first memory cell is coupled, the second voltage being less than the first voltage, and a voltage difference between the first voltage and the second voltage being greater than or equal to a first tunneling voltage;

configuring a third voltage for a word line to which the second memory cell is coupled, the third voltage being less than the first voltage, and a voltage difference between the first voltage and the third voltage being less than a second tunneling voltage.

In one possible implementation, the peripheral circuitry is further configured to:

applying the third voltage to the coupled word line of the second memory cell.

floating the word line to which the second memory cell is coupled.

In a possible embodiment, the storage string further comprises at least one first selection pipe, the first selection pipe being close to the first end; the peripheral circuitry is further configured to:

applying a fourth voltage to a select line to which the first select tube is coupled, the fourth voltage being less than the first voltage, and a voltage difference between the first voltage and the fourth voltage satisfying a voltage difference condition that band-to-band tunneling occurs.

In one possible implementation, the first end is coupled to a bit line contact corresponding to the memory string, the bit line contact is an N-type doped conductive structure, and the doping concentration of the impurity is greater than or equal to the first concentration.

In one possible embodiment, the first concentration is 5 x 10^ 8.

In one possible implementation, the first end is coupled to a corresponding source contact of the memory string.

In one possible implementation, the memory string further includes at least one first selection transistor, the first selection transistor is close to the first end, the first end is coupled to a source contact corresponding to the memory string, and the source contact is a P-type doped conductive structure; the peripheral circuitry is further configured to:

applying a fifth voltage to a select line to which the first select transistor is coupled, the fifth voltage being less than the first voltage.

In one possible embodiment, the first storage unit is located near the first end and the second storage unit is located far from the first end.

In a possible embodiment, the storage string further comprises at least one second selection pipe, said at least one second selection pipe being remote from the first end; the peripheral circuitry is further configured to:

configuring a sixth voltage for a select line to which the second select tube is coupled, the sixth voltage being less than the first voltage, and a voltage difference between the first voltage and the sixth voltage being less than a third tunneling voltage.

In a possible embodiment, the first storage unit is far away from the first end, and the second storage unit is close to the first end; the peripheral circuitry is further configured to:

applying an eighth voltage to the word line to which the second memory cell is coupled before a channel voltage of the memory string reaches a seventh voltage, the seventh voltage being greater than the eighth voltage and less than or equal to the first voltage, a voltage difference between the seventh voltage and the eighth voltage being less than the second tunneling voltage;

the step of configuring the word line to which the second memory cell is coupled with a third voltage is performed after the channel voltage of the memory string reaches the seventh voltage.

before a channel voltage of the memory string reaches the seventh voltage, applying a ninth voltage to a select line to which the second select transistor is coupled, the seventh voltage being greater than the ninth voltage and less than or equal to the first voltage, a voltage difference between the seventh voltage and the ninth voltage being less than a third tunneling voltage;

configuring a sixth voltage for a select line coupled to the second select transistor after a channel voltage of the memory string reaches the seventh voltage, the sixth voltage being less than the first voltage, and a voltage difference between the first voltage and the sixth voltage being less than a third tunneling voltage.

In a second aspect, a system is provided that includes a memory device configured to store data, the memory device including a memory array and peripheral circuitry;

the plurality of word lines are respectively coupled to a plurality of memory cells of the memory string;

the peripheral circuitry is coupled to the storage array and configured to:

applying the third voltage to the coupled word line of the second memory cell.

floating the word line to which the second memory cell is coupled.

In one possible embodiment, the first concentration is 5 x 10^ 8.

In one possible embodiment, the system further comprises a host and a memory controller;

the host is configured to send data to or receive data from the storage device;

the memory controller is coupled to the host and the storage device and is configured to control the storage device.

In a third aspect, a method of operating a memory device is provided, the memory device including a memory array including a memory string and a plurality of word lines, the memory string including at least one first memory cell and at least one second memory cell, the first memory cell being a memory cell in the memory string in which invalid data is stored, the second memory cell being a memory cell in the memory string in which valid data is stored, the plurality of word lines being respectively coupled to the plurality of memory cells of the memory string; the method comprises the following steps:

In one possible implementation, the configuring the third voltage for the word line coupled to the second memory cell includes:

applying the third voltage to the coupled word line of the second memory cell.

floating the word line to which the second memory cell is coupled.

In a possible embodiment, the storage string further comprises at least one first selection pipe, the first selection pipe being close to the first end; the method further comprises the following steps:

In one possible embodiment, the first concentration is 5 x 10^ 8.

In one possible implementation, the memory string further includes at least one first selection transistor, the first selection transistor is close to the first end, the first end is coupled to a source contact corresponding to the memory string, and the source contact is a P-type doped conductive structure; the method further comprises the following steps:

In a possible embodiment, the storage string further comprises at least one second selection pipe, said at least one second selection pipe being remote from the first end; the method further comprises the following steps:

In a possible embodiment, the first storage unit is far away from the first end, and the second storage unit is close to the first end; the method further comprises the following steps:

According to the technical scheme, in the process of erasing the storage block, a first voltage is applied to a first end of the storage string, a second voltage smaller than the first voltage is applied to a word line coupled to a first storage unit of the storage string, invalid data stored in the storage string can be erased due to the fact that the voltage difference between the first voltage and the second voltage is larger than or equal to the tunneling voltage of the first storage unit, in addition, a third voltage smaller than the first voltage is configured to the word line coupled to a second storage unit of the storage string, and the voltage difference between the first voltage and the third voltage is smaller than the tunneling voltage of the second storage unit, so that the stored valid data are protected from being erased, the valid data do not need to be migrated, the time for migrating the valid data back and forth is saved, and the erasing efficiency of the storage block is improved.

Drawings

FIG. 1 is a schematic diagram of a system provided by an embodiment of the present application;

FIG. 2 is a schematic diagram of a memory card according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of an example solid state drive provided by an embodiment of the present application;

FIG. 4 is a block diagram of a memory device provided by an embodiment of the present application;

FIG. 5 is a schematic structural diagram of a memory device according to an embodiment of the present application;

FIG. 6 is a schematic structural diagram of a memory block according to an embodiment of the present disclosure;

FIG. 7 is a cross-sectional side view of a storage string provided by an embodiment of the present application;

FIG. 8 is a schematic diagram of a peripheral circuit provided by an embodiment of the present application;

FIG. 9 is a flow chart of a method of operating a memory device according to an embodiment of the present application;

FIG. 10 is a schematic diagram illustrating a distribution of memory cells in a memory string according to an embodiment of the present application;

FIG. 11 is a schematic diagram of voltage waveforms during data erasing under condition 1.1 according to an embodiment of the present application;

FIG. 12 is a schematic diagram of voltage waveforms during data erasing under condition 1.2 according to an embodiment of the present application;

FIG. 13 is a schematic diagram of voltage waveforms during data erasing under condition 2.1.1 according to an embodiment of the present application;

FIG. 14 is a schematic diagram of voltage waveforms during data erasing under condition 2.1.2 according to an embodiment of the present application;

FIG. 15 is a schematic diagram of voltage waveforms during data erasing under condition 2.2.1 according to an embodiment of the present application;

fig. 16 is a schematic voltage waveform during data erasing under 2.2.2 according to the embodiment of the present application;

fig. 17 is a flowchart of an operation method of another memory device according to an embodiment of the present application:

fig. 18 is a schematic voltage waveform during data erasing in case 3 according to an embodiment of the present application.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

The terms "first," "second," and the like, in this application, are used for distinguishing between similar items and items that have substantially the same function or similar functionality, and it should be understood that "first," "second," and "nth" do not have any logical or temporal dependency, nor do they define a quantity or order of execution. It will be further understood that, although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by these terms.

These terms are only used to distinguish one element from another. For example, a first element can be termed a second element, and, similarly, a second element can also be termed a first element, without departing from the scope of various examples. The first element and the second element may both be elements, and in some cases, may be separate and distinct elements.

For example, at least one element may be an integer number of elements equal to or greater than one, such as one element, two elements, three elements, and the like. And at least two means two or more, for example, at least two elements may be any integer number of two or more, such as two elements, three elements, and the like.

Fig. 1 is a schematic diagram of a system provided by an embodiment of the present application, and system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having storage therein.

As shown in fig. 1, the system 100 includes a host 101 and a storage subsystem 102, and the host 101 may be a processor (e.g., a Central Processing Unit (CPU)) or a system on chip (SoC) (e.g., an Application Processor (AP)) of an electronic device. The host 101 may be configured to send data to the storage device 103. Alternatively, the host 101 may be configured to receive data from the storage device 103.

The memory subsystem 102 includes one or more memory devices 103 and a memory controller 104. Among other things, the memory device 103 may be any of the memories disclosed in the present disclosure. Optionally, the memory device 103 is a NAND flash (NAND flash) memory device. A NAND flash memory device, such as a three-dimensional (3D) NAND flash memory device.

According to some embodiments, the memory controller 104 is coupled to the host 101 and the memory device 103, and is configured to control the memory device 103. The memory controller 104 may manage data stored in the storage device 103 and communicate with the host 101.

In one possible implementation, the memory controller 104 is designed for operation in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other medium for use in electronic devices such as personal computers, digital cameras, mobile phones, and so forth.

In one possible implementation, the memory controller 104 is designed for operation in a high duty cycle environment Solid State Drive (SSD) or embedded multimedia card (eMMC) that serves as a data storage and enterprise storage array for mobile devices such as smart phones, tablet computers, laptop computers, and the like.

The memory controller 104 may be configured to control operations of the memory device 103, such as read, erase, and program operations. The memory controller 104 may also be configured to manage various functions with respect to data stored or to be stored in the memory device 103, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like. In one possible implementation, the memory controller 104 is further configured to process an Error Correction Code (ECC) with respect to data read from or written to the memory device 103.

The memory controller 104 may also perform any other suitable functions, such as formatting the memory device 103. The memory controller 104 may communicate with external devices (e.g., the host 101) according to a particular communication protocol. For example, the memory controller 104 may communicate with the external device via at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system small interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and so forth.

The memory controller 104 and the one or more memory devices 103 may be integrated into various types of memory devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the system 100 may be implemented and packaged into different types of end electronic products.

Fig. 2 is a schematic diagram of a memory card provided by an embodiment of the present application, and as shown in fig. 2, the memory controller 104 and the single memory device 103 may be integrated into the memory card 200. The memory card 200 may include a PC card (PCMCIA), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, and the like. Memory card 200 may also include a memory card connector 201 that couples memory card 200 with a host (e.g., host 101 in FIG. 11).

Fig. 3 is a schematic diagram of a solid state drive provided by an embodiment of the present application, and as shown in fig. 3, the memory controller 104 and the plurality of memory devices 103 may be integrated into a Solid State Drive (SSD) 300. Solid state drive 300 may also include solid state drive connector 310 that couples solid state drive 301 with a host (e.g., host 101 in fig. 1). In one possible implementation, the storage capacity and/or operating speed of the solid state drive 310 is greater than the storage capacity and/or operating speed of the memory card 200.

Fig. 4 is a block diagram of a memory device 103 according to an embodiment of the present application, where the memory device 103 includes a memory array 301 and a peripheral circuit 302, where the memory array 301 is used for storing data, and the peripheral circuit 302 is used for controlling the memory array 301 to implement an operation method of the memory device provided below.

To further illustrate the internal structure of the memory array 301, reference is made to fig. 5, which is a schematic structural diagram of a memory device provided in the embodiments of the present application. As shown in fig. 5, the memory array 301 includes a plurality of memory strings 11, the plurality of memory strings 11 are arranged in an array over a substrate (not shown) of the memory array 301, and each memory string 11 extends vertically over the substrate.

Each memory string 11 includes a plurality of memory cells 111 connected in series, and the plurality of memory cells 111 are vertically stacked above the memory array 301 substrate. In different memory strings 11, the memory cells at the same height or similar heights from the substrate carrying surface are in the same layer.

The memory cell 111 includes a source S, a drain D, a Control Gate (CG), and a memory layer, and the control gate of the memory cell 111 is also referred to as a gate G. The storage layer is used to store electrons, and the number of electrons stored in the storage layer determines the data stored in the storage unit, so that the storage unit 11 has a function of storing data. Alternatively, the memory cell 111 includes a floating gate field effect transistor or a charge trap (charge trap) type field effect transistor. A floating gate fet is a special fet that includes a source, a drain, a control gate, and a Floating Gate (FG), which may also be referred to as a floating gate for short, and which is a cell for storing electrons and serves as a storage layer for memory cell 111. The charge trap type field effect transistor, which may also be referred to as a charge trap device, includes a source electrode, a drain electrode, a control gate, and a charge trap layer, which is a unit for storing electrons and serves as a storage layer of the memory cell 111.

In some embodiments, each memory cell 111 is a single level cell having two possible memory states and therefore can store one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range.

In some embodiments, each memory cell 111 is a cell capable of storing more than a single bit of data in more than four memory states. For example, two bits per cell (also referred to as a multilevel cell), three bits per cell (also referred to as a tertiary cell), or four bits per cell (also referred to as a quaternary cell) may be stored. Each MLC may be programmed to assume a range of possible nominal stored values. In one example, if each MLC stores two bits of data, the MLC may be programmed to assume one of three possible programming levels from the erased state by writing one of three possible nominal storage values to the cell. The fourth nominal storage value may be used for the erased state.

With continued reference to fig. 5, a plurality of memory cells 111 at the same level in the plurality of memory strings 11 share the same Word Line (WL).

Each memory string 11 also includes an upper select pipe 112 and a lower select pipe 113, the upper select pipe 112 and the lower select pipe 113 being used to activate the selected memory string when erasing, programming the memory cells. The upper select tubes 112, which may also be referred to as Top Select Gates (TSG), have at least one upper select tube 112 in each memory string 11 vertically stacked above the memory cells 111 in the memory string 11. The lower select transistors 113 may also be referred to as Bottom Select Gates (BSG), with at least one lower select transistor 113 in each memory string 11. Vertically stacked below the memory cells 111 and above the substrate in the memory string 11.

The upper select transistors in the same layer of the memory strings 11 share the same Drain Select Line (DSL). The lower select transistors in the same layer of the memory strings 11 share the same Source Select Line (SSL). In some embodiments, each memory string 11 is configured to store data by applying a select voltage (e.g., a threshold voltage above the TSG) or a deselect voltage (e.g., 0V) to the gate of the corresponding TSG via one or more DSLs. And/or, in some embodiments, each memory string 11 is configured to be selected or deselected by applying a select voltage (e.g., above a threshold voltage of a BSG) or a deselect voltage (e.g., 0V) to the gate of the corresponding BSG via one or more SSLs.

Each memory string 11 also includes virtual memory cells (dummy cells) 114, at least one of the virtual cells 114 on each memory string 11. A plurality of dummy memory cells 114 in the same layer in the plurality of memory strings 11 share the same Dummy Word Line (DWL).

One end of each memory string 11 is directly or indirectly connected to a Bit Line (BL), and the other end of each memory string 11 is indirectly connected to a Source Line (SL). One end of the memory string 11 directly or indirectly connected to the bit line may be referred to as a drain end, and one end indirectly connected to the source line may be referred to as a source end.

All memory strings 11 in the memory array 302 that share a group of word lines are referred to as a memory block (block) 11A. The memory block 11A is the smallest physically addressed unit of data erasure. To further embody the structure of the memory block 11A, referring to the schematic structural diagram of a memory block provided in the embodiment of the present application shown in fig. 6, for example, the memory block 11A shown in fig. 5 includes n memory strings 11, each memory string 11 includes m memory cells 111, m WL arranged along the Z direction: WL _1 to WL _ m are connected to the memory cells 111 in the same layer. J DSLs arranged along direction Y: DSL _1 to DSL _ j are respectively connected with a layer of TSG, j SSLs arranged along the direction Y: SSL _0 to SSL _ j are respectively connected with a layer of BSG. N BLs arranged along direction X: BL _1 to BL _ n. The memory strings 11 share the same source line contact connected to the source line, thereby realizing that the memory strings 11 share the same source line. The source line contact can also be referred to as the Array Common Source (ACS). A plurality of dummy memory cells in the same layer in the plurality of memory strings 11 share the same dummy word line DWL. Wherein n and m are both integers greater than 1, i in fig. 6 is an integer greater than 1 and less than m, and j is an integer greater than 1 and less than n.

It should be appreciated that in some examples, the erase operation may be performed at a half block level, at a quarter block level, or at any suitable fraction of a number of blocks or blocks.

The memory string 11 further includes a channel, and referring to a cross-sectional side view of a memory string provided by the embodiment of the present application shown in fig. 7, the memory string 11 further includes a channel 115 vertically passing through the memory string 11, the channels of the devices in the memory string 11 are connected in series to form the channel 115, and the control lines to which the devices are connected are formed at the periphery of the channel 115, as shown in fig. 7. One end of the channel 115 is connected to one bit line through a bit line contact 116 and the other end is coupled to a source contact 304 in the substrate 303, the source contact 304 being coupled to a source line contact. In some embodiments, the source contact 304 is part of the substrate 303, as shown in fig. 7. In yet another possible implementation, the source contact 304 serves as the substrate of the memory device.

Each device in the memory string 11 includes a memory cell 111, an upper selection pipe 112, a lower selection pipe 113, and a dummy memory cell 114, a control line of the memory cell 111 is a word line to which the memory cell 111 is connected, a control line of the upper selection pipe 112 is a drain selection line to which the upper selection pipe 112 is connected, a control line of the lower selection pipe 113 is a source selection line to which the lower selection pipe 113 is connected, and a control line of the dummy memory cell 114 is a dummy word line to which the dummy cell 114 is connected. And the peripheral circuit 302 is used for supplying appropriate voltages to control lines and the like of each device in the memory string of the memory array 301 when data is read, written or erased from the memory array 301, so as to complete data reading, writing or erasing.

Referring back to FIG. 5, peripheral circuitry 302 may be coupled to memory array 301 through bitlines, wordlines, source lines, DSLs, SSL lines, and DWLs. Peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory array 301 by applying and sensing voltage and/or current signals to and from each target memory cell via bit lines, word lines, source lines, DSL, SSL lines, and DWL.

The peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, fig. 8 is a schematic diagram of a peripheral circuit provided in the embodiment of the present application. As with the peripheral circuitry 302 shown in fig. 8, the peripheral circuitry 302 includes page buffers/sense amplifiers 804, column decoders/Bit Line (BL) drivers 806, row decoders/Word Line (WL) drivers 808, voltage generators 810, control logic 812, registers 814, an interface 816, and a data bus 818. In some examples, additional peripheral circuitry not shown in fig. 8 is also included. The page buffer/sense amplifier 804 may be configured to read data from the memory array 301 and program (write) data to the memory array 301 according to control signals from the control logic unit 812. In one example, the page buffer/sense amplifier 804 can store a page of program data (write data) to be programmed into a page of the memory array 301. In another example, page buffer/sense amplifier 804 can perform a program verify operation to ensure that data has been properly programmed into memory cells 111 coupled to the selected word line. In yet another example, page buffer/sense amplifier 804 can also sense low power signals from bit lines representing data bits stored in memory cells 111 and amplify small voltage swings to recognizable logic levels in a read operation. The column decoder/bit line driver 806 may be configured to be controlled by the control logic unit 812 and select one or more memory strings 11 by applying the bit line voltage generated from the voltage generator 810.

The row decoder/word line drivers 808 may be configured to be driven byControl logic 812 controls and selects/deselects word lines 1620 of memory block 11A of memory array 301 for selection/deselection of block 1615. The row decoder/word line drivers 808 may also be configured to use the word line voltage (V) generated from the voltage generator 810_WL) To drive the word lines. In some embodiments, the row decoder/wordline driver 808 may also select/deselect and drive DSL and SSL. As described in detail below, the row decoder/wordline driver 808 is configured to perform an erase operation on the memory cells 111 coupled to the selected wordline(s). The voltage generator 810 may be configured to be controlled by the control logic unit 812 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verify voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory array 301.

The control logic unit 812 may be coupled to each of the peripheral circuits 302 described above and configured to control the operation of each of the peripheral circuits 302. Registers 814 may be coupled to control logic unit 812 and include status, command, and address registers for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit 302. Interface 816 may be coupled to control logic 812 and act as a control buffer to buffer and relay control commands received from a host (not shown) to control logic 812 and to buffer and relay status information received from control logic 812 to the host. The interface 816 may also be coupled to the column decoder/bit line drivers 806 via a data bus 1618, and acts as a data I/O interface and data buffer to buffer data and relay it to the memory array 301 or to relay or buffer data from the memory array 301.

The principle of erasing the memory cells in the memory block is further described below:

and applying a bit line voltage to a bit line of the memory string where the memory cell is located to generate holes at one end of the memory string close to the bit line, wherein the holes are transmitted to a channel of the memory string, so that the voltage of the channel is increased. And applying an erasing voltage to the word line coupled with the memory unit, wherein the erasing voltage is less than the voltage of the channel, and the voltage difference between the erasing voltage and the word line is greater than the tunneling voltage of the memory unit, the tunneling effect is generated between the channel of the memory unit and the grid of the memory unit due to the voltage difference, and then holes in the channel of the memory unit tunnel to the storage layer of the memory unit so as to eliminate electrons in the storage layer, thereby realizing the erasing of the memory unit.

Based on the above description, the following describes a process of erasing a memory string with reference to a flowchart of an operation method of a memory device according to an embodiment of the present application shown in fig. 9.

901. A first voltage is applied to a first end of the memory string.

The memory string is any memory string in any memory block to be erased in the memory device. Optionally, the first voltage ranges from 10V to 30V or from 15V to 25V.

Both ends of the memory string are coupled to the bit line contact and the source contact corresponding to the memory string, respectively, and are referred to as a first end and a second end, respectively, for convenience of description. Wherein the first end is coupled to a bit line contact corresponding to the memory string or coupled to a source contact corresponding to the memory string. And the second end is the other end of the memory string than the first end. For example, if the first end is coupled to a bitline contact, the second end is coupled to a source contact, and if the first end is coupled to a source contact, the second end is coupled to a bitline contact.

A first voltage is applied to a first end of the memory string to generate holes at the first end. Initially, the voltage of the channel is less than the first voltage, thereby causing holes to move from the first end of the memory string, to the channel of the memory string, and along the channel to the second end of the memory string. Along with the movement of the holes in the channel, the holes are distributed to all positions of the channel of the memory string, and then the voltage of the whole channel gradually reaches the first voltage. In addition, a first voltage is also applied to the second end of the memory string, so that the voltages at two ends of the channel of the memory string are the same, and the channel of the memory string is prevented from being conducted.

902. A second voltage is applied to a word line to which the first memory cell is coupled, the second voltage being less than the first voltage, and a voltage difference between the first voltage and the second voltage being greater than or equal to a first tunneling voltage.

The first storage unit is a storage unit in which invalid data is stored in the storage string, at least one first storage unit in the storage string is provided, and the invalid data is data which is specified to be erased by a user. Optionally, the second voltage ranges from 0V to 3V, the first tunneling voltage is a tunneling unit of the first memory cell, the first tunneling voltage is a minimum voltage capable of erasing data stored in the first memory cell, and the first tunneling voltage ranges from 15V to 30V.

The voltage of the channel of the first memory cell gradually reaches a first voltage along with the movement of holes in the channel, and since the voltage difference between the first voltage and the second voltage is greater than or equal to a first tunneling voltage and the first tunneling voltage is the minimum voltage capable of erasing the data stored in the first memory cell, the voltage difference is enough to generate a tunneling effect between the channel of the first memory cell and the gate of the first memory cell, so that the data stored in the first memory cell can be erased.

903. Configuring a third voltage for a word line coupled to a second memory cell, the third voltage being less than the first voltage, and a voltage difference between the first voltage and the third voltage being less than a second tunneling voltage.

The second storage unit is a storage unit in which valid data is stored in a storage string, at least one second storage unit in the storage string is provided, and the valid data is data stored in the storage string except invalid data. Optionally, the third voltage has a value ranging from 10V to 25V, the second tunneling voltage is a tunneling voltage of the second memory cell, the second tunneling voltage is a minimum voltage capable of erasing data stored in the second memory cell, and the second tunneling cell has a value ranging from 15V to 30V.

In one possible implementation, the third voltage is applied by applying the third voltage to the word line to which the second memory cell is coupled; or floating the word line to which the second memory cell is coupled to configure the third voltage for the word line to which the second memory cell is coupled. The word line coupled to the second memory cell is floated to make the second memory cell in the floating state, and after the word line is in the floating state, if the channel voltage is increased, the voltage of the word line is increased by the voltage jump principle at two ends of the capacitor, for example, to a third voltage. For example, the word line is disconnected from the power source to float the word line.

The voltage of the channel of the second memory cell gradually reaches the first voltage as holes move in the channel. And because the voltage difference between the first voltage and the third voltage is smaller than the second tunneling voltage, and the second tunneling voltage is the minimum voltage capable of erasing the data stored in the second memory cell, the voltage difference is not enough to cause a tunneling effect between the channel of the second memory cell and the gate of the second memory cell, so that the data stored in the second memory cell can be protected from being erased.

It should be noted that, the execution of steps 901-903 is not in sequence. For example, the

steps

901 and 903 may be executed simultaneously, or the step 901 may be executed first, and then the

steps

902 and 903 may be executed simultaneously. Or, step 903, then step 902, and then step 901 are executed, where the execution sequence of

steps

901 and 903 is not limited in this embodiment.

In the method provided by the embodiment of the application, in the process of erasing the memory block, a first voltage is applied to a first end of a memory string, a second voltage smaller than the first voltage is applied to a word line coupled to a first memory cell of the memory string, and invalid data stored in the memory string can be erased because the voltage difference between the first voltage and the second voltage is larger than or equal to the tunneling voltage of the first memory cell.

In one possible implementation, the first memory cell of the memory string is proximate to the first end and the second memory cell is distal to the first end. In yet another possible embodiment, the first memory cell of the memory string is located away from the first end and the second memory cell is located close to the first end.

And controlling holes to move from different directions of the memory string to the channel of the memory string according to different distribution conditions of the first memory cell in the memory string. For example, by applying a first voltage to the first end of the first memory cell, holes are controlled to move from the first end of the first memory cell to the channel of the memory string. For another example, by applying a first voltage to the first end of the first memory cell, holes are controlled to move from the first end of the first memory cell to the channel of the memory string.

The following description is provided for the process of controlling the movement of holes from the end of the memory string near the first memory cell to the channel of the memory string:

since the first end of a memory string may be coupled to the bit line contact corresponding to the memory string and also to the source contact corresponding to the memory string, there are 2 cases, respectively case 1 and case 2, for the memory string.

Case 1, a first memory cell in the memory string is near the first end, a second memory cell is far from the first end, and the first end is coupled to a bit line contact corresponding to the memory string.

Taking the schematic distribution diagram of memory cells in a memory string provided by the embodiment of the present application shown in fig. 10 as an example, when the first end is coupled to the bit line contact corresponding to the memory string, the memory string satisfying case 1 is exemplarily the memory string 1001 shown in fig. 7. The first memory cell in memory string 1001 is in an adjacent layer and is near the bit line contact to which memory string 1001 is coupled as the upper memory cell of memory string 1001. The second memory cell in memory string 1001 is in an adjacent layer and is adjacent to the source contact to which memory string 1001 is coupled as the lower memory cell of memory string 1001.

Case 2, a first memory cell in the memory string is proximate to the first end, a second memory cell is distal to the first end, and the first end is coupled to a corresponding source contact of the memory string.

When the first end is coupled to the source contact corresponding to the memory string, structure 2 is exemplarily the memory string 1002 shown in fig. 10, and the first memory cell in the memory string 1002 is located at an adjacent layer and is close to the source contact to which the memory string 1002 is coupled, as a lower-layer memory cell of the memory string 1002. The second memory cell in memory string 1002 is in an adjacent layer and is adjacent to the bit line contact to which memory string 1002 is coupled as the upper memory cell of memory string 1002.

The process of controlling the holes to move along the channel from the first end to the second end of the memory string is different for different situations of the memory string. Here, taking case 1 as an example, the following description is made for the process of controlling the holes to move along the channel from the first end to the second end of the memory string:

in case 1, when the first memory cell is close to the first end and the first end is close to the bit line contact corresponding to the memory string, if the bit line contact is an N-type doped conductive structure and the doping concentration of the impurity is greater than or equal to the first concentration, the first voltage is applied to the bit line contact to control the movement of holes from the first end of the memory string to the channel of the memory string.

The doped conductive structure is an impurity semiconductor obtained by doping an impurity into an intrinsic semiconductor, for example, the impurity semiconductor obtained by doping a pentavalent impurity element is an N-type impurity semiconductor, that is, an N-type doped conductive structure. And the impurity semiconductor obtained by doping the trivalent impurity element is a P-type impurity semiconductor, namely a P-type doped conductive structure.

The doped conductive structure is classified into a heavily doped conductive structure, a middle doped conductive structure, and a lightly doped conductive structure according to different doping concentrations of impurities. The heavily doped conductive structure is a doped conductive structure with impurities having a doping concentration greater than or equal to a first concentration, for example, the N-type doped conductive structure with the doping concentration greater than or equal to the first concentration is an N-type heavily doped conductive structure, and the P-type doped conductive structure with the doping concentration greater than or equal to the first concentration is a P-type heavily doped conductive structure. The medium doped conductive structure is a doped conductive structure with impurities having a doping concentration less than a first concentration and greater than a second concentration, for example, the N-type doped conductive structure with the doping concentration less than the first concentration and greater than the second concentration is an N-type medium doped conductive structure, and the P-type doped conductive structure with the doping concentration less than the first concentration and greater than the second concentration is a P-type medium doped conductive structure. The lightly doped conductive structure is a doped conductive structure with a doping concentration of impurities less than or equal to a second concentration, for example, the N-type doped conductive structure with the doping concentration less than or equal to the second concentration is an N-type lightly doped conductive structure, and the P-type doped conductive structure with the doping concentration less than or equal to the second concentration is a P-type lightly doped conductive structure. In addition, for convenience of description, the medium-doped conductive structure and the light-doped conductive structure are both referred to as a common doped conductive structure, for example, the N-type medium-doped conductive structure and the N-type light-doped conductive structure are both referred to as an N-type common doped conductive structure, the P-type medium-doped conductive structure and the P-type light-doped conductive structure are both referred to as a P-type common doped conductive structure,

wherein the second concentration is less than the first concentration, and in one possible embodiment, the first concentration is 5 x 10^ 8. The second concentration may be set according to an application scenario, and the second concentration is not limited in this embodiment of the application.

If the first memory cell is near the first end, the first end is coupled to a bit line contact, and the bit line contact is an N-type heavily doped conductive structure, the source contact coupled to the memory string may be of a different material, for example, the source contact is an N-type heavily doped conductive structure or a P-type heavily doped conductive structure (e.g., a P-type heavily doped conductive structure).

Case 1 can be further extended to cases 1.1 and 1.2 below based on source contacts of different materials.

In case 1.1, the bit line contact coupled to the first end is an N-type heavily doped conductive structure, the source contact coupled to the memory string is an N-type heavily doped conductive structure, the first memory cell is close to the first end, and the second memory cell is far from the first end and close to the source contact.

In case 1.2, the bit line contact coupled to the first end is an N-type heavily doped conductive structure, the source contact coupled to the memory string is a P-type heavily doped conductive structure, the first memory cell is close to the first end, and the second memory cell is far from the first end and close to the source contact.

In a possible embodiment, the storage string further comprises at least one first selection pipe, the first selection pipe being close to the first end. For example, if the first end is coupled to a bit line contact, the first select tube is also the upper select tube. The first select transistor is also a lower select transistor if the first end is coupled to a source contact.

For each of cases 1.1 and 1.2, the first select transistor of the memory string is controlled to generate gate-induced drain leakage (GIDL) by applying a first voltage to the bit line contact, the GIDL generating electron-hole pairs between the gate and the drain of the first select transistor, the holes in the electron-hole pairs moving toward the channel of the memory string and entering the channel of the memory string. Wherein the hole refers to the effect of losing one electron on a covalent bond and leaving a vacancy on the covalent bond.

For example, a first voltage is applied to the bit line to which the bit line contact is connected, and a first voltage is applied to the source line so that voltages at both ends of a channel of the memory string are the same to prevent the channel of the memory string from being turned on. And applying a fourth voltage to the select line coupled to the first select tube, where the fourth voltage is less than the first voltage, and a voltage difference between the first voltage and the fourth voltage satisfies a voltage difference condition that band-to-band tunneling (B2B) occurs, so that a voltage difference is formed between the gate and the drain of the first select tube, B2B occurs between the gate and the drain of the first select tube, and an electron-hole pair is generated, and a hole in the electron-hole pair moves to the channel of the memory string and enters the channel of the memory string.

In one possible implementation, before the channel voltage of the memory string is increased to a tenth voltage, an eleventh voltage is configured for the select line coupled to the first select transistor, wherein the channel voltage of the memory string is the voltage of the channel of the memory string, the tenth voltage is smaller than the first voltage and larger than the fourth voltage, and a voltage difference between the tenth voltage and the fourth voltage is smaller than or equal to a fourth tunneling voltage, which is a minimum voltage capable of causing the first select transistor to generate a tunneling effect, that is, the tunneling voltage of the first select transistor. The eleventh voltage is less than the first voltage, and a voltage difference between the first voltage and the eleventh voltage is less than the fourth tunneling voltage, so that after the channel voltage is increased to the first voltage, the voltage difference between the gate and the channel of the first select tube is less than the fourth tunneling voltage, and the threshold voltage of the first select tube can be prevented from drifting.

In a possible embodiment, the storage string further comprises at least one second selection pipe, the second selection pipe being remote from the first end. For example, if the first end is coupled to a bit line contact, the second select tube is also the lower select tube. The second select transistor is also referred to as an upper select transistor if the first end is coupled to a source contact.

In addition, a sixth voltage is configured for the select line coupled to the second select transistor in the memory string, the sixth voltage is smaller than the first voltage, and a voltage difference between the first voltage and the sixth voltage is smaller than a third tunneling voltage, and the third tunneling voltage is a minimum voltage capable of causing the second select transistor to generate a tunneling effect, namely, a tunneling voltage of the second select transistor. With the movement of the holes in the channel, the voltage of the channel of the second selection tube gradually reaches the first voltage, and then a voltage difference, namely a difference value between the first voltage and the sixth voltage, is generated between the channel of the second selection tube and the gate of the second selection tube.

It should be noted that, if the first selection pipe is an upper selection pipe, the selection line coupled to the first selection pipe is DSL, and if the first selection pipe is a lower selection pipe, the selection line coupled to the first selection pipe is SSL. If the second selection pipe is an upper selection pipe, the selection line coupled with the second selection pipe is DSL, and if the second selection pipe is a lower selection pipe, the selection line coupled with the second selection pipe is SSL. Optionally, the sixth voltage and the eleventh voltage both have a value range of 10V to 25V, and the third tunneling voltage and the fourth tunneling voltage have a value range of 15V to 30V. The process of applying the sixth voltage to the select line coupled to the second select transistor in the memory string is the same as the process of applying the third voltage to the word line coupled to the second memory cell, for example, applying the sixth voltage to the select line coupled to the second select transistor or floating the select line coupled to the second select transistor so that the voltage of the coupled word line of the second memory cell reaches the sixth voltage. The eleventh voltage is applied to the select line coupled to the first select transistor in the memory string in the same manner as the third voltage is applied to the word line coupled to the second memory cell. For example, the eleventh voltage is applied to the select line to which the first select transistor is coupled, or the select line to which the first select transistor is coupled is floated, so that the voltage of the coupled word line of the first memory cell reaches the eleventh voltage.

To further illustrate the situation of applying voltages to each device in a memory string during data erasing in case 1.1, refer to a voltage waveform diagram in case 1.1 provided by the embodiment of the present application shown in fig. 11. As shown in fig. 11, the first memory cell is an upper memory cell of the memory string, near the first end of the memory string, and the bit line contact coupled to the first end is an N-type heavily doped conductive structure, while the second memory cell is a lower memory cell of the memory string, far from the first end and near the source contact coupled to the memory string. The source line contact is respectively connected with the source contact part and the source line, wherein the source contact part and the source line contact are both N-type heavily doped conductive structures (represented by 'N +' in the figure).

During the data erasing process of the memory string, the voltages of the BL and the SL gradually increase from the respective initial voltages until increasing to the first voltage in the time period t1-t3, and the first voltage is maintained in the time period t3-t 4.

During the time period t1-t2, the TSG acts as the first select tube of the memory string, and its coupled select line is held at the fourth voltage. The voltage difference generated by the voltage of the BL and the voltage of the selection line enables holes to be generated at the position corresponding to the TSG, and at the moment, the voltage of the channel is lower than the first voltage, the holes move to the channel at the low voltage, and the voltage of the channel is gradually increased. During the time period t2-t3, the select line to which the TSG is coupled is floated, the select line is in a floating state, and when the voltage of the channel rises, the voltage jump principle across the capacitor causes the voltage of the select line to increase. For example, the select line to which the TSG is coupled gradually increases from the fourth voltage until increasing to the eleventh voltage. The voltage difference between the gate and the channel of the TSG is smaller than the tunneling voltage of the TSG, so that the threshold voltage of the TSG is prevented from drifting.

The word line to which the first memory cell is coupled is maintained at the second voltage for a time period t2-t4, and as the voltage of the channel increases, when a voltage difference between the voltage of the channel and the second voltage is greater than a tunneling voltage of the first memory cell, data stored by the first memory cell can be erased,

during the time period t1-t3, the word line to which the second memory cell is coupled is floated, the word line is in a floating state, and when the voltage of the channel rises, the voltage jump principle across the capacitor causes the voltage of the word line to increase. For example, the voltage of the word line is gradually increased from the initial voltage of the word line until the voltage is increased to a third voltage. As the voltage of the word line increases, the voltage difference between the voltage of the channel and the voltage of the word line is smaller than the tunneling voltage of the second memory cell, so as to prevent the data stored in the second memory cell from being erased.

In the time period t2-t3, the BSG is the second select tube of the memory string whose coupled select line is floated, similar to the select line to which the TSG is coupled being floated, so that the voltage of the select line gradually increases from the initial voltage of the select line until increasing to the sixth voltage. As the voltage of the selection line increases, the voltage difference between the voltage of the channel and the voltage of the selection line is smaller than the tunneling voltage of the BSG, so that the threshold voltage of the BSG is prevented from drifting.

To further illustrate the situation in case 1.2, during data erasing process of the memory string, the voltage application of each device in the memory string is shown in fig. 12, which is a schematic diagram of the voltage waveform during data erasing process in case 1.2. As shown in fig. 12, the first memory cell is an upper memory cell of the memory string, near the first end of the memory string, and the bit line contact coupled to the first end is an N-type heavily doped conductive structure, while the second memory cell is a lower memory cell of the memory string, far from the first end and near the source contact coupled to the memory string. The source line contact is respectively connected with the source contact part and the source line, wherein the source contact part is a P-type heavily doped conductive structure (represented by 'P +' in the figure), and the source line contact is an N-type heavily doped conductive structure.

The process of controlling the movement of the holes from the first end to the second end of the memory string is different for different cases of the memory string, and here, taking case 2 as an example, the process of controlling the movement of the holes from the first end to the second end of the memory string is described as follows:

for case 2, a first memory cell in a memory string is near a first end, a second memory cell is far from the first end, and the first end is coupled to a corresponding source contact of the memory string, controlling holes to move from the first end of the memory string to the second end of the memory string.

In different implementations, the source contact has different materials. For example, the source contact is an N-type heavily doped conductive structure or a P-type heavily doped conductive structure. Case 2 can be further extended to cases 2.1 and 2.2 below based on source contacts of different materials.

Case 2.1, a first memory cell in a memory string is close to a first end, a second memory cell is far away from the first end, the first end is coupled to a source contact corresponding to the memory string, and the source contact is an N-type heavily doped conductive structure.

Case 2.2, a first memory cell in a memory string is close to a first end, a second memory cell is far away from the first end, the first end is coupled to a source contact corresponding to the memory string, and the source contact is a P-type heavily doped conductive structure.

For the source contacts of different materials in case 2.1 and case 2.2, the manner of controlling the holes to move from the first end to the second end of the memory string is different, and for case 2.1 and case 2.2, the following description is made for the process of controlling the holes to move from the first end coupled to the source contact to the second end of the memory string, respectively:

for case 2.1, the bit line contacts to which the memory string is coupled may also be of different materials. For example, the bit line contact is an N-type heavily doped conductive structure or an N-type commonly doped conductive structure. Case 2.1 can be further extended to cases 2.1.1 and 2.1.2 below based on bit line contacts of different materials.

In case 2.1.1, the bit line contact coupled to the memory string is an N-type heavily doped conductive structure, the source contact coupled to the first end is an N-type heavily doped conductive structure, the first memory cell is close to the first end, and the second memory cell is far from the first end and close to the bit line contact.

Case 2.1.2, the bit line contact coupled to the memory string is an N-type common doped conductive structure, the source contact coupled to the first end is an N-type heavily doped conductive structure, the first memory cell is close to the first end, and the second memory cell is far from the first end and close to the bit line contact.

For each of cases 2.1.1 and 2.1.2, in one possible implementation, a first select transistor of the memory string is controlled to generate electron-hole pairs by applying a first voltage to a source contact, the holes of the electron-hole pairs moving toward a channel of the memory string and entering the channel of the memory string.

For example, a first voltage is applied to the bit line to which the bit line contact is connected, and a first voltage is applied to the source line so that voltages at both ends of a channel of the memory string are the same to prevent the channel of the memory string from being turned on. And applying a second voltage to the word line coupled to the first selection tube, so that a voltage difference between the first voltage and the second voltage is formed between the source electrode and the grid electrode of the first selection tube, the voltage difference causes band-to-band tunneling to occur between the grid electrode and the source electrode of the first selection tube, and GIDL is generated, and holes in the GIDL move to the channel of the memory string and enter the channel of the memory string.

In addition, before the channel voltage of the memory string is increased to the tenth voltage, the eleventh voltage is configured for the selection line coupled with the first selection tube, so as to avoid the threshold voltage of the first selection tube from drifting along with the rising of the channel voltage. And configuring a sixth voltage for a selection line coupled with a second selection tube in the memory string to avoid the threshold voltage of the second selection tube from drifting along with the rising of the channel voltage.

To further illustrate the situation that in case 2.1.1, during data erasing process of the memory string, the voltages of the devices in the memory string are applied, see fig. 13, which is a schematic diagram of the voltage waveforms during data erasing process in case 2.1.1 according to the embodiment of the present application. As shown in fig. 13, the second memory cell, which is an upper memory cell of the memory string, is far away from the first end of the memory string and close to a bit line contact coupled to the memory string, and the bit line contact is an N-type heavily doped conductive structure. And a first memory cell, as a lower memory cell of the memory string, proximate the first end and coupled to the source contact. The source line contact is respectively connected with the source electrode contact part and the source line, wherein the source electrode contact part and the source line contact are both N-type heavily doped conductive structures.

During the time period t1-t2, the BSG acts as the first select tube of the memory string, whose coupled select line is held at the fourth voltage. The voltage difference generated by the voltage of the source line and the voltage of the selection line enables holes to be generated at the position corresponding to the BSG, and at the moment, the voltage of the channel is lower than the first voltage, the holes move to the channel at the low voltage, and the voltage of the channel is gradually increased. During the time period t2-t3, the select line to which the BSG is coupled is floated, the select line is in a floating state, and as the voltage of the channel increases, the voltage jump across the capacitor causes the selected voltage to increase. For example, the select line to which the BSG is coupled gradually increases from the fourth voltage until increasing to the eleventh voltage. The voltage difference between the gate and the channel of the BSG is smaller than the tunneling voltage of the BSG, so that the threshold voltage of the BSG is prevented from drifting.

The word line to which the first memory cell is coupled is maintained at the second voltage for a time period t2-t4, and as the voltage of the channel increases, the data stored by the first memory cell can be erased when the voltage difference between the channel voltage and the second voltage is greater than the tunneling voltage of the first memory cell.

During the time period t2-t3, the TSG is the second select tube of the memory string whose coupled select line is floated, similar to the select line to which the BSG is coupled, such that the voltage of the select line gradually increases from the initial voltage of the select line until increasing to a sixth voltage. As the voltage of the selection line increases, the voltage difference between the voltage of the channel and the voltage of the selection line is smaller than the tunneling voltage of the TSG, so as to avoid the threshold voltage of the TSG from drifting.

To further illustrate the situation that in case 2.1.2, during data erasing, voltages of devices in a memory string are applied, see fig. 14, which is a schematic diagram of voltage waveforms during data erasing in case 2.1.2 according to the embodiment of the present application. As shown in fig. 14, the second memory cell is an upper memory cell of the memory string, and is close to a bit line contact of the memory string, and the bit line contact is an N-type common doped conductive structure (denoted by "N" in the figure). The first memory cell is used as a lower memory cell of the memory string, and a source contact part which is close to the first end of the memory string and is coupled with the first end is an N-type heavily doped conductive structure. The source line contact is respectively connected with the source electrode contact part and the source line, wherein the source line contact is of an N-type heavily doped conductive structure.

During the time period t2-t3, the TSG is the second select tube of the memory string whose coupled select line is floated, similar to the select line to which the BSG is coupled, such that the voltage of the select line gradually increases from the initial voltage of the select line until increasing to a sixth voltage, and the sixth voltage is maintained during the time period t3-t 4. As the voltage of the selection line increases, the voltage difference between the voltage of the channel and the voltage of the selection line is smaller than the tunneling voltage of the TSG, so as to avoid the threshold voltage of the TSG from drifting.

The above is the description of the process of controlling the memory string to generate the holes at the corresponding positions of the first select tubes so as to move to the channels of the memory string in conjunction with the case 2.1. In this connection, with reference to case 2.2, the process of controlling the movement of holes from the first end to the second end of the memory string is described as follows:

for case 2.2, in one possible implementation, when the first end is coupled to a corresponding source contact of the memory string, and the source contact is a heavily P-doped conductive structure, the bit line contact coupled to the memory string may also be made of different materials, for example, the bit line contact is an N-type commonly doped conductive structure or an N-doped conductive structure. Case 2.2 can be further extended to cases 2.2.1 and 2.2.2, below, based on bit line contacts of different materials.

In case 2.2.1, the source contact coupled to the first end is a P-type heavily doped conductive structure, the bit line contact coupled to the memory string is an N-type common doped conductive structure, the first memory cell is close to the first end, and the second memory cell is far from the first end and close to the bit line contact.

Case 2.2.2, the substrate coupled to the first end is a P-type heavily doped conductive structure, the bit line contact coupled to the memory string is an N-type heavily doped conductive structure, the first memory cell is close to the first end, and the second memory cell is far from the first end and close to the bit line contact.

For each of cases 2.2.1 and 2.2.2, in one possible implementation, the source contact is controlled to generate holes that move toward the channel of the memory string and into the channel of the memory string.

For example, a first voltage is applied to the bit line to which the bit line contact is connected, and a first voltage is applied to the source line so that voltages at both ends of a channel of the memory string are the same to prevent the channel of the memory string from being turned on. A first voltage of the source line is applied to the source contact through the source line contact, and a positive potential is continuously output to the substrate. And because the source contact part is of a P-type heavily doped conductive structure, the continuously input positive potential causes the source contact part to generate holes, and the holes generated by the source contact part move to the channel of the memory string and enter the channel of the memory string.

In addition, a fifth voltage is applied to the selection line coupled to the first selection tube of the memory string, wherein the fifth voltage is lower than the first voltage, so that the holes generated by the source contact part move to the channel direction of the first selection tube and can move to the channel direction of the second selection tube through the channel of the first selection tube.

Before the channel voltage of the memory string is increased to the tenth voltage, an eleventh voltage is configured for the selection line coupled to the first selection tube to avoid the threshold voltage of the first selection tube from drifting along with the rising of the channel voltage. And configuring a sixth voltage for a selection line coupled with a second selection tube in the memory string to avoid the threshold voltage of the second selection tube from drifting along with the rising of the channel voltage.

To further illustrate the situation of applying voltages to each device in a memory string during data erasing in case 2.2.1, see a schematic diagram of voltage waveforms during data erasing in case 2.2.1 provided by the embodiment of the present application shown in fig. 15. As shown in fig. 15, the second memory cell is an upper memory cell of the memory string, and is located away from the first end and close to a bit line contact coupled to the memory string, where the bit line contact is an N-type common doped conductive structure. The first memory cell is used as a lower memory cell of the memory string, and a source contact part which is close to the first end and is coupled with the first end is a P-type heavily doped conductive structure. The source line contact is connected to the source contact portion and the source line, respectively. The source line contact is an N-type heavily doped conductive structure.

During the data erasing process of the memory string, the voltages of the BL and the SL gradually increase from the respective initial voltages until increasing to the first voltage in the time period t1-t3, and the first voltage is maintained in the time period t3-t 4. The voltage of the SL is applied to the source contact through the source line contact, so that holes are generated at the source contact as the voltage of the source contact increases.

During the time period t1-t2, the BSG acts as the first select tube of the memory string, whose coupled select line is held at the fifth voltage. The fifth voltage is a low voltage, and as the voltage of the source contact increases, a voltage difference between the voltage of the source contact and the fifth voltage causes holes generated by the source contact to move toward the channel of the BSG and further enter the channel of the memory string. At this time, the voltage of the channel is lower than the first voltage, and the holes move to the channel at the low voltage, so that the voltage of the channel gradually increases. During the time period t2-t3, the select line to which the BSG is coupled is floated, the select line is in a floating state, and as the voltage of the channel increases, the voltage jump across the capacitor causes the selected voltage to increase. For example, the select line to which the BSG is coupled gradually increases from the fourth voltage until increasing to the eleventh voltage. The voltage difference between the gate and the channel of the BSG is smaller than the tunneling voltage of the BSG, so that the threshold voltage of the BSG is prevented from drifting.

To further illustrate the situation that in case 2.2.2, during data erasing, voltages of devices in a memory string are applied, see fig. 16, which is a schematic diagram of voltage waveforms during data erasing in case 2.2.2 according to the embodiment of the present application. As shown in fig. 16, the second memory cell is an upper memory cell of the memory string, and is far from the first end and close to a bit line contact coupled to the memory string, and the bit line contact is an N-type heavily doped conductive structure. The first memory cell is used as a lower memory cell of the second memory string, and a source contact part which is close to the first end and is coupled with the first end is a P-type heavily doped conductive structure. The source line contact is respectively connected with the source electrode contact part and the source line, wherein the source line contact is of an N-type heavily doped conductive structure.

The above description has been made on the process of controlling the movement of holes from the end of the memory string near the first memory cell to the channel of the memory string. In yet another possible implementation, the movement of holes to the channel of the memory string is controlled from the end of the memory string remote from the first memory cell. Referring to fig. 17, a flow chart of an operation method of a memory device according to an embodiment of the present application is provided. The method is performed by peripheral circuitry in the memory device.

1701. A first voltage is applied to a first end of the memory string.

The process is described above in relation to generating holes at the first end, for example, by the source contact or at a corresponding location of the first select transistor, by applying the first voltage to the first end of the memory string, and is not described herein again.

In addition, a first voltage is also applied to the second end of the memory string, so that the voltages at two ends of the channel of the memory string are the same, and the channel of the memory string is prevented from being conducted.

1702. If the first memory cell is far from the first end of the memory string and the second memory cell is close to the first end, an eighth voltage is applied to the word line coupled to the second memory cell before the channel voltage of the memory string reaches a seventh voltage, the seventh voltage is greater than the eighth voltage and less than or equal to the first voltage, and the voltage difference between the seventh voltage and the eighth voltage is less than the second tunneling voltage.

The seventh voltage is a voltage before the channel voltage of the memory string reaches the first voltage in the process of moving the holes to the channel of the memory string, and therefore the seventh voltage is smaller than the first voltage. And the seventh voltage is greater than the eighth voltage, so that a voltage difference is formed between the channel of the second storage unit and the gate of the second storage unit, and the voltage difference is less than the tunneling voltage of the second storage unit, so as to protect the data stored in the second storage unit from being erased. And the eighth voltage is smaller than the first voltage of the first end, so that the holes move from the first end to the channel direction of the second memory cell and enter the channel of the first memory cell. The value range of the eighth voltage is 0V to 5V, and optionally, the value range of the eighth voltage is 0V to 3V. For example, the third gate voltage is 0V, 1V, or 2V. Optionally, the third gate voltage is equal to the first gate voltage.

And applying an eighth voltage to the word line coupled with the second memory cell, wherein the eighth voltage is lower than the voltage of the first end, so that the holes from the first end move to the direction of the channel of the second memory cell at low potential after entering the channel of the memory string, and enter the channel of the first memory cell through the channel of the second memory cell.

After the hole enters the channel of the memory string and moves in the channel of the memory string, the voltage of each position in the channel is gradually increased, and finally the channel voltage is increased to the first voltage. And continuing to apply the eighth voltage to the word line to which the second memory cell is coupled until the channel voltage reaches a seventh voltage. The seventh voltage is greater than the eighth voltage, so that a voltage difference formed between a channel and the gate of the second memory cell is less than a tunneling voltage of the second memory cell, thereby protecting data stored in the second memory cell from being erased.

1703. After the channel voltage of the memory string reaches the seventh voltage, a third voltage is configured for the word line to which the second memory cell is coupled, the third voltage being less than a high first voltage, and a voltage difference between the first voltage and the third voltage being less than a second tunneling voltage.

And configuring a third voltage for the word line coupled to the second memory cell when the channel voltage reaches a seventh voltage along with the increase of the channel voltage, so that a voltage difference formed between the channel and the gate of the second memory cell is smaller than that of the tunneling cell of the second memory cell, thereby preventing the data stored in the second memory cell from being erased.

Please refer to step 903 above, which is not described herein again for the process of configuring the second voltage for the word line coupled to the second memory cell.

1704. A second voltage is applied to a word line to which the first memory cell is coupled, the second voltage being less than the first voltage, and a voltage difference between the first voltage and the second voltage being greater than or equal to a first tunneling voltage.

Step 1704 is similar to step 902, and here, the step 1704 is not described in detail in this embodiment of the present application.

It should be noted that

steps

1701, 1702 and 1704 are not executed in a sequential order. For example, steps 1701, 1702 and 1704 may be executed simultaneously, or step 901 may be executed first, and then steps 1702 and 1704 may be executed simultaneously. Further alternatively, step 1704 is executed first, step 1702 is executed, and step 1701 is executed, where the execution order of

steps

1701, 1702, and 1704 is not limited in this embodiment of the present application.

To facilitate understanding of the process of step 1701-: the first memory cell is far from the first end of the memory string, the second memory cell is near to the first end, the source contact part coupled to the first end is a P-type heavily doped conductive structure, and the bit line contact coupled to the memory string is an N-type common doped conductive structure, for example, as follows:

in case 3, the bit line contact coupled to the memory string is an N-type common doped conductive structure, and the data erase using GIDL cannot be performed using the upper select transistor, so that the source contact portion can be controlled to generate holes, and the holes generated by the source contact portion move to the channel of the second memory cell after entering the channel of the memory string, and then move from the channel of the second memory cell to the channel of the first memory cell.

For further embodying the voltage application condition of each device in the memory string during data erasing process of the memory string in case 3, refer to a voltage waveform diagram during data erasing process in case 3 provided by the embodiment of the present application shown in fig. 18. As shown in fig. 18, the first memory cell is an upper memory cell of the memory string, and is located away from the first end of the memory string and close to a bit line contact coupled to the memory string, and the bit line contact is an N-type commonly doped conductive structure. The second memory cell is used as a lower memory cell of the memory string, and a source contact part which is close to the first end and is coupled with the first end is a P-type heavily doped conductive structure. The source line contact is respectively connected with the source electrode contact part and the source line, wherein the source line contact is of an N-type heavily doped conductive structure.

During the time period t1-t2, the word line to which the second memory cell is coupled is maintained at an eighth voltage, which is less than the first voltage, such that holes generated by the source contact move through the channel of the BSG in the direction of the channel of the second memory cell and through the channel of the second memory cell continue to move toward the channel of the first memory cell. During the time period t2-t3, the word line to which the second memory cell is coupled is floated, the word line is in a floating state, and when the voltage of the channel rises, the voltage jump principle across the capacitor causes the voltage of the word line to increase. For example, the voltage of the word line is gradually increased from the initial voltage of the word line until the voltage is increased to a third voltage. As the voltage of the word line increases, the voltage difference between the voltage of the channel and the voltage of the word line is smaller than the tunneling voltage of the second memory cell, so as to prevent the data stored in the second memory cell from being erased.

In the method provided by the embodiment of the application, in the process of erasing the memory block, a first voltage is applied to a first end of a memory string, a second voltage smaller than the first voltage is applied to a word line coupled to a first memory cell of the memory string, and invalid data stored in the memory string can be erased because the voltage difference between the first voltage and the second voltage is larger than or equal to the tunneling voltage of the first memory cell. And, by controlling the hole to move from the end of the memory string near the second memory cell to the channel of the memory string to raise the channel voltage, before the channel voltage reaches the seventh voltage, the eighth voltage is applied to the word line coupled to the second memory cell, so that the hole entering the channel can move to the channel of the first memory cell to erase the data stored in the first memory cell. And when the channel voltage reaches the seventh voltage, configuring a third voltage for the word line coupled with the second memory cell to prevent the data stored in the second memory cell from being erased.

It should be noted that, since the first memory cell and the second memory cell in each memory string in the memory block are arranged in the same manner, and the memory strings of the memory block share the same source line, applying the first voltage to the source line is equivalent to applying the same voltage to the end of each memory string of the memory block coupled to the source line. A first voltage is applied to a bit line corresponding to each memory string in the memory block. When voltages are applied to the word lines coupled to the memory cells in the memory string and the selection lines coupled to the selection pipes, the data stored in the first memory cell in each memory string in the memory block can be erased, and the data stored in the second memory cell in each memory string can be protected from being erased.

In addition, the distribution of the memory strings may be other than the two cases of the memory string 1001 and the memory string 1002 described above, and when the distribution of the memory strings is other possible distribution, data erasure of the memory strings may be performed based on the operation method for the memory device.

Other possible distribution scenarios are, for example, any of storage strings 1003-1005 in FIG. 10. Wherein, the second memory cell in the memory string 1003 is in the adjacent layer and is located in the middle of the memory string 1003. The first memory cell in the memory string 1003 is divided into two parts, one part of the first memory cell is located at the adjacent layer and close to the bit line contact coupled to the memory string 1003, and the other part of the first memory cell is located at the adjacent layer and close to the source contact coupled to the memory string 1003.

The first memory cell in the memory string 1004 is in an adjacent layer and is located in the middle of the memory string 1004. And the second memory cells in memory string 1004 are divided into two portions, one portion of the second memory cells being in an adjacent layer and near the bit line contact to which memory string 1004 is coupled, and the other portion of the second memory cells being in an adjacent layer and near the source contact to which memory string 1004 is coupled.

The first memory cell and the second memory cell in the memory string 1005 are in adjacent layers. Of course, in addition to the memory string 1001-1005, the memory string may have other distribution manners, for example, one layer of the first memory cells is distributed in every two layers of the second memory cells, or the first memory cells and the second memory cells are alternately distributed in the memory string, and herein, the distribution of the first memory cells and the second memory cells in the memory string is not limited in this embodiment of the present application.

It should be appreciated that reference throughout this specification to "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in some embodiments" or "in other embodiments" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The above-mentioned serial numbers of the embodiments of the present disclosure are merely for description and do not represent the merits of the embodiments.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The above description is only an embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered by the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A memory device, comprising a memory array and peripheral circuitry;

the peripheral circuitry is coupled to the storage array and configured to:

2. The memory device of claim 1, wherein the peripheral circuitry is further configured to:

applying the third voltage to the coupled word line of the second memory cell.

3. The memory device of claim 1, wherein the peripheral circuitry is further configured to:

floating the word line to which the second memory cell is coupled.

4. The memory device of any one of claims 1-3, wherein the memory string further comprises at least a first select tube, the first select tube being proximate the first end; the peripheral circuitry is further configured to:

5. The memory device of claim 4, wherein the first end is coupled to a corresponding bit line contact of the memory string, the bit line contact is an N-type doped conductive structure, and a doping concentration of the impurity is greater than or equal to a first concentration.

6. The memory device of claim 5, wherein the first concentration is 5 x 10^ 8.

7. The memory device of claim 4, wherein the first end is coupled to a corresponding source contact of the memory string.

8. The memory device of any one of claims 1-3, wherein the memory string further comprises at least one first select transistor proximate the first end, the first end coupled to a corresponding source contact of the memory string, the source contact being a P-type doped conductive structure; the peripheral circuitry is further configured to:

9. The memory device of any of claims 4-8, wherein the first memory cell is proximate the first end and the second memory cell is distal the first end.

10. The storage device of claim 9, wherein the storage string further comprises at least one second selection pipe, the at least one second selection pipe being distal from the first end; the peripheral circuitry is further configured to:

11. The memory device of any of claims 4-8, wherein the first memory cell is distal from the first end and the second memory cell is proximal to the first end; the peripheral circuitry is further configured to:

12. The memory device of claim 11, wherein the memory string further comprises at least one second select tube, the at least one second select tube distal to the first end; the peripheral circuitry is further configured to:

13. A system comprising a memory device configured to store data, the memory device comprising a memory array and peripheral circuitry;

the peripheral circuitry is coupled to the storage array and configured to:

14. The system of claim 13, wherein the peripheral circuitry is further configured to:

applying the third voltage to the coupled word line of the second memory cell.

15. The system of claim 13, wherein the peripheral circuitry is further configured to:

floating the word line to which the second memory cell is coupled.

16. The system of any of claims 13-15, wherein the storage string further comprises at least a first selector tube, the first selector tube being proximate the first end; the peripheral circuitry is further configured to:

17. The system of claim 16, wherein the first end is coupled to a corresponding bit line contact of the memory string, wherein the bit line contact is an N-type doped conductive structure, and wherein a doping concentration of the impurity is greater than or equal to a first concentration.

18. The system of claim 17, wherein the first concentration is 5 x 10^ 8.

19. The system of claim 16, wherein the first end is coupled to a corresponding source contact of the memory string.

20. The system according to any of claims 13-15, wherein the memory string further comprises at least one first selection transistor, the first selection transistor being proximate to the first end, the first end being coupled to a corresponding source contact of the memory string, the source contact being a P-type doped conductive structure; the peripheral circuitry is further configured to:

21. The system of any of claims 16-20, wherein the first storage unit is proximate the first end and the second storage unit is distal the first end.

22. The system of claim 21, wherein the storage string further comprises at least one second selection pipe, the at least one second selection pipe being distal from the first end; the peripheral circuitry is further configured to:

23. The system of any of claims 16-20, wherein the first storage unit is distal from the first end and the second storage unit is proximal to the first end; the peripheral circuitry is further configured to:

24. The system of claim 23, wherein the storage string further comprises at least one second selector tube, the at least one second selector tube distal from the first end; the peripheral circuitry is further configured to:

25. The system of any of claims 13-24, further comprising a host and a memory controller;

the host is configured to send data to or receive data from the storage device;

the memory controller is coupled to the host and the storage device and configured to control the storage device.

26. A method of operating a memory device, the memory device comprising a memory array including a memory string and a plurality of word lines, the memory string including at least one first memory cell and at least one second memory cell, the first memory cell being a memory cell of the memory string in which invalid data is stored, the second memory cell being a memory cell of the memory string in which valid data is stored, the plurality of word lines being respectively coupled to the plurality of memory cells of the memory string; the method comprises the following steps:

27. The method of claim 26, wherein configuring the word line to which the second memory cell is coupled with a third voltage comprises:

applying the third voltage to the coupled word line of the second memory cell.

28. The method of claim 26, wherein configuring the word line to which the second memory cell is coupled with a third voltage comprises:

floating the word line to which the second memory cell is coupled.

29. The method of any of claims 26-28, wherein the storage string further comprises at least a first selector tube, the first selector tube being proximate the first end; the method further comprises the following steps:

30. The method of claim 29, wherein the first end is coupled to a corresponding bit line contact of the memory string, wherein the bit line contact is an N-type doped conductive structure, and wherein a doping concentration of the impurity is greater than or equal to a first concentration.

31. The method of claim 30, wherein the first concentration is 5 x 10 x 8.

32. The method of claim 29, wherein the first end is coupled to a corresponding source contact of the memory string.

33. The method of any of claims 26-28, wherein the memory string further comprises at least a first select transistor proximate to the first end, the first end coupled to a corresponding source contact of the memory string, the source contact being a P-type doped conductive structure; the method further comprises the following steps:

34. The method of any of claims 29-33, wherein the first storage unit is proximate the first end and the second storage unit is distal the first end.

35. The method of claim 34, wherein the storage string further comprises at least one second selector tube, the at least one second selector tube being distal from the first end; the method further comprises the following steps:

36. The method of any of claims 29-33, wherein the first storage unit is distal from the first end and the second storage unit is proximal to the first end; the method further comprises the following steps:

37. The method of claim 36, wherein the storage string further comprises at least one second selector tube, the at least one second selector tube being distal from the first end; the method further comprises the following steps: