CN115019860A - Memory and operation method thereof, and memory system - Google Patents

Memory and operation method thereof, and memory system Download PDF

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Publication number
CN115019860A
CN115019860A CN202210719641.7A CN202210719641A CN115019860A CN 115019860 A CN115019860 A CN 115019860A CN 202210719641 A CN202210719641 A CN 202210719641A CN 115019860 A CN115019860 A CN 115019860A
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word line
voltage
dummy word
charging
memory
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栗山正男
魏镜
张扬
杨名
向莉
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits

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Abstract

The embodiment of the disclosure discloses a memory, an operation method thereof and a memory system. The operation method comprises the following steps: charging the first dummy word line to a first voltage during a first charge phase of a program operation; wherein the first dummy word line is located between the upper select gate line and the word line, and/or the first dummy word line is located between the lower select gate line and the word line; charging the first dummy word line from the first voltage to a second voltage in a second charge phase of the programming operation; wherein the second charging phase is located after the first charging phase, and the charging rate of the first charging phase is less than or equal to the charging rate of the second charging phase; after the second charge phase, charging selected ones of the word lines to a programming voltage; wherein the programming voltage is greater than the second voltage.

Description

Memory and operation method thereof, and memory system
Technical Field
The disclosed embodiments relate to, but are not limited to, the field of integrated circuits, and in particular, to a memory, an operating method thereof, and a memory system.
Background
With the development of science and technology, people live with more and more portable electronic devices, such as digital cameras, MP3, tablet computers, smart phones, and the like. Therefore, the market of the memory has also grown rapidly, so that the integration degree and the bit density of the memory have been gradually increased.
However, as the integration level and bit density of the memory increase, the coupling effect in the memory increases during the logic operation (e.g., program operation) performed on the memory, affecting the normal operation of the memory.
Disclosure of Invention
According to a first aspect of the embodiments of the present disclosure, there is provided an operating method of a memory, including:
charging the first dummy word line to a first voltage during a first charge phase of a program operation; wherein the first dummy word line is located between the upper select gate line and the word line, and/or the first dummy word line is located between the lower select gate line and the word line;
charging the first dummy word line from the first voltage to a second voltage in a second charge phase of the programming operation; wherein the second charging phase is located after the first charging phase, and the charging rate of the first charging phase is less than or equal to the charging rate of the second charging phase;
after the second charge phase, charging selected ones of the word lines to a programming voltage; wherein the programming voltage is greater than the second voltage.
According to a second aspect of embodiments of the present disclosure, there is provided a memory comprising:
a memory cell array comprising:
a word line between upper and lower select gate lines;
a first dummy word line between the upper select gate line and the word line, and/or between the lower select gate line and the word line;
peripheral circuitry coupled to the array of memory cells; wherein the content of the first and second substances,
the peripheral circuitry is configured to charge the first dummy word line to a first voltage during a first charge phase of a programming operation;
the peripheral circuitry is further configured to charge the first dummy word line from the first voltage to a second voltage during a second charge phase of the programming operation; wherein the second charging phase is located after the first charging phase, and the charging rate of the first charging phase is less than or equal to the charging rate of the second charging phase;
the peripheral circuitry is further configured to charge selected ones of the word lines to a programming voltage after the second charge phase; wherein the programming voltage is greater than the second voltage.
According to a third aspect of embodiments of the present disclosure, there is provided a memory system including:
one or more memories as provided in the second aspect of embodiments of the present disclosure;
a memory controller coupled to the memory and configured to control the memory.
In the embodiment of the disclosure, the first dummy word line is charged to the first voltage in the first charging stage of the programming operation, and the first dummy word line is charged from the first voltage to the second voltage in the second charging stage of the programming operation, so that the charging process of the first dummy word line is divided into two stages, and the charging rate of the first charging stage is less than or equal to the charging rate of the second charging stage, so that the boosting rate of the first dummy word line can be better controlled, the parasitic capacitance between the first dummy word line and the upper selection gate line and/or the parasitic capacitance between the first dummy word line and the lower selection gate line can be reduced, and the coupling effect of the first dummy word line on the upper selection gate line and/or the lower selection gate line can be further reduced.
Furthermore, the coupling effect of the first dummy word line on the upper selection grid line and/or the lower selection grid line is reduced, so that the probability that the voltage of the upper selection grid line and/or the voltage of the lower selection grid line greatly rises in the programming process is reduced, and the normal operation of the programming operation of the memory is ensured.
Drawings
FIG. 1 is a partial cross-sectional view of a reservoir shown in accordance with an exemplary embodiment;
FIG. 2 is a partial cross-sectional view of a reservoir shown according to a specific example;
FIG. 3 is a timing diagram illustrating a method of operation of a memory in accordance with an exemplary embodiment;
FIG. 4 is a waveform diagram illustrating an enable signal according to an exemplary embodiment;
FIG. 5 is a flow chart illustrating a method of operation of a memory according to an embodiment of the present disclosure;
FIG. 6 is a timing diagram one illustrating a method of operation of a memory according to an embodiment of the present disclosure;
FIG. 7 is a timing diagram illustrating a second method of operating a memory according to an embodiment of the present disclosure;
FIG. 8 is a timing diagram illustrating a method of operating a memory according to an embodiment of the present disclosure;
FIG. 9 is a timing diagram illustrating a method of operation of a memory according to an embodiment of the present disclosure;
FIG. 10 is a schematic diagram illustrating a memory system according to an embodiment of the present disclosure;
FIG. 11a is a schematic diagram illustrating a memory card according to an embodiment of the present disclosure;
FIG. 11b shows a schematic diagram of a Solid State Drive (SSD) in accordance with an embodiment of the present disclosure;
FIG. 12 is a schematic diagram illustrating a memory according to an embodiment of the present disclosure;
FIG. 13 is a partial cross sectional view of an array of memory cells including NAND memory strings in accordance with an embodiment of the present disclosure;
fig. 14 is a block diagram illustrating a memory including a memory cell array and peripheral circuitry according to an embodiment of the disclosure.
Detailed Description
The technical solutions of the present disclosure will be further explained in detail with reference to the drawings and examples. While exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The present disclosure is more particularly described in the following paragraphs with reference to the accompanying drawings by way of example. Advantages and features of the present disclosure will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present disclosure.
In the embodiments of the present disclosure, the terms "first", "second", and the like are used for distinguishing similar objects, and are not necessarily used for describing a particular order or sequence.
The technical solutions described in the embodiments of the present disclosure may be arbitrarily combined without conflict.
FIG. 1 is a partial cross-sectional view of a reservoir 10 shown in accordance with an exemplary embodiment. Referring to fig. 1, a memory 10 includes a substrate 11, a stacked structure on the substrate 11, and at least one channel structure 16 penetrating the stacked structure; the laminated structure includes: at least one bottom select gate (bsg) 12, at least one Word Line (WL) 14, and at least one top select gate (tsg) 15; a common source 17, extending through the stacked structure and coupled to the substrate 11, for dividing the stacked structure into a plurality of sub-blocks.
The stacked structure also includes at least one dummy word line, such as a dummy (dum) word line 13a (denoted as lower dummy word line 13a) located between the lower select gate line 12 and the word line 14. Also for example, a dummy word line 13b (denoted as an upper dummy word line 13b) is located between the word line 14 and the upper select gate line 15.
The memory string comprises a lower selection transistor, a memory cell, an upper selection transistor and at least one dummy memory cell which are connected in series, wherein the dummy memory cell can be positioned between the lower selection transistor and the memory cell; and/or, the dummy memory cell may also be located between the memory cell and the upper select transistor. For example, lower select gate line 12 is coupled to a lower select transistor, lower dummy word line 13a is coupled to a lower dummy memory cell, word line 14 is coupled to a memory cell, upper dummy word line 13b is coupled to an upper dummy memory cell, and upper select gate line 15 is coupled to an upper select transistor.
The substrate 11 includes: a first well region 11a, a second well region 11b, a third well region 11c and a fourth well region 11 d. Here, the doping types of the first well region 11a and the third well region 11c are the same, for example, both are P-type wells (P wells), and the doping concentrations of the first well region 11a and the third well region 11c may be the same or different. The doping types of the second well region 11b and the fourth well region 11d are the same, for example, both are N-type wells (nwell), the doping concentrations of the second well region 11b and the fourth well region 11d may be the same or different, in an example, the doping concentration of the fourth well region 11d is greater than the doping concentration of the second well region 11b, and the common source 17 is coupled to the fourth well region 11 d.
In a specific example, referring to fig. 2, the memory 10 includes 6 lower select gate lines (i.e., bsg0 to bsg 5), 4 lower dummy word lines 13a (i.e., dum0 to dum3), 252 word lines (i.e., WL0 to WL251), 4 upper dummy word lines 13b (i.e., dum4 to dum7), and 4 upper select gate lines (i.e., tsg0 to tsg3), i.e., the memory string includes 6 lower select transistors, 4 lower dummy memory cells, 252 memory cells, 4 upper dummy memory cells, and 4 upper select transistors connected in series in sequence, and the memory string is led out through an interconnection structure (including a first metal layer M1 and a second metal layer M2).
Fig. 3 is a timing diagram illustrating a method of operating a memory for programming the memory 10 shown in fig. 1 or 2, according to an example embodiment. Specifically, the method comprises the following steps: at t 1 To t 2 For a time period, a turn-on voltage (greater than the threshold voltage of the upper select transistor) is applied to the selected upper select gate line tsg (sel), and for a selected lowerSelect gate line bsg (sel) applies a turn-off voltage (e.g., ground voltage vss), pass voltages vpass to unselected word line WLn- (unsel) (i.e., the word line above the selected word line) and unselected word line WLn + (unsel) (i.e., the word line below the selected word line), bias voltages vbias to upper dummy word line dum-b and lower dummy word line dum-a, and a program voltage (vpe) to selected word line WLn (sel) to program selected memory cells in the selected memory string. Here, vpe is greater than vbias, which is greater than or equal to vpass.
At t 1 To t 2 For a time period, an off voltage is applied to the unselected upper select gate line tsg (unsel) and an off voltage is applied to the unselected lower select gate line bsg (unsel) to turn off the channel of the unselected memory string, i.e., to inhibit programming of the memory cells in the unselected memory string.
However, in the process of performing a programming operation on the memory, due to the coupling effect, parasitic capacitance exists between different conductive lines (as shown by a dashed line box in fig. 2), so that the voltage of a part of the conductive lines fluctuates, and the normal operation of the memory is affected. Here, the conductive line includes a lower select gate line, a dummy word line, a word line (including a selected word line and an unselected word line), an upper select gate line, a first metal layer, and a second metal layer.
Referring to fig. 3, during the process of charging the upper dummy word line dum-b to vbias, the coupling of the upper dummy word line dum-b to the unselected upper select gate line tsg (unsel) causes a large rise (Big spike) in the voltage of the unselected upper select gate line tsg (unsel), as shown by the arrow (r), which may cause the upper select transistor of the unselected memory string to turn on, thereby causing the memory cell in the unselected memory string to be programmed and causing program cross talk.
Similarly, during the process of charging the upper dummy word line dum-b to the bias voltage vbias, the coupling of the upper dummy word line dum-b to the selected upper select gate line tsg (sel) causes a large rise in the voltage of the selected upper select gate line tsg (sel), as indicated by the arrow, which causes the potential of the selected upper select gate line to rise, affecting the normal programming of the selected memory cell.
Referring to fig. 3, during the process of charging the lower dummy word line dum-a to vbias, the coupling of the lower dummy word line dum-a to the unselected lower select gate line bsg (unsel) causes a large increase in the voltage of the unselected lower select gate line bsg (unsel), as shown by arrow (c), which may cause the lower select transistor of the unselected memory string to turn on, thereby causing the memory cells in the unselected memory string to be programmed and causing program cross talk.
Similarly, during the process of charging the lower dummy word line dum-a to the bias voltage vbias, the coupling of the lower dummy word line dum-a to the selected lower select gate line bsg (sel) causes a large rise in the voltage of the selected lower select gate line bsg (sel), as indicated by arrow (r), which may cause the lower select transistor of the selected memory string to turn on, affecting the normal programming of the selected memory cell.
Fig. 4 is a waveform diagram illustrating an enable signal for controlling a dummy word line in a programming process according to an exemplary embodiment. Specifically, the method comprises the following steps: at t 1 At the moment, the first enable signal vdd _ en is at Low level (L), the second enable signal vss _ en falls from High level (H) to Low level, and the third enable signal vbias _ en rises from Low level to High level, that is, at t 1 At this point, dum (e.g., dum-a) is rapidly charged by the third enable signal vbias _ en from vss to vdd (as shown by the dashed box in fig. 4), resulting in an increased coupling of dum-a to bsg (unsel) and/or bsg (sel), which in turn results in a large increase in the voltage of bsg (unsel) and/or bsg (sel) as shown in fig. 3.
In view of the above, the embodiments of the present disclosure provide a method for operating a memory.
FIG. 5 is a flow chart illustrating a method of operation of a memory according to an embodiment of the present disclosure. Referring to fig. 5, the method includes at least the following steps:
s110: charging the first dummy word line to a first voltage in a first charge phase of a program operation; wherein the first dummy word line is located between the upper select gate line and the word line, and/or the first dummy word line is located between the lower select gate line and the word line;
s120: charging the first dummy word line from the first voltage to a second voltage in a second charge phase of the programming operation; the second charging stage is positioned after the first charging stage, and the charging rate of the first charging stage is less than or equal to that of the second charging stage;
s130: after the second charge phase, charging a selected one of the word lines to a program voltage; wherein the programming voltage is greater than the second voltage.
In the embodiment of the disclosure, the first dummy word line is charged to the first voltage in the first charging stage of the programming operation, and the first dummy word line is charged from the first voltage to the second voltage in the second charging stage of the programming operation, so that the charging process of the first dummy word line is divided into two stages, and the charging rate of the first charging stage is less than or equal to the charging rate of the second charging stage, the boosting rate of the first dummy word line can be better controlled, the parasitic capacitance between the first dummy word line and the upper selection gate line and/or the parasitic capacitance between the first dummy word line and the lower selection gate line can be reduced, and the coupling effect of the first dummy word line on the upper selection gate line and/or the lower selection gate line can be further reduced.
Furthermore, the coupling effect of the first dummy word line on the upper selection grid line and/or the lower selection grid line is reduced, so that the probability that the voltage of the upper selection grid line and/or the voltage of the lower selection grid line greatly rises in the programming process is reduced, and the normal operation of the programming operation of the memory is ensured.
In some embodiments, the above method further comprises: charging unselected ones of the word lines to a pass voltage in a first charging phase and a second charging phase; the passing voltage is greater than the first voltage and less than or equal to the second voltage;
the step S110 includes: performing a first floating operation on the first dummy word line; wherein the unselected word line couples the floating first dummy word line to the first voltage during the unselected word line charging to the pass voltage.
Illustratively, referring to FIG. 6, at t 1 To t 13 Time period, will notThe selected word line WL charges to the pass voltage vpass. Here, t 1 To t 13 The time period includes t 1 To t 11 Time period (i.e., first charging phase) and t 11 To t 13 Time period (i.e., second charging phase).
At t 1 To t 11 During the time period, the unselected word line WL couples the floating first dummy word line dum1 to the first voltage vdd, at t 11 To t 13 During the time period, the first dummy word line dum1 is charged from the first voltage vdd to the second voltage vbias. Here, the pass voltage vpass is greater than the first voltage vdd, and the pass voltage vpass is less than or equal to the second voltage vbias.
It should be noted that, during the process of floating the first dummy word line, the voltage of the first dummy word line changes with the change of the word line voltage, for example, in the first charging phase, as the word line voltage increases, the voltage of the floating first dummy word line increases, and the boosting rate of the first dummy word line in the first charging phase is smaller than or equal to the boosting rate of the first dummy word line in the second charging phase.
In practical applications, a plurality of word lines (including selected word lines and unselected word lines) in the memory are typically charged to a pass voltage in the first charging phase and the second charging phase. Preferably, word lines adjacent to the first dummy word line couple the floating first dummy word line to the first voltage. For example, when a first dummy word line is located between the upper select gate line and the word line, word lines located below and adjacent to the first dummy word line couple the floating first dummy word line to a first voltage; and/or when the first dummy word line is between the lower select gate line and the word line, word lines above and adjacent to the first dummy word line couple the floating first dummy word line to a first voltage.
In the embodiment of the disclosure, through charging the unselected word lines to the pass voltage in the first charging stage and the second charging stage, and performing the first floating operation on the first dummy word line in the first charging stage, the floating first dummy word line is coupled to the first voltage by using the unselected word line, so that the boosting rate of the first dummy word line can be better controlled, the coupling effect of the first dummy word line on the upper selection gate line and/or the lower selection gate line is favorably reduced, the probability of fluctuation of the upper selection gate line and/or the lower selection gate line in the programming process is further reduced, and the normal operation of the memory programming operation is ensured.
In addition, by performing the first floating operation on the first dummy word line in the first charge stage, it is advantageous to reduce power consumption of a memory program operation.
In some embodiments, the above method further comprises: a first floating operation is performed on the first dummy word line prior to the first charge phase.
Illustratively, referring to FIG. 6, at t 01 To t 1 In time period, the first dummy word line dum1 is floated, i.e., the first dummy word line dum1 is floated before the word line WL is charged.
Still referring to FIG. 6, at t 01 At this time, the first enable signal vdd _ en is low, the second enable signal vss _ en is lowered from high to low, and the third enable signal vbias _ en is low, i.e., the first dummy word line dum1 starts to float. At t 11 At this time, the first enable signal vdd _ en is at a low level, the second enable signal vss _ en is at a low level, and the third enable signal vbias _ en is raised from a low level to a high level, i.e., the first dummy word line ends to float and starts to be charged.
At the same time (i.e., t) 1 At that moment), lowering the second enable signal vss _ en from a high level to a low level and raising the third enable signal vbias _ en from a low level to a high level requires a more complex circuit design.
In the embodiment of the disclosure, the first dummy word line is floated before the first charging stage, different enable signals can be switched at different times, and the coupling effect of the first dummy word line on the upper selection gate line and/or the lower selection gate line is favorably reduced while the complexity of circuit design is not increased.
In some embodiments, the above method further comprises: performing a second floating operation on the second dummy word line in the first charge stage; wherein the unselected word line couples the floating second dummy word line to the first voltage during the unselected word line charging to the pass voltage; the second dummy word line is located between the word line and the first dummy word line, and a floating time period of the second floating operation is different from a floating time period of the first floating operation.
In one example, as shown with reference to FIG. 7, at t 1 From to t 11 In time periods, the unselected word line WL couples the floating second dummy word line dum2 to the first voltage. In another example, as shown with reference to FIG. 8, at t 1 To t 11 In the' time period, the unselected word line WL couples the floating second dummy word line dum2 to the first voltage. It should be understood that the floating time period of the second dummy word line is less than the floating time period of the first dummy word line, i.e., the floating time period of the first floating operation is greater than the floating time period of the second floating operation.
In one example, the first and second dummy word lines are located between the upper select gate line and the word line, and the first dummy word line is located between the second dummy word line and the upper select gate line, i.e., the first dummy word line is relatively close to the upper select gate line and the second dummy word line is relatively far from the upper select gate line. The coupling effect of the first dummy word line to the upper select gate line is greater than the coupling effect of the second dummy word line to the upper select gate line. Different dummy word lines are controlled differently by floating a first dummy word line relatively close to an upper select gate line for a relatively long time and floating a second dummy word line relatively far from the upper select gate line for a relatively short time. In this example, a word line adjacent to the second dummy word line couples the floating second dummy word line to the first voltage. For example, a word line that is located below and adjacent to the second dummy word line couples the floated second dummy word line to the first voltage.
In one example, the first and second dummy word lines are located between the lower select gate line and the word line, and the first dummy word line is located between the second dummy word line and the lower select gate line, i.e., the first dummy word line is relatively close to the lower select gate line and the second dummy word line is relatively far from the lower select gate line. The coupling effect of the first dummy word line to the lower select gate line is greater than the coupling effect of the second dummy word line to the lower select gate line. Different dummy word lines are controlled differently by floating a first dummy word line relatively close to the lower select gate line for a relatively long time and floating a second dummy word line relatively far from the lower select gate line for a relatively short time. In this example, a word line adjacent to the second dummy word line couples the floating second dummy word line to the first voltage. For example, a word line located above and adjacent to the second dummy word line couples the floated second dummy word line to the first voltage.
It should be noted that the first dummy word line and the second dummy word line are merely examples and are used to convey the disclosure. In other embodiments, the memory may further include a third dummy word line, a fourth dummy word line, etc., which may float for different lengths of time in the memory, and the disclosure is not limited thereto.
In the embodiment of the disclosure, by performing the first floating operation on the first dummy word line and performing the second floating operation on the second dummy word line in the first charging stage, and the floating duration of the second floating operation is different from the floating duration of the first floating operation, the first dummy word line and the second dummy word line can be floated for different durations according to the difference of the coupling effect of the first dummy word line and the second dummy word line on the upper selection gate line and/or the lower selection gate line, which is beneficial to achieving better control of the first dummy word line and the second dummy word line.
In some embodiments, the performing the first floating operation on the first dummy word line includes:
starting to perform a first floating operation on a first dummy word line at a first time;
ending the first floating operation on the first dummy word line at a second time;
the performing the second floating operation on the second dummy word line in the first charging phase includes:
after the first time and before the second time, starting to perform a second floating operation on the second dummy word line;
at a second time, the second floating operation performed on the second dummy word line is ended.
In an exemplary manner, the first and second electrodes are,as shown with reference to fig. 7, may be at t 1 At time, the first dummy word line dum1 begins to float, at t 11 At time, the floating of the first dummy word line dum1 ends. Can be at t 1 At time, the second dummy word line dum2 begins to float, at t 11 At time, the floating of the second dummy word line dum2 ends. Here, t 1 ＜t 1 ’＜t 11 。
It is to be understood that, in the present example, the first dummy word line and the second dummy word line start floating at different times and end floating at the same time, that is, the floating time period of the second floating operation and the floating time period of the first floating operation are controlled to be different by controlling the start time of the first dummy word line performing the floating operation and the start time of the second dummy word line performing the floating operation to be different.
In some embodiments, the performing the first floating operation on the first dummy word line includes:
starting to perform a first floating operation on a first dummy word line at a first time;
ending the first floating operation on the first dummy word line at a second time;
the performing the second floating operation on the second dummy word line in the first charging phase includes:
starting to perform a second floating operation on the second dummy word line at a first time;
the second floating operation performed on the second dummy word line is ended before the second timing.
Illustratively, as shown with reference to FIG. 8, may be at t 1 At time, the first dummy word line dum1 begins to float, at t 11 At time, the floating of the first dummy word line dum1 ends. Can be at t 1 At time, the second dummy word line dum2 begins to float at t 11 At time, floating the second dummy word line dum2 ends. Here, t 1 ＜t 11 ’＜t 11 。
It is to be understood that, in the present example, the first dummy word line and the second dummy word line start floating at the same time and end floating at different times, that is, the floating time period of the second floating operation and the floating time period of the first floating operation are controlled to be different by controlling the end time of the first dummy word line performing the floating operation and the end time of the second dummy word line performing the floating operation to be different.
In some embodiments, step S110 includes: performing a charging operation on the first dummy word line at a first time to a second time to charge the first dummy word line to a first voltage;
step S120, including: charging the first dummy word line from the first voltage to the second voltage at third to fourth times;
the method further comprises the following steps: the first dummy word line is held at the first voltage at the second to third timings.
Illustratively, as shown with reference to FIG. 9, at t 1 (i.e., first time) to t 11 (i.e., a second time) the first dummy word line dum1 is charged from vss to the first voltage vdd, at t 11 To t 12 (i.e., a third time) the first dummy word line dum1 is held at the first voltage vdd for a time period t 12 To t 13 (i.e., a fourth time) the first dummy word line dum1 is charged from the first voltage vdd to the second voltage vbias.
In some embodiments, the first charging phase comprises a first time to a second time, and the second charging phase comprises a third time to a fourth time. The charge rate of the first dummy word line from the first time to the second time is less than or equal to the charge rate of the first dummy word line from the third time to the fourth time.
It can be appreciated that, in this example, the first dummy word line is charged to the second voltage, and the first charge phase, the second charge phase and the hold phase between the first charge phase and the second charge phase are included, so that the boosting rate of the first dummy word line can be better controlled, which is beneficial to reducing the coupling effect of the first dummy word line on the upper selection gate line and/or the lower selection gate line, further reducing the probability of the fluctuation of the upper selection gate line and/or the lower selection gate line in the programming process, and ensuring the normal operation of the memory programming.
In some embodiments, in charging a first dummy word line between the upper select gate line and the word line to a first voltage, the method further comprises: applying a turn-on voltage to an upper select gate line coupled to the selected memory string and applying a turn-off voltage to a lower select gate line coupled to the selected memory string, an upper select gate line of an unselected memory string, and a lower select gate line of an unselected memory string;
and/or the presence of a gas in the gas,
in charging a first dummy word line between a lower select gate line and a word line to a first voltage, the method further includes: an on voltage is applied to an upper select gate line coupled to the selected memory string, and an off voltage is applied to a lower select gate line coupled to the selected memory string, an upper select gate line of the unselected memory string, and a lower select gate line of the unselected memory string.
Applying a turn-on voltage to an upper select gate line coupled to the selected memory string and a turn-off voltage to a lower select gate line coupled to the selected memory string to program a selected memory cell in the selected memory string in a first charge phase and a second charge phase; a turn-off voltage is applied to an upper select gate line coupled to an unselected memory string and a lower select gate line coupled to the unselected memory string to turn off a channel of the unselected memory string, i.e., inhibit programming of memory cells in the unselected memory string.
In one example, the first dummy word line is located between the upper selection gate line (including the upper selection gate line of the selected memory string and the upper selection gate line of the unselected memory string) and the word line, and the charging process of the first dummy word line is divided into two stages, and the charging rate of the first charging stage is less than or equal to the charging rate of the second charging stage, so that the coupling effect of the first dummy word line on the upper selection gate line can be reduced, the influence on the programming of the selected memory cell can be reduced, the probability of the programming of the memory cells in the unselected memory string can be reduced, and the probability of the occurrence of the programming crosstalk can be reduced.
In one example, the first dummy word line is located between the lower selection gate line (including the lower selection gate line of the selected memory string and the lower selection gate line of the unselected memory string) and the word line, and the charging process of the first dummy word line is divided into two stages, and the charging rate of the first charging stage is less than or equal to the charging rate of the second charging stage, so that the coupling effect of the first dummy word line on the lower selection gate line can be reduced, the influence on the programming of the selected memory cell can be reduced, the probability of the programming of the memory cells in the unselected memory string can be reduced, and the probability of the occurrence of the programming crosstalk can be reduced.
In some embodiments, the above method further comprises: the first dummy word line is held at the second voltage during the charging of the selected word line to the programming voltage.
Illustratively, as shown in connection with FIG. 6, at t 1 To t 2 In this time period, the selected word line and the unselected word lines are charged to the pass voltage, and after a certain period of time, the selected word line is charged from the pass voltage to the program voltage, the unselected word lines are maintained at the pass voltage vpass, and the first dummy word line dum1 is maintained at the second voltage vbias, so as to complete the programming of the selected memory cell. Here, the program voltage is greater than the second voltage vbias.
It will be appreciated that in this example, the charging of the selected word line is performed in two phases, i.e., first charging to the pass voltage and then maintaining for a certain period of time and then recharging to the programming voltage, and in other embodiments, it may also be performed at t 1 To t 2 In a time period, a selected word line is directly charged to a program voltage to program a selected memory cell.
In some embodiments, the program operation includes a plurality of program loops; the method further comprises the following steps:
charging a first dummy word line to a first voltage during a first charge phase of each programming cycle;
the first dummy word line is charged from the first voltage to a second voltage during a second charge phase of each programming cycle.
In an example, a first floating operation may be performed on a first dummy word line to charge the first dummy word line to a first voltage during a first charge phase of each program cycle.
In another example, a charge operation may be performed on the first dummy word line to charge the first dummy word line to a first voltage during a first charge phase of each program cycle.
In yet another example, a first floating operation may be performed on a first dummy word line to charge the first dummy word line to a first voltage during a first charge phase of a portion of a programming cycle; in a first charge phase of another portion of the programming cycle, a charge operation may be performed on the first dummy word line to charge the first dummy word line to a first voltage.
In a programming operation, a memory cell to be programmed can be programmed to a target state by executing a plurality of programming cycles, and the charging of the first dummy word line in each programming cycle can be better controlled by charging the first dummy word line to a first voltage in a first charging phase of each programming cycle and charging the first dummy word line from the first voltage to a second voltage in a second charging phase of each programming cycle, which is beneficial to reducing the coupling effect of the first dummy word line on an upper selection grid line and/or a lower selection grid line in each programming cycle.
FIG. 10 is a schematic diagram illustrating a memory system 100 according to an embodiment of the disclosure. Referring to fig. 10, the memory system 100 includes:
one or more memories 103;
a memory controller 104 coupled to the memory 103 and configured to control the memory 103.
System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, Virtual Reality (VR) device, Augmented Reality (AR) device, or any other suitable electronic device having storage therein.
As shown in fig. 10, the system 100 may include a host 101 and a storage subsystem 102, the storage subsystem 102 having one or more memories 103, the storage subsystem further including a memory controller 104. The host 101 may be a processor (e.g., a Central Processing Unit (CPU)) or a system on chip (SoC) (e.g., an Application Processor (AP)) of an electronic device. The host 101 may be configured to send data to the memory 103. Alternatively, the host 101 may be configured to receive data from the memory 103.
Memory 103 may be any memory device disclosed in the present disclosure. The memory 103 may be a NAND flash memory device (e.g., a three-dimensional (3D) NAND flash memory device, which may have reduced leakage current from a drive transistor (e.g., a string driver) coupled to unselected word lines during an erase operation, which allows for further scaling of the drive transistor.
In some embodiments, memory controller 104 is also coupled to host 101. The memory controller 104 may manage data stored in the memory 103 and communicate with the host 101.
In some embodiments, the memory controller 104 is designed for operation in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other medium for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like.
In some embodiments, the memory controller 104 is designed for operation in a high duty cycle environment Solid State Disk (SSD) or embedded multimedia card (eMMC) that serves as a data storage and enterprise storage array for mobile devices such as smart phones, tablet computers, laptop computers, and the like.
The memory controller 104 may be configured to control operations of the memory 103, such as read, erase, and program operations. The memory controller 104 may also be configured to manage various functions with respect to data stored or to be stored in the memory 103, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like. In some implementations, the memory controller 104 is also configured to process Error Correction Codes (ECC) with respect to data read from the memory 103 or written to the memory 103.
The memory controller 104 may also perform any other suitable functions, such as formatting the memory 103. The memory controller 104 may communicate with external devices (e.g., the host 101) according to a particular communication protocol. For example, the memory controller 104 may communicate with the external device via at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system small interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and so forth.
The memory controller 104 and the one or more memories 103 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 100 may be implemented and packaged into different types of terminal electronics.
In one example as shown in fig. 11a, the memory controller 104 and the single memory 103 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, and the like. Memory card 202 may also include a memory card connector 204 that couples memory card 202 with a host (e.g., host 101 in FIG. 10).
In another example as shown in fig. 11b, the memory controller 104 and the plurality of memories 103 may be integrated into a Solid State Drive (SSD) 206. The solid state drive 206 may also include a solid state drive connector 208 that couples the solid state drive 206 with a host (e.g., host 101 in fig. 10). In some implementations, the storage capacity and/or operating speed of the solid state drive 206 is greater than the storage capacity and/or operating speed of the memory card 202.
It is understood that the memory controller 104 may perform the method of operation as provided by any of the embodiments of the present disclosure.
Fig. 12 is a schematic diagram illustrating a memory 300 according to an embodiment of the disclosure. Referring to fig. 12, the memory 300 includes:
a memory cell array 301, comprising:
word line 318, word line 318 located between upper select gate line 311 and lower select gate line 315;
a first dummy word line 322, the first dummy word line 322 being located between the upper select gate line 311 and the word line 318, and/or the first dummy word line 322 being located between the lower select gate line 315 and the word line 318;
peripheral circuitry 302 coupled to the memory cell array 301; wherein the content of the first and second substances,
the peripheral circuitry 302 is configured to charge the first dummy word line 322 to a first voltage during a first charge phase of a programming operation;
the peripheral circuitry 302 is further configured to charge the first dummy word line 322 from the first voltage to a second voltage during a second charge phase of the programming operation; the second charging stage is positioned after the first charging stage, and the charging rate of the first charging stage is less than or equal to that of the second charging stage;
the peripheral circuitry 302 is further configured to charge selected ones of the word lines to the programming voltage after the second charge phase; wherein the programming voltage is greater than the second voltage.
The memory cell array 301 may be a NAND flash memory cell array, wherein the memory cell array 301 is provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown).
In some implementations, each NAND memory string 308 includes multiple memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, e.g., a voltage or charge, that depends on the number of electrons trapped within the area of the memory cell 306. Each memory cell 306 may be a floating gate type memory cell including a floating gate transistor or a charge trapping type memory cell including a charge trapping transistor.
In some embodiments, each memory cell 306 is a single level cell having two possible memory states and thus can store one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range.
In some embodiments, each memory cell 306 is a cell capable of storing more than a single bit of data in more than four memory states. For example, two bits per cell (also referred to as a multilevel cell), three bits per cell (also referred to as a three level cell), or four bits per cell (also referred to as a four level cell) may be stored. Each multilevel cell can be programmed to assume a range of possible nominal storage values. In one example, if each multi-level cell stores two bits of data, the multi-level cell may be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values to the cell. The fourth nominal storage value may be used for the erased state.
As shown in FIG. 12, each NAND memory string 308 can include a lower select gate 310 at its source terminal and an upper select gate 312 at its drain terminal. The lower select gate 310 and the upper select gate 312 can be configured to activate a selected NAND memory string 308 (column of the array) during read and program operations. Each NAND memory string 308 can also include a first dummy memory cell 321, the first dummy memory cell 321 being located between the upper select gate 312 and the memory cell 306.
It should be noted that fig. 12 only shows the case where the first dummy word line 322 is located between the upper select gate line 311 and the word line 318, and the first dummy memory cell 321 is located between the upper select gate 312 and the memory cell 306. In other embodiments, however, the first dummy word line 322 may also be located between the lower select gate line 315 and the word line 318, with the first dummy memory cell 321 located between the lower select gate 310 and the memory cell 306.
In some embodiments, the sources of NAND memory strings 308 in the same memory block 304 are coupled by the same Source Line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all of the NAND memory strings 308 in the same memory block 304 have an Array Common Source (ACS).
In some embodiments, the upper select gate 312 of each NAND memory string 308 is coupled to a respective bit line 316, and data can be read from or written to the bit line 316 via an output bus (not shown).
In some embodiments, each NAND memory string 308 is configured by applying a select voltage (e.g., above the threshold voltage of the transistor having the upper select gate 312) or a deselect voltage (e.g., 0V) to the respective upper select gate 312 via one or more upper select gate lines 311. And/or, in some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., above the threshold voltage of the transistor having the lower select gate 310) or a deselect voltage (e.g., 0V) to the respective lower select gate 310 via one or more lower select gate lines 315.
As shown in fig. 12, the NAND memory strings 308 may be organized into a plurality of memory blocks 304, each of the plurality of memory blocks 304 may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic unit of data for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased at the same time. To erase memory cells 306 in a selected block of storage regions, the source lines coupled to the selected block of storage regions and unselected block storage regions in the same storage plane as the selected block of storage regions may be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)).
It should be appreciated that in some examples, the erase operation may be performed at a half block level, at a quarter block level, or at any suitable fraction of a number of blocks or blocks. The memory cells 306 of adjacent NAND memory strings 308 may be coupled by a word line 318, the word line 318 selecting which row of memory cells 306 is affected by read and program operations.
In some embodiments, each word line 318 is coupled to a memory page 320 of memory cells 306, the memory page 320 being the basic unit of data for a programming operation. The size of a page 320 of memory in bits may be related to the number of NAND memory strings 308 coupled by a word line 318 in a memory block 304. Each word line 318 may include a plurality of control gates (gate electrodes) at each memory cell 306 in a respective memory page 320 and a gate line coupling the control gates. It is understood that a row of memory cells is a plurality of memory cells 306 located in the same memory page 320.
Fig. 13 illustrates a side view of a cross section of an example memory cell array 301 including NAND memory strings 308 in accordance with some aspects of the present disclosure. As shown in fig. 13, the NAND memory strings 308 may extend vertically through the memory stack layer 404 over the substrate 402. Substrate 402 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.
Memory stack 404 may include alternating gate conductive layers 406 and gate dielectric layers 408. The number of pairs of gate conductive layers 406 and gate dielectric layers 408 in the memory stack layer 404 may determine the number of memory cells 306 in the memory cell array 301.
The gate conductive layer 406 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 406 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 406 comprises a doped polysilicon layer. Each gate conductive layer 406 may include a control gate surrounding a memory cell 306, and may laterally extend at the top of the memory stack layer 404 as an upper select gate line 311, at the bottom of the memory stack layer 404 as a lower select gate line 315, or between the upper select gate line 311 and the lower select gate line 315 as a word line 318.
As shown in fig. 13, NAND memory string 308 includes a channel structure 412 that extends vertically through memory stack 404. In some embodiments, the channel structure 412 includes a channel hole filled with semiconductor material(s) (e.g., as a semiconductor channel 420) and dielectric material(s) (e.g., as a storage film 418). In some embodiments, the semiconductor channel 420 comprises silicon, e.g., polysilicon. In some embodiments, storage film 418 is a composite dielectric layer that includes a tunneling layer 426, a storage layer 424 (also referred to as a "charge trapping/storage layer"), and a blocking layer 422. The channel structure 412 may have a cylindrical shape (e.g., a pillar shape). In some embodiments, the semiconductor channel 420, the tunneling layer 426, the storage layer 424, and the blocking layer 422 are arranged radially from the center of the cylinder toward the outer surface of the cylinder in this order. The tunneling layer 426 may include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer 424 may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 422 may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the storage film 418 may include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).
In some embodiments, as shown in fig. 13, a well 414 (e.g., a P-well and/or an N-well) is formed in the substrate 402 and the source terminal of the NAND memory string 308 is in contact with the well 414. For example, the source line 314 may be coupled to the well 414 to apply an erase voltage to the well 414 (i.e., the source of the NAND memory string 308) during an erase operation. In some embodiments, the NAND memory string 308 also includes a channel plug 416 at the drain end of the NAND memory string 308. It should be understood that although not shown in fig. 13, additional components of the memory cell array 301 may be formed, including but not limited to gate line apertures/source contacts, local contacts, interconnect layers, and the like.
In some embodiments, the peripheral circuitry 302 is further configured to charge unselected ones of the word lines 318 to a pass voltage during the first and second charge phases; the passing voltage is greater than the first voltage and less than or equal to the second voltage;
the peripheral circuit 302 is configured to charge the first dummy word line 322 to a first voltage during a first charge phase of a programming operation, including:
the peripheral circuit 302 is configured to perform a first floating operation on the first dummy word line 322; wherein the unselected word line couples the floating first dummy word line 318 to the first voltage during the charging of the unselected word line 318 to the pass voltage by the peripheral circuit 302.
In some embodiments, the memory cell array further comprises:
a second dummy word line 324, the second dummy memory cell 323 being located between the memory cell 306 and the first dummy memory cell 321, the second dummy word line 324 being located between the word line 318 and the first dummy word line 322;
the peripheral circuitry 302 is further configured to perform a second floating operation on the second dummy word line 324 during the first charge phase; wherein, during the charging of the unselected word line 318 to the pass voltage by the peripheral circuitry 302, the unselected word line 318 couples the floating second dummy word line 324 to the first voltage; the floating time period of the second floating operation is different from the floating time period of the first floating operation.
In some embodiments, peripheral circuitry 302 is specifically configured to:
at a first time, a first floating operation is started on the first dummy word line 322; at a second time, the first floating operation on the first dummy word line 322 is finished;
after the first time, and before the second time, the second floating operation is started to be performed on the second dummy word line 324; at a second time, the second floating operation on the second dummy word line 324 is finished.
In some embodiments, peripheral circuitry 302 is specifically configured to:
at a first time, a first floating operation is started on the first dummy word line 322; at a second time, the first floating operation on the first dummy word line 322 is finished;
at the first timing, the second floating operation is started to be performed on the second dummy word line 324; before the second time, the second floating operation on the second dummy word line 324 is finished.
In some embodiments, the peripheral circuitry 302 is configured to charge the first dummy word line 322 to a first voltage during a first charge phase of a programming operation, including: at first to second times, the peripheral circuit 302 charges the first dummy word line 322 to a first voltage;
the peripheral circuit 302 is further configured to charge the first dummy word line from the first voltage to a second voltage during a second charge phase of the programming operation, including: at the third to fourth times, the peripheral circuit 302 charges the first dummy word line 322 from the first voltage to the second voltage;
the peripheral circuitry 302 is also configured to hold the first dummy word line 322 at the first voltage from the second time to the third time.
In some embodiments, while the peripheral circuitry 302 is configured to charge the first dummy word line 322 located between the upper select gate line 311 and the word line 318 to the first voltage, the peripheral circuitry 302 is further configured to: applying a turn-on voltage to the upper select gate line 311 coupled to the selected memory string and applying a turn-off voltage to the lower select gate line 315 coupled to the selected memory string, the upper select gate line 311 of the unselected memory string, and the lower select gate line 315 of the unselected memory string;
and/or the presence of a gas in the gas,
while the peripheral circuitry 302 is configured to charge the first dummy word line 322 located between the lower select gate line 315 and the word line 318 to the first voltage, the peripheral circuitry 302 is further configured to: an on voltage is applied to the upper select gate line 311 coupled to the selected memory string, and an off voltage is applied to the lower select gate line 315 coupled to the selected memory string, the upper select gate line 311 of the unselected memory string, and the lower select gate line 315 of the unselected memory string.
In some embodiments, the peripheral circuitry 302 is further configured to: during the charging of the selected word line 318 to the programming voltage, the first dummy word line 322 is held at the second voltage.
In some embodiments, the program operation includes a plurality of program loops; the peripheral circuitry 302 is configured to charge the first dummy word line 322 to a first voltage during a first charge phase of each programming cycle;
the peripheral circuitry 302 is also configured to charge the first dummy word line 322 from the first voltage to a second voltage during a second charge phase of each programming cycle.
Referring to fig. 12, the peripheral circuit 302 may be coupled to the memory cell array 301 through a bit line 316, a word line 318, a dummy word line (including a first dummy word line 322 and a second dummy word line 324), a source line 314, a select gate line (including a lower select gate line 315 and an upper select gate line 311). The peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of the memory cell array 301 by applying and sensing voltage and/or current signals to and from each target memory cell 306 via the bit line 316, word line 318, first dummy word line 322, second dummy word line 324, source line 314, lower select gate line 315, and upper select gate line 311 to each target memory cell 306.
The peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, fig. 14 shows some exemplary peripheral circuits 302, the peripheral circuits 302 including page buffers/sense amplifiers 504, column decoders/Bit Line (BL) drivers 506, row decoders/Word Line (WL) drivers 508, voltage generators 510, control logic 512, registers 514, interfaces 516, and a data bus 518. It should be understood that additional peripheral circuitry not shown in fig. 14 may also be included in some examples.
The page buffer/sense amplifier 504 may be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic unit 512. In one example, the page buffer/sense amplifier 504 may store a page of program data (write data) to be programmed into one memory page 320 of the memory cell array 301. In another example, the page buffer/sense amplifier 504 may perform a program verify operation to ensure that data has been properly programmed into the memory cells 306 coupled to the selected word line 318. In yet another example, page buffer/sense amplifier 504 may also sense low power signals from bit line 316 representing data bits stored in memory cells 306 and amplify small voltage swings to recognizable logic levels in a read operation. The column decoder/bit line driver 506 may be configured to be controlled by the control logic unit 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from the voltage generator 510.
The row decoder/word line driver 508 may be configured to be controlled by the control logic unit 512 and to select/deselect a memory block 304 of the memory cell array 301 and to select/deselect a word line of the memory block 304318. The row decoder/word line driver 508 may also be configured to use the word line voltage (V) generated from the voltage generator 510 WL ) To drive word line 318. In some embodiments, the row decoder/word line driver 508 may also select/deselect and drive the lower select gate line 315 and the upper select gate line 311. As described in detail below, the row decoder/word line driver 508 is configured to perform an erase operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 may be configured to be controlled by the control logic unit 512 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verify voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array 301.
The control logic unit 512 may be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. The registers 514 may be coupled to the control logic unit 512 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. Interface 516 may be coupled to control logic unit 512 and act as a control buffer to buffer and relay control commands received from a host (not shown) to control logic unit 512 and to buffer and relay status information received from control logic unit 512 to the host. The interface 516 may also be coupled to the column decoder/bit line drivers 506 via a data bus 518 and act as a data I/O interface and data buffer to buffer data and relay it to the memory cell array 301 or to relay or buffer data from the memory cell array 301.
It is emphasized that peripheral circuitry 302 is configured to perform the control methods provided by the embodiments of the present disclosure on selected ones of the plurality of rows of memory cells.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (19)

1. A method of operating a memory, comprising:
charging the first dummy word line to a first voltage during a first charge phase of a program operation; wherein the first dummy word line is located between the upper select gate line and the word line, and/or the first dummy word line is located between the lower select gate line and the word line;
charging the first dummy word line from the first voltage to a second voltage in a second charge phase of the programming operation; wherein the second charging phase is located after the first charging phase, and the charging rate of the first charging phase is less than or equal to the charging rate of the second charging phase;
after the second charge phase, charging selected ones of the word lines to a programming voltage; wherein the programming voltage is greater than the second voltage.
2. The method of claim 1, further comprising: charging unselected ones of the word lines to a pass voltage in the first and second charge phases; wherein the pass voltage is greater than the first voltage and less than or equal to the second voltage;
the charging the first dummy word line to a first voltage during a first charge phase of a programming operation, comprising:
performing a first floating operation on the first dummy word line; wherein the unselected word line couples the floating first dummy word line to the first voltage during the charging of the unselected word line to the pass voltage.
3. The method of claim 2, further comprising:
performing a second floating operation on a second dummy word line in the first charge phase; wherein the unselected word line couples the floating second dummy word line to the first voltage during the charging of the unselected word line to the pass voltage; the second dummy word line is located between the word line and the first dummy word line, and a floating duration of the second floating operation is different from a floating duration of the first floating operation.
4. The method of claim 3,
the performing a first floating operation on the first dummy word line includes:
starting to perform the first floating operation on the first dummy word line at a first time;
ending performing the first floating operation on the first dummy word line at a second time;
the performing, in the first charge phase, a second floating operation on a second dummy word line includes:
after the first time, and before the second time, beginning to perform the second floating operation on the second dummy word line;
ending the second floating operation on the second dummy word line at the second time.
5. The method of claim 3,
the performing a first floating operation on the first dummy word line includes:
starting to perform the first floating operation on the first dummy word line at a first time;
ending the first floating operation on the first dummy word line at a second time;
the performing, in the first charge phase, a second floating operation on a second dummy word line includes:
starting to perform the second floating operation on the second dummy word line at the first timing;
ending the second floating operation on the second dummy word line before the second time.
6. The method of claim 1, wherein charging the first dummy word line to the first voltage during the first charge phase of the programming operation comprises:
performing a charging operation on the first dummy word line at a first time to a second time to charge the first dummy word line to the first voltage;
the charging the first dummy word line from the first voltage to a second voltage in a second charge phase of the programming operation, comprising:
charging the first dummy word line from the first voltage to the second voltage at a third time to a fourth time;
the method further comprises the following steps: maintaining the first dummy word line at the first voltage at the second to third times.
7. The method of claim 1,
in charging a first dummy word line between the upper select gate line and the word line to the first voltage, the method further includes: applying a turn-on voltage to an upper select gate line coupled to the selected memory string and applying a turn-off voltage to a lower select gate line coupled to the selected memory string, an upper select gate line of an unselected memory string, and a lower select gate line of an unselected memory string;
and/or the presence of a gas in the gas,
in charging a first dummy word line between the lower select gate line and the word line to the first voltage, the method further includes: an on voltage is applied to an upper select gate line coupled to the selected memory string, and an off voltage is applied to a lower select gate line coupled to the selected memory string, an upper select gate line of the unselected memory string, and a lower select gate line of the unselected memory string.
8. The method of claim 1, further comprising:
maintaining the first dummy word line at the second voltage during charging of the selected word line to a programming voltage.
9. The method of claim 1, wherein the programming operation comprises a plurality of programming cycles; the method further comprises the following steps:
charging the first dummy word line to the first voltage during a first charge phase of each programming cycle;
charging the first dummy word line from the first voltage to the second voltage during a second charge phase of each programming cycle.
10. A memory, comprising:
a memory cell array comprising:
a word line between upper and lower select gate lines;
a first dummy word line between the upper select gate line and the word line, and/or between the lower select gate line and the word line;
peripheral circuitry coupled to the array of memory cells; wherein the content of the first and second substances,
the peripheral circuitry is configured to charge the first dummy word line to a first voltage during a first charge phase of a programming operation;
the peripheral circuitry is further configured to charge the first dummy word line from the first voltage to a second voltage during a second charge phase of the programming operation; wherein the second charging phase is located after the first charging phase, and the charging rate of the first charging phase is less than or equal to the charging rate of the second charging phase;
the peripheral circuitry is further configured to charge selected ones of the word lines to a programming voltage after the second charge phase; wherein the programming voltage is greater than the second voltage.
11. The memory of claim 10, wherein the peripheral circuitry is further configured to charge unselected ones of the word lines to a pass voltage during the first and second charge phases; wherein the pass voltage is greater than the first voltage and less than or equal to the second voltage;
the peripheral circuitry is configured to charge the first dummy word line to a first voltage during a first charge phase of a programming operation, including:
the peripheral circuit is configured to perform a first floating operation on the first dummy word line; wherein the unselected word line couples the floating first dummy word line to the first voltage during the charging of the unselected word line to the pass voltage by the peripheral circuitry.
12. The memory of claim 11, wherein the memory cell array further comprises:
a second dummy word line between the word line and the first dummy word line;
the peripheral circuit is further configured to perform a second floating operation on the second dummy word line in the first charge phase; wherein the unselected word line couples the floating second dummy word line to the first voltage during the charging of the unselected word line to the pass voltage by the peripheral circuitry; the floating time period of the second floating operation is different from the floating time period of the first floating operation.
13. The memory of claim 12, wherein the peripheral circuitry is specifically configured to:
starting to perform the first floating operation on the first dummy word line at a first time;
ending the first floating operation on the first dummy word line at a second time;
after the first time, and before the second time, beginning to perform the second floating operation on the second dummy word line;
ending the second floating operation on the second dummy word line at the second time.
14. The memory of claim 12, wherein the peripheral circuitry is specifically configured to:
starting to perform the first floating operation on the first dummy word line at a first time;
ending the first floating operation on the first dummy word line at a second time;
starting to perform the second floating operation on the second dummy word line at the first timing;
ending the second floating operation on the second dummy word line before the second time.
15. The memory of claim 10, wherein the peripheral circuitry is configured to charge the first dummy word line to a first voltage during a first charge phase of a programming operation, comprising:
at a first time to a second time, the peripheral circuit charges the first dummy word line to the first voltage;
the peripheral circuitry is further configured to charge the first dummy word line from the first voltage to a second voltage during a second charge phase of the programming operation, including:
at a third time to a fourth time, the peripheral circuit charges the first dummy word line from the first voltage to the second voltage;
the peripheral circuit is further configured to hold the first dummy word line at the first voltage from the second time to the third time.
16. The memory of claim 10,
when the peripheral circuitry is configured to charge a first dummy word line between the upper select gate line and the word line to the first voltage, the peripheral circuitry is further configured to: applying a turn-on voltage to an upper select gate line coupled to the selected memory string and applying a turn-off voltage to a lower select gate line coupled to the selected memory string, an upper select gate line of an unselected memory string, and a lower select gate line of an unselected memory string;
and/or the presence of a gas in the atmosphere,
when the peripheral circuitry is configured to charge a first dummy word line between the lower select gate line and the word line to the first voltage, the peripheral circuitry is further configured to: an on voltage is applied to upper select gate lines coupled to the selected memory strings, and an off voltage is applied to lower select gate lines coupled to the selected memory strings, upper select gate lines of unselected memory strings, and lower select gate lines of unselected memory strings.
17. The memory of claim 10, wherein the peripheral circuitry is further configured to: maintaining the first dummy word line at the second voltage during charging of the selected word line to a programming voltage.
18. The memory of claim 10, wherein the program operation comprises a plurality of program cycles;
the peripheral circuitry is configured to charge the first dummy word line to the first voltage during a first charge phase of each programming cycle;
the peripheral circuitry is further configured to charge the first dummy word line from the first voltage to the second voltage during a second charge phase of each programming cycle.
19. A memory system, comprising:
one or more memories as claimed in any one of claims 10 to 18;
a memory controller coupled to the memory and configured to control the memory.
CN202210719641.7A 2022-06-23 2022-06-23 Memory and operation method thereof, and memory system Pending CN115019860A (en)

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