CN114974382A

CN114974382A - Memory, system and operation method of memory

Info

Publication number: CN114974382A
Application number: CN202210406573.9A
Authority: CN
Inventors: 魏文喆; 刘红涛
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-04-18
Filing date: 2022-04-18
Publication date: 2022-08-30

Abstract

The application discloses a memory, a system and an operation method of the memory, and belongs to the technical field of storage. The memory is programmed by applying a first voltage to one end of the memory string, applying a second voltage and a third voltage to a first select transistor and a second select transistor of the memory string, respectively, the first selection tube and the second selection tube are conducted, a fourth voltage is applied to the memory unit of the first stack, rendering the memory cell of the first stack conductive, applying a fifth voltage to the memory cell of the second stack in the memory string, rendering the memory cell of the second stack non-conductive, to discharge the channel of the memory string, in the discharging process, because one part of the storage units in the storage string are in a conducting state and the other part of the storage units are in a non-conducting state, the current in the channel in the discharging process can be reduced, the hot carrier injection of the storage units in the second stack is reduced, and the interference on the storage units of the second stack is reduced.

Description

Memory, system and operation method of memory

Technical Field

The present application relates to the field of storage technologies, and in particular, to a memory, a system, and an operating method of the memory.

Background

Three-dimensional (3D) memories are widely used in computer devices, mobile phones, personal computers, and other types of electronic devices due to their small size, high storage capacity, and non-volatile data.

A memory string in a three-dimensional memory is formed by a plurality of stacks (stacks), each stack comprising a plurality of levels of memory cells connected in series. In the programming phase, the three-dimensional memory is programmed in page units, and the memory cells are programmed to store data into the memory cells.

However, after the programming stage is completed, the channel of the memory string where the memory cell programmed this time is located is rapidly discharged, and since the plurality of stacks in the memory string share the same channel, in the discharging process of the channel, Hot Carrier Injection (HCI) effect is easily generated in the memory cells in other stacks, so that the threshold voltages of the memory cells in other stacks are shifted, and interference is caused to the memory cells in other stacks.

Disclosure of Invention

Embodiments of the present application provide a memory, a system, and an operating method of a memory, which can reduce interference to memory cells of other stacks in a memory string when programming a memory cell of a certain stack in the memory string. The technical scheme is as follows:

in a first aspect, a memory is provided, the memory comprising a memory array and peripheral circuitry;

the memory array comprises a memory string, a first selection line, a second selection line and a plurality of word lines, wherein the memory string comprises a first stack, a second stack, a first selection pipe and a second selection pipe, and the first stack and the second stack respectively comprise a plurality of memory units;

the first select line is coupled to the first select tube, the second select line is coupled to the second select tube;

the plurality of word lines are respectively coupled to a plurality of memory cells of the memory string;

the peripheral circuitry coupled to the first select line, the second select line, and the plurality of word lines, the peripheral circuitry configured to:

after the programming phase of the first stack, applying a first voltage to one end of the memory string, applying a second voltage to the first selection line coupled by the first selection pipe, applying a third voltage to the second selection line coupled by the second selection pipe, respectively applying a fourth voltage to the word line coupled by each memory cell of the first stack, respectively applying a fifth voltage to the word line coupled by each memory cell of the second stack, to discharge the channel of the memory string;

the second voltage is used for conducting the first selection tube, the third voltage is used for conducting the second selection tube, a fourth voltage applied to each memory cell of the first stack is used for conducting a corresponding memory cell, and a fifth voltage applied to each memory cell of the second stack is used for not conducting the corresponding memory cell.

In one possible implementation, the verification phase of the first stack is subsequent to the programming phase, the peripheral circuitry being further configured to:

after the programming phase and before the verifying phase, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled by the first select transistor, applying a third voltage to the second select line coupled by the second select transistor, applying a fourth voltage to the word line coupled by each memory cell of the first stack, and applying a fifth voltage to the word line coupled by each memory cell of the second stack are performed.

In one possible implementation, the peripheral circuitry is further configured to:

immediately after the programming phase is finished, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first selection line coupled by the first selection pipe, applying a third voltage to the second selection line coupled by the second selection pipe, applying a fourth voltage to the word line coupled by each memory cell of the first stack, and applying a fifth voltage to the word line coupled by each memory cell of the second stack are performed.

after the programming phase is finished, after a first preset time period, executing the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first selection line coupled by the first selection pipe, applying a third voltage to the second selection line coupled by the second selection pipe, applying a fourth voltage to the word line coupled by each memory cell of the first stack, and applying a fifth voltage to the word line coupled by each memory cell of the second stack.

after the verifying stage, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled by the first select transistor, applying a third voltage to the second select line coupled by the second select transistor, applying a fourth voltage to the word line coupled by each memory cell of the first stack, and applying a fifth voltage to the word line coupled by each memory cell of the second stack are performed.

immediately after the verification phase is finished, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first selection line coupled by the first selection pipe, applying a third voltage to the second selection line coupled by the second selection pipe, applying a fourth voltage to the word line coupled by each memory cell of the first stack, and applying a fifth voltage to the word line coupled by each memory cell of the second stack are performed.

after the verifying stage is finished, after a second preset time period, executing the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first selection line coupled by the first selection pipe, applying a third voltage to the second selection line coupled by the second selection pipe, applying a fourth voltage to the word line coupled by each memory cell of the first stack, and applying a fifth voltage to the word line coupled by each memory cell of the second stack.

In one possible implementation, the fifth voltage applied to each memory cell of the second stack is less than the minimum turn-on voltage of each memory cell of the second stack.

In one possible implementation, the fifth voltage is greater than the initial voltage of the word line coupled to each memory cell of the second stack and less than the voltage applied to the word line coupled to each memory cell of the second stack during the programming phase;

alternatively, the fifth voltage is greater than the initial voltage of the word line to which each memory cell of the second stack is coupled and less than the voltage applied to the word line to which each memory cell of the second stack is coupled during the verify phase.

In a second aspect, a system is provided that includes a memory configured to store data, the memory including a memory array and peripheral circuitry;

In one possible implementation, the system further includes a host and a memory controller;

the host is configured to send data to or receive data from the memory;

the memory controller is coupled to the host and the memory and configured to control the memory.

In a third aspect, a method for operating a memory is provided, where the memory includes a memory array including a memory string, a first select line, a second select line, and a plurality of word lines, the memory string includes a first stack, a second stack, a first select pipe, and a second select pipe, and the first stack and the second stack respectively include a plurality of memory cells;

the plurality of word lines are respectively coupled to a plurality of memory cells of the memory string, the method comprising:

In one possible implementation, the verification phase of the first stack is located after the programming phase, the method further comprising:

after the programming phase and before the verifying phase, performing the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select pipe, applying a third voltage to the second select line coupled to the second select pipe, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack

In one possible implementation, the method further includes:

immediately after the programming phase ends, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line to which the first select transistor is coupled, applying a third voltage to the second select line to which the second select transistor is coupled, applying a fourth voltage to the word line to which each memory cell of the first stack is coupled, and applying a fifth voltage to the word line to which each memory cell of the second stack is coupled are performed.

In one possible implementation, the method further includes:

In one possible implementation, the verification phase of the first stack is after the programming phase, and the method further includes:

In one possible implementation, the method further includes:

In the technical solution provided by the embodiment of the present application, after a programming stage of a first stack in a memory string, a first voltage is applied to one end of the memory string, a second voltage and a third voltage are respectively applied to a selection line coupled to a first selection transistor and a selection line coupled to a second selection transistor of the memory string, so that the first selection transistor and the second selection transistor are turned on, a fourth voltage is respectively applied to word lines coupled to memory cells of the first stack, so that memory cells of the first stack are turned on, a fifth voltage is respectively applied to word lines coupled to memory cells of a second stack in the memory string, so that memory cells of the second stack are not turned on, so as to discharge a channel of the memory string, and in a discharging process, since a part of memory cells in the memory string are in a conducting state and another part of memory cells in the memory string are in a non-conducting state, a current in the channel in the discharging process can be reduced, hot carrier injection of the memory cells in the second stack is reduced, reducing interference to the memory cells of the second stack.

Drawings

FIG. 1 is a schematic diagram of a system shown in accordance with an exemplary embodiment;

FIG. 2 is a schematic diagram illustrating a memory card in accordance with an exemplary embodiment;

FIG. 3 is a schematic diagram of a solid state drive shown in accordance with an exemplary embodiment;

FIG. 4 is a schematic diagram illustrating a memory in accordance with an exemplary embodiment;

FIG. 5 is a schematic diagram illustrating a structure of a memory string in accordance with an illustrative embodiment;

FIG. 6 is a schematic diagram illustrating the structure of a peripheral circuit in accordance with an exemplary embodiment;

FIG. 7 is a schematic diagram illustrating the principle of HCI effect generation according to an exemplary embodiment;

FIG. 8 is a flowchart illustrating a method of operation of a memory in accordance with an exemplary embodiment;

FIG. 9 is a flowchart illustrating a method of operation performed after a programming phase and before a verification phase in accordance with an exemplary embodiment;

FIG. 10 is a voltage waveform diagram illustrating channel discharge immediately after the end of a programming phase in accordance with an exemplary embodiment;

FIG. 11 is a graph of a voltage waveform illustrating a channel discharge after a first predetermined period of time according to an exemplary embodiment;

FIG. 12 is a flowchart illustrating a method of operation performed after a verification phase in accordance with an exemplary embodiment;

FIG. 13 is a voltage waveform diagram illustrating channel discharge immediately after a verify phase is completed in accordance with an exemplary embodiment;

FIG. 14 is a graph illustrating a voltage waveform for discharging a channel after a second predetermined period of time in accordance with an exemplary embodiment;

FIG. 15 is a graph illustrating a shift in threshold voltage of a memory cell of a second stack in accordance with an exemplary embodiment.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

The terms "first," "second," and the like, in this application, are used for distinguishing between similar items and items that have substantially the same function or similar functionality, and it should be understood that "first," "second," and "nth" do not have any logical or temporal dependency, nor do they define a quantity or order of execution. It will be further understood that, although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by these terms.

These terms are only used to distinguish one element from another. For example, a first element can be termed a second element, and, similarly, a second element can also be termed a first element, without departing from the scope of various examples. The first element and the second element may both be elements, and in some cases, may be separate and distinct elements.

For example, at least one element may be an integer number of elements equal to or greater than one, such as one element, two elements, three elements, and the like. And at least two means two or more, for example, at least two elements may be any integer number of two or more, such as two elements, three elements, and the like.

Fig. 1 is a schematic diagram illustrating a system 100 that may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, Virtual Reality (VR) device, Augmented Reality (AR) device, or any other suitable electronic device having storage therein, according to an example embodiment.

As shown in fig. 1, the system 100 includes a host 101 and a storage subsystem 102, and the host 101 may be a processor (e.g., a Central Processing Unit (CPU)) or a system on chip (SoC) (e.g., an Application Processor (AP)) of an electronic device. The host 101 may be configured to send data to the memory 103. Alternatively, the host 101 may be configured to receive data from the memory 103.

The storage subsystem 102 includes one or more memories 103 and a memory controller 104. Wherein the memory 103 is configured to store the memory controller 104 coupled to the memory 103. Memory 103 may be any memory disclosed in the present disclosure. Optionally, the memory 103 is a NAND gate flash (NAND flash) memory device. A NAND flash memory device, such as a three-dimensional (3D) NAND flash memory device.

According to some embodiments, the memory controller 104 is also coupled to the host 101. The memory controller 104 may manage data stored in the memory 10 and communicate with the host 101.

In one possible implementation, the memory controller 104 is designed for operation in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other medium for use in electronic devices such as personal computers, digital cameras, mobile phones, and so forth.

In one possible implementation, the memory controller 104 is designed for operation in a high duty cycle environment Solid State Disk (SSD) or embedded multimedia card (eMMC) that serves as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, and the like, as well as enterprise storage arrays.

The memory controller 104 may be configured to control operations of the memory 103, such as read, erase, and program operations. The memory controller 104 may also be configured to manage various functions with respect to data stored or to be stored in the memory 103, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like. In one possible implementation, memory controller 104 is also configured to process Error Correction Codes (ECC) with respect to data read from memory 103 or written to memory 103.

The memory controller 104 may also perform any other suitable functions, such as formatting the memory 103. The memory controller 104 may communicate with external devices (e.g., the host 101) according to a particular communication protocol. For example, the memory controller 104 may communicate with the external device via at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system small interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and so forth.

The memory controller 104 and the one or more memories 103 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the system 100 may be implemented and packaged into different types of end electronic products.

Fig. 2 is a schematic diagram illustrating a memory card according to an example embodiment, and as shown in fig. 2, the memory controller 104 and the single memory 103 may be integrated into the memory card 200. The memory card 200 may include a PC card (PCMCIA), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, and the like. Memory card 200 may also include a memory card connector 201 that couples memory card 200 with a host (e.g., host 101 in FIG. 1).

Fig. 3 is a schematic diagram illustrating a solid state drive according to an example embodiment, and as shown in fig. 3, the memory controller 104 and the plurality of memories 103 may be integrated into a Solid State Drive (SSD) 300. Solid state drive 300 may also include a solid state drive connector 301 that couples solid state drive 300 with a host (e.g., host 101 in fig. 1). In one possible implementation, the storage capacity and/or operating speed of the solid state drive 300 is greater than the storage capacity and/or operating speed of the memory card 200.

FIG. 4 is a schematic diagram illustrating a memory in accordance with an exemplary embodiment. As shown in fig. 4, the memory 103 includes a memory array 310, a plurality of Bit Lines (BLs) 320, a plurality of Word Lines (WLs) 330, and a peripheral circuit 340.

The memory array 310 includes a plurality of memory strings 311, the memory strings 311 are arranged above a memory array substrate (not shown) in an array, and each memory string 311 extends vertically above the substrate.

Each memory string 311 includes a plurality of memory cells 312, and the plurality of memory cells 312 in each memory string 311 are vertically stacked above the memory array 310 substrate. Each memory cell 312 has a function of storing data, the stored data is determined by the number of electrons stored in the memory cell 312, and the number of electrons stored in the memory cell 312 can determine the magnitude of the threshold voltage of the memory cell 312, so that the threshold voltage of the memory cell 312 can indicate the data stored therein. The memory cell 312 is a floating gate field effect transistor or a charge trap (charge trap) type field effect transistor.

Each memory string 311 also includes an upper select pipe 313 and a lower select pipe 314, the upper select pipes 313 at the same height or a similar height from the substrate carrying surface in different memory strings 311 being coupled to the same Drain Select Line (DSL) 350. The lower select tubes 314 of different memory strings 311 are coupled to the same Source Select Line (SSL) 360 at the same height or a similar height from the substrate carrying surface. Wherein upper select pipe 313 and lower select pipe 314 are used to activate selected memory strings when erasing, programming or erasing memory cells. The upper select transistor 313 is also referred to as a Top Select Gate (TSG), and the lower select transistor 314 is also referred to as a Bottom Select Gate (BSG).

One end of the memory string 311 is coupled to a bit line 320, and the other end of the memory string 311 is coupled to a Source Line (SL) 380.

The memory cells 312 of different memory strings 311 are at the same level with the same height or similar heights from the substrate carrier surface, and the memory cells 312 at the same level form a memory cell row 31a, i.e. the memory array 310 includes a plurality of memory cell rows, and a plurality of word lines 330 are respectively coupled to the plurality of memory cell rows. All memory strings 311 in the memory array 310 sharing a same set of word lines form a memory block 31b, and the source terminals of the memory strings 311 in the same memory block 31b are coupled to a same source line 380.

As the number of layers of the memory string 311 increases, it is necessary to form a plurality of stacked memory strings 311 by a plurality of times of etching. For example, FIG. 5 illustrates a schematic diagram of a memory string structure, according to an example embodiment. Referring to fig. 5, a memory string 500 includes a plurality of memory cells, the memory cells arranged one by one are respectively connected to word lines 330, and the memory cells arranged one by one include channels, and the channels of the memory cells in each stack can be sequentially connected to form channels 315 of a memory string 311. When two stacks are stacked by an etching process to form the memory string 311, at least one dummy memory cell is disposed between the two pairs of stacks, so that the peripheral circuit 340 controls different stacks in the same memory string based on the dummy memory cell.

Referring back to FIG. 4, peripheral circuitry 340 is coupled to the plurality of word lines 330, the peripheral circuitry 340 by controlling the voltage V of the word line 330 to which the selected memory string is coupled _WL And the voltage V of the bit line coupled by the selected memory string _BL The memory cells in the selected memory string are controlled to implement the method of operation described below.

The peripheral circuit 340 includes various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, FIG. 6 illustrates a schematic diagram of a peripheral circuit, according to an exemplary embodiment. As with peripheral circuitry 340 shown in fig. 6, peripheral circuitry 340 includes page buffers/sense amplifiers 604, column decoders/Bit Line (BL) drivers 606, row decoders/Word Line (WL) drivers 608, voltage generators 610, control logic 612, registers 614, interfaces 616, and a data bus 618. In some examples, additional peripheral circuitry not shown in fig. 6 is also included. The page buffer/sense amplifier 604 may be configured to read data from the memory array 310 and program (write) data to the memory array 310 according to control signals from the control logic unit 612. In one example, the page buffer/sense amplifier 604 may store a page of program data (write data) to be programmed into one page of the memory array 310. In another example, the page buffer/sense amplifier 604 may perform a program verify operation to ensure that data has been properly programmed into the memory cells 312 coupled to the selected word line. In yet another example, page buffer/sense amplifier 604 may also sense low power signals from bit lines representing data bits stored in memory cells 312 and amplify small voltage swings to recognizable logic levels in a read operation. The column decoder/bit line driver 606 may be configured to be controlled by the control logic unit 612 and select one or more memory strings 311 by applying bit line voltages generated from the voltage generator 610.

The row decoder/word line drivers 608 may be configured to be controlled by the control logic unit 612 and select/deselect the memory blocks 31b of the memory array 310 to select/deselect the word lines 330 of the block 31 b. The row decoder/word line driver 608 may also be configured to drive word lines using word line voltages generated from the voltage generator 610. In some embodiments, the row decoder/wordline driver 608 may also select/deselect and drive DSL and SSL. As described in detail below, the row decoder/wordline driver 608 is configured to perform an erase operation on the memory cells 312 coupled to the selected wordline(s). The voltage generator 610 may be configured to be controlled by the control logic unit 612 and to generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verify voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory array 310.

The control logic unit 612 may be coupled to each of the peripheral circuits 340 described above and configured to control the operation of each of the peripheral circuits 340. Registers 614 may be coupled to control logic unit 612 and include status, command, and address registers for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit 340. The interface 616 may be coupled to the control logic 612 and act as a control buffer to buffer and relay control commands received from a host (not shown) to the control logic 612 and to buffer and relay status information received from the control logic 612 to the host. The interface 616 may also be coupled to the column decoder/bit line drivers 606 via a data bus 618, and act as a data I/O interface and data buffer to buffer data and relay it to the memory array 310 or to relay or buffer data from the memory array 310.

With continuing reference to FIG. 5, taking the memory string 500 of FIG. 5 as the selected memory string, the lower stack (lower) of the selected memory string as the unselected (unsel) stack, the upper stack (upper) of the selected memory string as the selected (sel) stack, and a memory cell in the selected stack as the selected memory cell, for example, the HCI effect occurring in the unselected stack of the selected memory string is described as follows:

the programming process of the selected memory cell includes a precharge (precharge) phase, a Programming (PGM) phase, and a verify (verify) phase. In the pre-charge stage, the channel of the selected memory string is pre-charged in a Gate Induced Drain Leakage (GIDL) manner to increase the potential of the channel. Then, the voltage of the BL or SL corresponding to the selected memory string is decreased to 0V, and the voltages of the BL and SL are both maintained at 0V in the programming phase. When the voltage of the BL or SL drops to 0V, the voltage of the BL or SL is lower than that of the channel of the selected memory string. Since the channel of the selected memory string and the BL or SL correspond to a PN junction, when the voltage of the BL or SL is lower than that of the channel of the selected memory string, the channel and the BL or SL form a PN junction that is forward-turned on, and the channel potential starts to be discharged. Different threshold voltages of the memory cells in the memory string are simultaneously selected, resulting in a channel voltage in the channel that forms a PNP-like junction. If the voltage of BL is 0V and any P area of the PNP-like junction is close to the upper selection tube, because the channel voltage of the memory cell in any P area is higher than the voltage of BL, the hole in the channel of the memory cell in any P area is transmitted to the BL direction, so that the channel voltage of the memory cell in any P area is reduced to realize the discharge to the BL direction. If the voltage of SL is 0V and any P area of the PNP-like junction is close to the lower selection tube, because the channel voltage of the memory cell in any P area is higher than the voltage of SL, holes in the channel of the memory cell in any P area are transmitted to the direction of SL, so that the channel potential of the memory cell in any P area is reduced, and the discharge to the direction of SL is realized.

During the period of time when the verify phase is entered, the voltages of both BL and SL continue to be maintained at 0V, so that the PNP junction-like structure will slow down the discharge of the channel voltage. Specifically, due to the unidirectional conductivity of the PN junction, holes in the channel of the memory cell in the N-region of the PNP-like junction cannot be transported toward the P-region during the discharge process, so that the holes are retained in the channel of the memory cell in the N-region, thereby delaying the discharge. And the holes that are left behind make the potential of the channel of the memory cell in the N region higher than the potential of the channel of the memory cell in the P region, thereby forming a potential difference between the channel of the memory cell in the N region and the channel of the memory cell in the P region. This potential difference induces the HCI effect when carriers flow in the channel.

Taking the schematic diagram of fig. 7 illustrating the HCI effect generation principle according to an exemplary embodiment as an example, if at least one memory cell c is stacked between the selected memory cell a and the selected memory cell b and the threshold voltage of the at least one memory cell c is 0V, the threshold voltages of the memory cell a and the memory cell b are both greater than the threshold voltage of the at least one memory cell c in the selected memory string shown in fig. 7. The memory cell a, the at least one memory cell c and the memory cell b form a PNP-like junction due to the fact that threshold voltages of the memory cell a, the at least one memory cell c and the memory cell b are different, wherein the memory cell a and the memory cell b are respectively located in a P area of the PNP-like junction, and the at least one memory cell c is located in an N area of the PNP-like junction. If the voltages of BL and SL are both 0V, the memory cell a approaches TSG, and holes in the channel of the memory cell a are transported in the BL direction. Taking the example that at least one memory cell c discharges in the SL direction, if the memory cell b is close to BSG, the memory cell b is located in the SL direction of at least one memory cell c. Under the action of the SL low voltage, holes in the channel of the at least one memory cell c are transported towards the memory cell b, but due to the unidirectional conductivity of the PN junction, the holes in the channel of the at least one memory cell c cannot cross the channel of the memory cell b, so that the holes in the channel of the at least one memory cell c are left in place, thereby maintaining the high voltage of the channel of the at least one memory cell c. And under the action of the SL low voltage, holes in the channel of the memory cell b are transported to the SL direction, the voltage of the channel of the memory cell b is reduced, and thus a potential difference is formed between at least one memory cell c and the channel of the memory cell b. When a current flows in the channel, the potential difference of the channel between the at least one storage unit c and the storage unit b causes the current carriers to generate an HCI effect between the storage unit b and the at least one storage unit c, and hot electrons in the HCI effect enter the at least one storage unit c.

If the data stored in the memory cells in the unselected stacks is maintained after the data is stored in the memory cells in the unselected stacks, the threshold voltages of the memory cells in the unselected stacks may be different, and a PNP-like junction may be formed between the memory cells in the unselected stacks during the discharge of the selected memory string. HCI effects may occur at memory cells that are not in the selected stack that resemble a PNP junction N region, both when reading data in the selected memory string and during programming, may generate carriers in the channel of the selected memory string. As the number of read operations or the number of programming stages that pass increases, multiple HCI effects may occur in a memory cell with a low threshold voltage in a non-selected stack, and hot electrons in the multiple HCI effects are accumulated in the memory layer of the memory cell with a low threshold voltage, so that the threshold voltage of the memory cell shifts, which may cause interference to the memory cell.

As can be seen from the above description of the memory, the memory includes a memory array and a peripheral circuit, wherein the memory array includes a plurality of memory strings, a first select line, a second select line and a plurality of word lines. Wherein the first select line is either one of DSL and SSL and the second select line is the other one of DSL and SSL. For example, the first select line is DSL and the second select line is SSL, and for example, the first select line is SSL and the second select line is DSL.

In one possible implementation, each memory string includes a first stack, a second stack, a first selection pipe, and a second selection pipe. The first stack and the second stack respectively comprise a plurality of storage units. If the first select line is DSL and the second select line is SSL, the first select tube is TSG and the second select tube is BSG, and if the first select line is SSL and the second select line is DSL, the first select tube is BSG and the second select tube is TSG.

Peripheral circuitry in the memory is configured to discharge a channel of a selected one of the plurality of memory strings. To further embody the process of discharging the channel of the selected memory string, a flow chart of a method of operating a memory is shown with reference to fig. 8 according to an exemplary embodiment, the method comprising:

801. after the programming phase of the first stack, a first voltage is applied to one end of the memory string, a second voltage is applied to a first select line to which the first select transistor is coupled, and a third voltage is applied to a second select line to which the second select transistor is coupled.

The memory string is a selected memory string in the current programming process, and the first stack is a selected stack in the current programming process, that is, a stack in which a selected memory cell in the current programming process is located. Still taking the memory string 500 shown in fig. 5 as an example, if the first stack is an upper stack in the memory string 500, the selected memory cell is any memory cell in the upper stack, and if the first stack is a lower stack in the memory string 500, the selected memory cell is any memory cell in the lower stack.

The first voltage is a voltage capable of discharging a channel of the memory string. The first voltage ranges from 0V to 1V. The second voltage is used to turn on the first selection transistor, for example, the second voltage is the turn-on voltage of the first selection transistor. The third voltage is used to turn on the second selection tube, for example, the third voltage is the turn-on voltage of the second selection tube.

Taking one end of the memory string as a drain end, the first select transistor as TSG, the second select transistor as BSG, the second voltage as TSG, and the third voltage as BSG, the following steps are performed in this step 801:

the drain terminal is coupled to a bit line, and the first voltage is applied to the bit line of the memory string after the programming phase of the first stack such that the first voltage acts on the drain terminal of the memory string. The source line of the memory string is grounded so that a 0V voltage of the source line acts at the source terminal of the memory string.

After the programming phase of the first stack, an on voltage of the TSG is applied to the drain select line to which the TSG of the memory string is coupled, so that the TSG is turned on. Applying a turn-on voltage of the BSG to a source select line to which the BSG of the memory string is coupled, such that the BSG is turned on.

802. After the programming phase of the first stack, a fourth voltage is applied to the word line to which each memory cell of the first stack is coupled, the fourth voltage applied to each memory cell of the first stack being used to turn on the corresponding memory cell.

The value of the fourth voltage applied to each memory cell of the first stack may be the same or different, and the corresponding memory cell may be turned on. The value range of the fourth voltage of each memory cell of the first stack is 5V to 7V. Since a fourth voltage can turn on the corresponding memory cell, the memory cells of the first stack can be turned on by applying the fourth voltage to the word lines to which the memory cells of the first stack are coupled, respectively.

When the memory string includes dummy memory cells, a conducting unit of the dummy memory cells is also applied to the dummy word line coupled to the dummy memory cells, so that the dummy memory cells are conducted.

803. After the programming phase of the first stack, a fifth voltage is applied to the word line to which each memory cell of the second stack is coupled, the fifth voltage being less than the fourth voltage.

The second stack is a stack in the memory string except the first stack, and the second stack is a non-selected stack. Still taking the memory string 500 shown in fig. 5 as an example, if the first stack is the upper stack in the memory string 500, the second stack is the lower stack in the memory string 500, and if the first stack is the lower stack in the memory string 500, the second stack is the upper stack in the memory string 500. Fig. 5 illustrates an example of a memory string 500 including 2 stacks, and in other embodiments, there are more than two stacks in the memory string, so that for the programming process, there is a first stack in the memory string, and each stack in the memory string except the first stack is a second stack, and there are at least two second stacks in the memory string.

The value of the fifth voltage applied to each memory cell of the second stack may be the same or different, and the corresponding memory cell may not be turned on. In one possible implementation, the fifth voltage applied across each memory cell of the second stack is less than the minimum turn-on voltage of each memory cell of the second stack. The value range of the fifth voltage is 0V to 4V or 0V to 3V. In one possible implementation, the fifth voltage is greater than the initial voltage of the word line coupled to each memory cell of the second stack and less than the voltage applied to the word line coupled to each memory cell of the second stack during the programming phase; alternatively, the fifth voltage is greater than the initial voltage of the word line to which each memory cell of the second stack is coupled and less than the voltage applied to the word line to which each memory cell of the second stack is coupled during the verify phase. The initial voltage of the word line coupled to each memory cell is greater than or equal to 0V, and the voltage of the word line coupled to each memory cell of the second stack during the programming phase is greater than the initial voltage of the corresponding word line. The voltage applied to the word line to which each memory cell of the second stack is coupled during the verify phase is greater than the initial voltage of the corresponding word line. The voltage applied to the word line coupled to each memory cell of the second stack during the program phase may be the same as or different from the voltage applied to the word line coupled to each memory cell of the second stack during the verify phase.

Since the fifth voltage can make the corresponding memory cell non-conductive, each memory cell in the second stack is made non-conductive by applying the fifth voltage to the word line coupled to each memory cell of the second stack, respectively.

Through the operation, the storage unit of the first stack, the TSG and the BSG in the storage string are all conducted, and the storage unit of the second stack is not conducted. The memory cell of the second stack is not turned on, but is in a non-conductive state (i.e., an off state), but still capable of transmitting leakage current, and therefore, the channel of the memory string is discharged under the action of the first voltage. In the discharging process, because each memory cell of the second stack is in an off state, a small amount of current in the channel of the memory string can still be transmitted through the non-conductive memory cell, and further slow discharging is realized. And because the current in the channel is smaller, under the action of the first voltage at one end of the storage string, the number of electrons in the current which become hot electrons is reduced, correspondingly, the number of the storage units which are tunneled to the second stack by the hot electrons is reduced, the drift of the threshold voltage of the storage units of the second stack is slowed down, and therefore in the programming process of the first stack, the interference on the storage units in the second stack can be reduced.

It should be noted that the peripheral circuits can execute the

steps

801 and 803 at the same time or at different times, and the execution sequence of the

steps

801 and 803 is not limited in the embodiment of the present application.

In the method provided by the embodiment of the application, after a programming stage of a first stack in a memory string, a first voltage is applied to one end of the memory string, a second voltage and a third voltage are respectively applied to a selection line coupled to a first selection tube and a selection coupled to a second selection tube of the memory string, so that the first selection tube and the second selection tube are conducted, a fourth voltage is respectively applied to word lines coupled to memory cells of the first stack, so that the memory cells of the first stack are conducted, a fifth voltage is respectively applied to the word lines coupled to the memory cells of the second stack in the memory string, so that the memory cells of the second stack are not conducted, so as to discharge a channel of the memory string, during the discharging process, because a part of the memory cells in the memory string are conducted and the other part of the memory cells in the memory string are not conducted, current in the channel during the discharging process can be reduced, hot carrier injection of the memory cells in the second stack is reduced, the disturbance of the memory cells of the second stack is reduced.

The operation of applying the first voltage to one end of the memory string, applying the second voltage to the first selection line coupled to the first selection pipe, applying the third voltage to the second selection line coupled to the second selection pipe, applying the fourth voltage to the word line coupled to each memory cell of the first stack, respectively, applying the fifth voltage to the word line coupled to each memory cell of the second stack, respectively, is referred to as a discharge operation for convenience of description.

There are two possible implementations of performing the discharge operation after the programming phase, the first implementation being: the discharge operation is performed after the program phase of the first stack and before the verify phase of the first stack. The second implementation mode is as follows: the discharge operation is performed after the verify phase of the first stack. See figures 9 and 11, respectively, for further illustration of both implementations.

FIG. 9 is a flowchart illustrating a method of operation performed after a programming phase and before a verification phase, as shown in FIG. 9, in accordance with an exemplary embodiment.

901. After a programming phase of the first stack and before a verification phase of the first stack, a first voltage is applied to one end of the memory string, a second voltage is applied to a first select line to which a first select pipe is coupled, and a third voltage is applied to a second select line to which a second select pipe is coupled.

The verification phase of the first stack is located after the programming phase of the first stack, and the verification phase and the programming phase belong to the current programming process of the first stack. For this case, according to the execution sequence, the stages in the current programming process of the first stack are: a precharge phase, a programming phase, a discharge phase, a verification phase.

The process of applying the first voltage to one end of the memory string, applying the second voltage to the first selection line coupled to the first selection pipe, and applying the third voltage to the second selection line coupled to the second selection pipe is described in step 801, and is not described herein again.

902. After the programming phase and before the verifying phase, a fourth voltage is applied to the word line to which each memory cell of the first stack is coupled, respectively.

The process of applying the fourth voltage to the word line coupled to each memory cell of the first stack is described in step 802, and is not described herein again.

903. After the programming phase and before the verification phase, a fifth voltage is applied to the word line to which each memory cell of the second stack is coupled, respectively.

The process of applying the fifth voltage to the word line coupled to each memory cell of the second stack is described in step 803, and is not described herein again.

It should be noted that the peripheral circuit can execute the steps 901-903 at the same time or at different times, and herein, the execution sequence of the steps 901-903 is not limited in this embodiment.

In the method provided by the embodiment of the application, after the programming stage and before the verification stage of the first stack, a first voltage is applied to one end of the memory string, a second voltage and a third voltage are respectively applied to a selection line coupled to a first selection pipe and a selection line coupled to a second selection pipe of the memory string, so that the first selection pipe and the second selection pipe are conducted, a fourth voltage is respectively applied to word lines coupled to memory cells of the first stack, so that the memory cells of the first stack are conducted, a fifth voltage is respectively applied to word lines coupled to memory cells of the second stack in the memory string, so that the memory cells of the second stack are not conducted to discharge the channel of the memory string, and in the discharging process, as a part of the memory cells in the memory string are in a conducting state and the other part of the memory cells in the memory string are in a non-conducting state, the current in the channel in the discharging process can be reduced, hot carrier injection of the memory cells in the second stack is reduced, reducing interference to the memory cells of the second stack.

The process shown in fig. 9 is a process of performing a discharging operation on the memory string in which the first stack is located after the programming phase and before the verifying phase. After the programming phase and before the verifying phase, the discharging operation on the memory string is performed in any one of the following manners a1 and a 2.

Mode a1, immediately after the programming phase is completed, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select line, applying a third voltage to the second select line coupled to the second select line, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack are performed.

Taking the TSG as the first select transistor, the BSG as the second select transistor, the TSG as the second voltage, and the BSG as the third voltage, as an example, refer to fig. 10, which is a voltage waveform diagram illustrating that channel discharge is performed immediately after the end of one programming phase according to an exemplary embodiment. The memory string is a selected memory string in a memory block to be programmed, the bit line of the selected memory string is a selected bit line, namely sel-BL, the TSG in the selected memory string is a selected TSG, namely sel-TSG, and the BSG in the selected memory string is a selected BSG, namely sel-BSG. The first stack in the selected memory string is the selected stack, the word line coupled to the selected memory cell in the first stack is the selected word line, sel-WL, and the word lines coupled to the memory cells other than the selected memory cell in the first stack are denoted as the word line of the selected stack, sel-deck-WL. The second stack in the selected memory string is an unselected stack, the memory cells in the second stack are unselected memory cells, and the word lines of the memory cells in the second stack are the word lines of the unselected stack, i.e., unsel-deck-WL.

As shown in FIG. 10, the time period from t0 to t6 corresponds to the current programming process of the selected memory cell in the first stack, and the time period after t6 corresponds to the next programming process. The present programming process includes a discharging phase (i.e., a phase for performing a discharging operation), and the next programming process does not include the discharging phase. While in still other embodiments the next programming process can also include a discharge phase, embodiments of the present application provide for whether the next programming process includes a discharge phase definition. As can be appreciated. In the multiple programming process of the first stack, the discharge phase referred to in the present application is in at least one programming process, and herein, the present application does not limit the at least one programming process in which the discharge phase is located.

the time period of t0-t1 corresponds to a pre-charging phase in the programming process, the time period of t1-t3 corresponds to a programming phase in the programming process, the time period of t3-t4 corresponds to a discharging phase in the programming process, a discharging operation is performed in the discharging time period, and the time period of t5-t6 corresponds to a verification phase in the programming process.

During t1-t3, the bit line initial voltage is held at sel-BL, and SL is held at ground, where the bit line initial voltage is the initial voltage of the bit line. Starting at t0, the voltage of the DSL to which the sel-TSG is coupled gradually increases from the initial voltage of the DSL, and when increasing to a voltage, the voltage is maintained at the DSL, wherein the voltage is less than the second voltage. The initial voltage of the DSL is maintained on the DSL coupled to the sel-TSG. The voltage of sel-WL is kept at a certain high voltage for a certain time period during t1-t3, and then gradually decreased from the high voltage during t2-t 3. For some time during t1-t3, the voltage of sel-deck-WL remains at the fourth voltage until the end of the programming phase. The voltage of unsel-deck-WL remains at the high voltage for a certain length of time during t1-t3, and then gradually decreases from the high voltage until it decreases to the fifth voltage at t 3.

During t3-t4, a discharge phase is entered, SL is held at ground, and from t3, the voltage of sel-BL is gradually increased from the initial voltage of the bit line until it increases to the first voltage, and the first voltage is held for a certain period of time, and then gradually decreased until it decreases to the initial voltage of the bit line. Starting at t3, the voltage of the DSL gradually increases until it increases to a second voltage, and the second voltage is maintained for a certain period of time so that the TSG remains on, and then gradually decreases until it decreases to the initial voltage of the DSL. Starting at t3, the voltage of SSL gradually increases from the initial voltage of SSL until increasing to the third voltage, and maintains the third voltage for a certain period of time, so that BSG remains on, and then gradually decreases until decreasing to the initial voltage of SSL. Starting at t3, the voltage of sel-WL gradually increases, and when increasing to the fourth voltage, the fourth voltage continues to be maintained, so that the selected memory cell remains conductive. Then, the voltage of sel-WL gradually decreases from the fourth voltage until t4, decreasing to the bit line initial voltage. Continuing to hold the fourth voltage on sel-deck-WL for a period of time after t3 such that the non-selected memory cells in the first stack remain conductive, then gradually decreasing the voltage of sel-deck-WL from the fourth voltage until t4 to a wordline initial voltage, where the wordline initial voltage is the initial voltage of the wordline to which the memory cells are coupled. For a certain length of time after t3, the voltage of unsel-deck-WL gradually decreases from the fifth voltage until it decreases to the wordline initial voltage at t 4. While the voltage of unsel-deck-WL remains at the fifth voltage, the individual memory cells of the second stack are non-conductive. The channel of the selected memory string is slowly discharged under the first voltage of the bit line.

In addition, the memory strings in the memory block to be programmed except the selected memory string are used as unselected memory strings, the bit lines coupled by the unselected memory strings are unselected bit lines, namely unsel-BL, and the TSG in the unselected memory strings is unselected TSG, namely unsel-TSG, because the unselected memory strings are not programmed. Then during the discharge phase, the memory applies a sixth voltage on unsel-BL, which may be the same as or different from the first voltage, but maintains the initial voltage of TSG at the gate of unsel-TSG to avoid conduction of the non-selected memory strings.

Mode a2, after the programming phase is over, after a first preset duration, performing the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select line, applying a third voltage to the second select line coupled to the second select line, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack.

The first preset time length is greater than 0, and the first preset time length can be set according to a specific implementation scenario, where a value range of the first preset time length is not limited in the embodiment of the present application.

Taking the TSG as the first selection transistor, the BSG as the second selection transistor, the TSG as the second voltage, and the BSG as the third voltage, refer to fig. 11, which is a voltage waveform diagram illustrating a channel discharge after a first preset time period according to an exemplary embodiment.

As shown in FIG. 11, the time period from t0 to t5 corresponds to the current programming process of the selected memory cell in the first stack, and the time period after t5 corresponds to the next programming process. the time period t0-t1 corresponds to a pre-charging stage in the programming process, the time period t1-t2 corresponds to a programming stage in the programming process, and the time length of the time period t2-t3 is a first preset time length. the time period t3-t4 corresponds to the discharge phase in the programming process, and the time period t4-t5 corresponds to the verification phase in the programming process.

During t1-t2, the voltages on the SSL to which sel-BL and sel-BSG are coupled are both maintained at their respective initial voltages. And the voltages of the sel-WL, sel-deck-WL, unsel-deck-WL and the DSL coupled by the sel-TSG are gradually reduced after a certain time of high voltage maintaining, and are reduced to the respective initial voltages at t 2.

During t2-t3, sel-BL, SSL, sel-WL, sel-deck-WL, unsel-deck-WL and SSL maintain their respective initial voltages,

during t3-t4, starting at t3, the voltage of sel-BL is gradually increased from the initial voltage of the bit line until increasing to the first voltage, and is maintained for a certain period of time, and then gradually decreased until decreasing to the initial voltage of the bit line at t 4. From t3, the voltage of the DSL gradually increases from the initial voltage until it increases to the second voltage, and the second voltage is maintained for a period of time such that the TSG remains on, and then gradually decreases until it decreases to the initial voltage at t 4. Starting at t3, the voltage of SSL gradually increases from the initial voltage until increasing to the third voltage, and the third voltage is maintained for a certain period of time, so that BSG remains on, and then gradually decreases until t4, decreasing to the initial voltage. Starting at t3, the voltages of sel-WL and sel-deck-WL gradually increase from their respective initial voltages until the corresponding fourth voltages are increased and maintained for a certain period of time, so that the respective memory cells in the first stack remain conductive, and then the voltages of sel-WL and sel-deck-WL gradually decrease until the respective initial voltages are decreased at t 4. Starting at t3, the unsel-deck-WL voltage is gradually increased from the wordline initial voltage until increasing to a fifth voltage and held for a period of time such that individual memory cells in the second stack are non-conductive, and then the unsel-deck-WL voltage is gradually decreased until decreasing to the wordline initial voltage at t 4.

During t1-t4, SL is kept at ground, during the discharge phase, during t3-t4, after sel-TSG, sel-BSG are turned on, the channel of the memory string is turned on, and if the memory cells of the first stack are turned on, the respective memory cells of the second stack are not turned on while the voltage of unsel-deck-WL is kept at the fifth voltage. The channel of the selected memory string is slowly discharged under the first voltage of the bit line.

In addition, since the non-selected memory strings are not programmed. Then the sixth voltage is applied to unsel-BL the same during the discharge phase, but the initial voltage of TSG is maintained at the gate of unsel-TSG to avoid conduction of the non-selected memory string.

FIG. 12 is a flowchart illustrating a method of operation performed after a verification phase, as shown in FIG. 12, in accordance with an exemplary embodiment.

1201. After a verify phase of the first stack, a first voltage is applied to one end of the memory string, a second voltage is applied to a first select line to which a first select transistor is coupled, and a third voltage is applied to a second select line to which a second select transistor is coupled.

The verification phase of the first stack is located after the programming phase of the first stack, and the verification phase and the programming phase belong to the current programming process of the first stack. For this case, according to the execution sequence, the stages in the current programming process of the first stack are: a precharge phase, a program phase, a verify phase, a discharge phase.

1202. After the verify phase of the first stack, a fourth voltage is applied to the word line to which each memory cell of the first stack is coupled, respectively.

1203. After the verify phase of the first stack, a fifth voltage is applied to the word line to which each memory cell of the second stack is coupled, respectively.

It should be noted that the peripheral circuit can execute steps 1201-1203 at the same time or at different times, and the execution sequence of steps 1201-1203 is not limited in this embodiment.

In the method provided by the embodiment of the application, after the verification stage of the first stack, a first voltage is applied to one end of the memory string, a second voltage and a third voltage are respectively applied to a selection line coupled to a first selection tube and a selection line coupled to a second selection tube of the memory string, so that the first selection tube and the second selection tube are conducted, a fourth voltage is respectively applied to word lines coupled to memory cells of the first stack, so that the memory cells of the first stack are conducted, a fifth voltage is respectively applied to word lines coupled to memory cells of the second stack in the memory string, so that the memory cells of the second stack are not conducted to discharge the channel of the memory string, and in the discharging process, because a part of the memory cells in the memory string are in a conducting state and another part of the memory cells in the memory string are in a non-conducting state, the current in the channel in the discharging process can be reduced, hot carrier injection of the memory cells in the second stack is reduced, reducing interference to the memory cells of the second stack.

The process shown in fig. 12 is a process of performing a discharging operation on the memory string in which the first stack is located after the verification stage. Wherein, after the verification phase, the manner of performing the discharging operation on the memory string includes any one of the following manner B1 and manner B2.

Mode B1, immediately after the verification phase of the first stack ends, the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line coupled to the first select line, applying a third voltage to the second select line coupled to the second select line, applying a fourth voltage to the word line coupled to each memory cell of the first stack, and applying a fifth voltage to the word line coupled to each memory cell of the second stack are performed.

Taking the TSG as the first select transistor, the BSG as the second select transistor, the TSG as the second voltage, and the BSG as the third voltage, refer to fig. 13, which is a voltage waveform diagram illustrating that channel discharge is performed immediately after the verification phase is completed according to an exemplary embodiment.

As shown in FIG. 13, the time period from t0 to t4 corresponds to the current programming process of the selected memory cell in the first stack, and the time period after t4 corresponds to the next programming process. the time period from t0 to t1 corresponds to the pre-charging stage in the programming process, the time period from t1 to t2 corresponds to the programming stage in the programming process, the time period from t2 to t3 corresponds to the verifying stage in the programming process, and the total time length from t2 to t3 is also the preset time length. the time period of t3-t4 corresponds to the discharging phase in the programming process, and the discharging operation is executed in the discharging time period.

During the period of t2-t3 after the programming is finished, the voltage of sel-BL is gradually increased from the initial voltage of the bit line from t2 and is kept after the first voltage is increased. By t3, the voltage of sel-BL continues to maintain the first voltage for a certain duration from entering the discharge phase, and then gradually decreases until t4 decreases to the initial bit line voltage.

During the period t2-t3 after the programming is finished, starting at t2, the voltage of the DSL coupled by the sel-TSG gradually increases from the initial voltage, and the second voltage is kept after increasing to the second voltage. Starting at t2, the voltage of SSL coupled by sel-BSG gradually increases from the initial voltage, and remains after increasing to the third voltage.

By t3, the DSL voltage continues to maintain the second voltage for a certain period of time from entering the discharge phase, so that the TSG is turned on. SSL continues to maintain the third voltage so that BSG remains on, after which DSL and SSL gradually decrease in voltage until t4 to their respective initial voltages.

During the period t2-t3 after the programming is finished, the voltages of sel-WL and sel-deck-WL gradually increase from t2, and the fourth voltage is maintained after increasing to the fourth voltage. By t3, sel-WL and sel-deck-WL continue to hold the fourth voltage for a certain duration from entering the discharge phase, causing the memory cells of the first stack to conduct. Then, the voltages of sel-WL and sel-deck-WL gradually decrease until t4, and the initial voltage of the word line is decreased.

The voltage of the unsel-deck-WL remains at the fifth voltage for a certain length of time during t2-t3, and thereafter gradually decreases from the fourth voltage until t3 decreases to the fifth voltage. By t3, a discharge phase is entered and the voltage of unsel-deck-WL continues to remain at the fifth voltage for a certain period of time after t3, so that the individual memory cells of the second stack remain non-conductive. Thereafter, the unsel-deck-WL voltage is gradually decreased from the fifth voltage until it is decreased to the word line initial voltage at t 4.

During t1-t4, SL is kept at ground, during the discharging phase, in t3-t4, after sel-TSG and sel-BSG are conducted, the channel of the memory string is conducted, and if the memory cell of the first stack is conducted, the voltage of unsel-deck-WL is kept at the fifth voltage, and the memory cells of the second stack are not conducted. The channel of the selected memory string is slowly discharged under the first voltage of the bit line.

In addition, since the non-selected memory strings are not programmed. Then during the discharge phase, a sixth voltage is applied across unsel-BL, but the initial voltage of TSG is maintained at the gate of unsel-TSG to avoid conduction of the non-selected memory strings.

Mode B2, after the verification phase of the first stack is finished, after a second preset time period, the steps of applying the first voltage to one end of the memory string, applying the second voltage to the first selection line coupled to the first selection pipe, applying the third voltage to the second selection line coupled to the second selection pipe, applying the fourth voltage to the word line coupled to each memory cell of the first stack, and applying the fifth voltage to the word line coupled to each memory cell of the second stack are performed.

The second preset duration is greater than 0, and the second preset duration may be equal to or not equal to the first preset duration. The second preset duration can be set according to a specific implementation scenario, and a value range of the second preset duration is not limited in the embodiment of the present application.

Taking the TSG as the first selection transistor, the BSG as the second selection transistor, the TSG as the second voltage, and the BSG as the third voltage, refer to fig. 14, which is a voltage waveform diagram illustrating that the channel discharge is performed after the second preset time period according to an exemplary embodiment.

As shown in FIG. 14, the time period from t0 to t5 corresponds to the current programming process of the selected memory cell in the first stack, and the time period after t5 corresponds to the next programming process. the time period t0-t1 corresponds to a pre-charging stage in the programming process, the time period t1-t2 corresponds to a programming stage in the programming process, the time period t2-t3 corresponds to a verification stage in the programming process, and the time length of the time period t3-t4 is a second preset time length. the time period t4-t5 corresponds to the discharge phase in the programming process.

During t2-t3, the voltages on DSL coupled by sel-BL, sel-TSG, sel-WL, sel-deck-WL, unsel-deck-WL and SSL coupled by sel-BSG, after a certain period of high voltage, are all gradually reduced to their respective initial voltages at t 3.

During t3-t4 sel-BL, DSL, sel-WL, sel-deck-WL, unsel-deck-WL and SSL maintain the respective initial voltages,

during t4-t5, starting at t4, the voltage of sel-BL is gradually increased from the initial voltage of the bit line until increasing to the first voltage, and is maintained for a certain period of time, and then gradually decreased until decreasing to the initial voltage of the bit line at t 5. Starting at t4, the voltage of the DSL to which the sel-TSG is coupled gradually increases from the initial voltage, maintains the second voltage for a certain period of time while increasing to the second voltage, and then gradually decreases until t 5. The voltage of SSL coupled by sel-BSG gradually increases from the initial voltage until increasing to a third voltage, and maintains the third voltage for a certain period of time, and then the voltage of SSL gradually decreases until decreasing to the initial voltage at t 5. Starting at t4, the voltages of sel-WL and sel-deck-WL each gradually increase from the respective initial voltages until increasing to a fourth voltage and remain at the fourth voltage for a period of time such that the respective memory cells in the first stack remain conductive, after which the voltages of sel-WL and sel-deck-WL gradually decrease until decreasing to the respective initial voltages at t 5. Starting at t4, the unsel-deck-WL voltage is gradually increased from the wordline initial voltage until increasing to a fifth voltage and held for a period of time such that individual memory cells in the second stack are non-conductive, and then the unsel-deck-WL voltage is gradually decreased until decreasing to the wordline initial voltage at t 5.

During t1-t5, SL is kept at ground, during the discharge phase, during t4-t5, after sel-TSG, sel-BSG are turned on, the channel of the memory string is turned on, and if the memory cells of the first stack are turned on, the respective memory cells of the second stack are not turned on while the voltage of unsel-deck-WL is kept at the fifth voltage. The channel of the selected memory string is slowly discharged under the first voltage of the bit line.

In addition, since the non-selected memory strings are not programmed. Then a sixth voltage is applied across unsel-BL during the discharge phase but the initial voltage of TSG is maintained at the gate of unsel-TSG to prevent conduction of non-selected memory strings.

FIG. 15 is a graph illustrating a shift in threshold voltage of a memory cell of a second stack in accordance with an exemplary embodiment. In the case where the programming process does not include the discharge phase proposed by the present disclosure, the programming process is not performed on the memory cells in the second stack in the memory string, and the programming process is performed on the memory cells in the first stack in the memory string a plurality of times. Thereafter, the offset amounts of the threshold voltages of the memory cells in the second stack are counted, and the offset amounts of the threshold voltages of the memory cells in the second stack are distributed in the bitmap shown on the left side in fig. 15. In the case where the programming process includes the discharge phase proposed in the present application, the programming process is not performed on the memory cell in the second stack in the memory string, and the programming process is performed on the memory cell in the first stack in the memory string a plurality of times. Thereafter, the shift amounts of the threshold voltages of the memory cells in the second stack are counted, and the shift amounts of the threshold voltages of the memory cells in the second stack are distributed in the bitmap shown on the right side in fig. 15. As can be seen from the left and right bitmap in fig. 15, the offset of the threshold voltage in the left bitmap is generally higher than that in the right bitmap, and therefore, after the verification phase of the memory cell, the discharge phase is added, so that the interference of HCI on the memory cells in other stacks can be reduced.

The above description is only exemplary of the present application and should not be taken as limiting, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A memory, comprising a memory array and peripheral circuitry;

2. The memory of claim 1, wherein the verify phase of the first stack is subsequent to the program phase, the peripheral circuitry further configured to:

3. The memory of claim 2, wherein the peripheral circuitry is further configured to:

4. The memory of claim 2, wherein the peripheral circuitry is further configured to:

5. The memory of claim 1, wherein the verify phase of the first stack is subsequent to the program phase, the peripheral circuitry further configured to:

6. The memory of claim 5, wherein the peripheral circuitry is further configured to:

7. The memory of claim 5, wherein the peripheral circuitry is further configured to:

8. The memory of any one of claims 1-7, wherein the fifth voltage is less than a minimum turn-on voltage of each memory cell of the second stack.

9. The memory of any one of claims 1-7, wherein the fifth voltage is greater than an initial voltage of a word line to which each memory cell of the second stack is coupled and less than a voltage applied to the word line to which each memory cell of the second stack is coupled during the programming phase;

10. A system comprising a memory configured to store data, the memory comprising a memory array and peripheral circuitry;

11. The system of claim 10, wherein the verify phase of the first stack is subsequent to the programming phase, the peripheral circuitry further configured to:

12. The system of claim 10, wherein the verify phase of the first stack is subsequent to the programming phase, the peripheral circuitry further configured to:

after the verify phase, performing the steps of applying a first voltage to one end of the memory string, applying a second voltage to the first select line to which the first select transistor is coupled, applying a third voltage to the second select line to which the second select transistor is coupled, applying a fourth voltage to the word line to which each memory cell of the first stack is coupled, and applying a fifth voltage to the word line to which each memory cell of the second stack is coupled.

13. The system according to any of claims 10-12, wherein the fifth voltage applied across each memory cell of the second stack is less than the minimum turn-on voltage of each memory cell of the second stack.

14. The system according to any of claims 10-12, wherein the fifth voltage is greater than an initial voltage of a word line coupled to each memory cell of the second stack and less than a voltage applied to the word line coupled to each memory cell of the second stack during the programming phase;

15. The system of any of claims 10-12, further comprising a host and a memory controller;

the host is configured to send data to or receive data from the memory;

16. The operation method of the memory is characterized in that the memory comprises a memory array, the memory array comprises a memory string, a first selection line, a second selection line and a plurality of word lines, the memory string comprises a first stack, a second stack, a first selection pipe and a second selection pipe, and the first stack and the second stack respectively comprise a plurality of memory units;

17. The method of claim 16, wherein a verify phase of the first stack is after the programming phase, the method further comprising:

18. The method of claim 16, wherein a verify phase of the first stack is after the programming phase, the method further comprising:

19. The method of any of claims 16-18, wherein the fifth voltage is less than a minimum turn-on voltage of each memory cell of the second stack.

20. The method of any of claims 16-18, wherein the fifth voltage is greater than an initial voltage of a word line coupled to each memory cell of the second stack and less than a voltage applied to the word line coupled to each memory cell of the second stack during the programming phase;