CN115273948A

CN115273948A - Operation method of memory, memory and memory system

Info

Publication number: CN115273948A
Application number: CN202210889977.8A
Authority: CN
Inventors: 杨名; 向莉; 魏镜; 张扬; 栗山正男; 梁轲
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-07-27
Filing date: 2022-07-27
Publication date: 2022-11-01

Abstract

The embodiment of the disclosure provides an operation method of a memory, the memory and a memory system. The memory comprises a memory cell array composed of a plurality of memory blocks, each of the memory blocks at least comprises a plurality of memory strings and a plurality of word lines coupled with the memory strings; the operation method comprises the following steps: applying an erasing voltage to a memory block to be erased in a first period; in a second time interval after the first time interval, conducting a top selection tube and a bottom selection tube of each memory string in the memory block to be erased so as to release charges in the channel of each erased memory string from two ends of the memory string; an erase verify operation is performed on the memory block.

Description

Operation method of memory, memory and memory system

Technical Field

The present disclosure relates to the field of semiconductor technologies, and relates to, but is not limited to, an operating method of a memory, and a memory system.

Background

Flash memory is a low cost, high density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. The flash memory includes a NOR flash memory and a NAND flash memory. The gate of the flash memory cell has a structure including a tunnel insulating layer, a floating gate electrode, a dielectric layer, and a control gate. Since the nonvolatile solid-state memory can still store data after the power is cut off, a special erase operation is required to erase the data. In the erasing operation, voltage is applied between the gate and the substrate of the flash memory unit, so that charges stored in the floating gate electrode are released, the threshold voltage of the memory unit is changed, and the purpose of erasing data is achieved.

However, after the memory cell is erased, the charges remaining in the channel tend to interfere with the subsequent data reading and writing, and therefore, how to clean up the charges remaining after erasing is an important operation for memory control.

Disclosure of Invention

In view of the above, embodiments of the present disclosure provide a method for operating a memory, a memory and a memory system.

In a first aspect, the present disclosure provides a method for operating a memory, where the memory includes a memory cell array composed of a plurality of memory blocks, each of the memory blocks includes at least a plurality of memory strings and a plurality of word lines coupled to the memory strings; the method comprises the following steps:

applying an erasing voltage to a memory block to be erased in a first period;

in a second time interval after the first time interval, conducting a top selection tube and a bottom selection tube of each storage string in the storage block to be erased so as to release charges in the channel of each erased storage string from two ends of the storage string;

an erase verify operation is performed on the memory block.

In some embodiments, in a second period after the first period, turning on a top select pipe and a bottom select pipe of each memory string in the memory block to be erased includes:

applying a first turn-on voltage to a top select gate line in the memory block; wherein the top select gate line is connected to the control electrode of the top select transistor;

applying a second turn-on voltage to a bottom select gate line in the memory block; wherein the bottom select gate line is connected to the control electrode of the bottom select transistor

And in the second period, synchronously applying a first gating voltage to a first gating switch connected on the top selection grid line and a second gating switch connected on the bottom selection grid line so as to apply the first starting voltage to the top selection tube and apply the second starting voltage to the bottom selection tube.

In some embodiments, the first turn-on voltage is equal to the second turn-on voltage.

In some embodiments, the method further comprises:

applying a second gating voltage to the first gating switch and the second gating switch for a first period; the second gating voltage is less than the first gating voltage.

In some embodiments, the method further comprises:

and in the second period, turning on a discharge path in a page buffer coupled to a bit line corresponding to the memory string.

In some embodiments, the turning on the discharge path in the page buffer to which the bit line corresponding to the memory string is coupled includes:

and applying a third opening voltage to a control switch in a discharge path in a page buffer to which the bit line is coupled.

In some embodiments, the method further comprises:

applying a cutoff voltage to a control switch between the bit line and a sense node in the page buffer to disconnect a precharge path in the page buffer and a path between latches in the second period.

In some embodiments, the applying the erase voltage to the memory block to be erased in the first period includes:

applying a ground voltage to each word line of the memory block to be erased in the first period;

the erase voltage is applied to the respective bit lines or source lines of the memory block to be erased at the same time.

In some embodiments, the method further comprises:

switching the erase voltage applied to the respective bit lines or source lines to a ground voltage during the second period.

In some embodiments, the performing an erase verify operation on the memory block includes:

applying an erase verify voltage to a selected word line on the memory block; wherein the selected word line is any word line on the memory block;

applying a turn-on voltage to unselected word lines on the memory block; wherein the turn-on voltage is greater than or equal to a maximum threshold voltage of the memory cell; the erase verify voltage is less than the turn-on voltage;

and reading the memory cell corresponding to the selected word line to obtain the verification result of the erasing verification operation.

In a second aspect, an embodiment of the present disclosure provides a memory, including:

a peripheral circuit and a memory cell array composed of a plurality of memory blocks;

wherein the peripheral circuitry is configured to perform at least the method of operation of any of the embodiments described above.

In a third aspect, embodiments of the present disclosure provide a memory system, including:

a memory and a controller;

the memory at least comprises a peripheral circuit and a memory cell array composed of a plurality of memory blocks; the peripheral circuitry is at least configured to perform the method of operation of any of the embodiments described above.

According to the operation method of the memory, a method that the top selection tube and the bottom selection tube are simultaneously opened is adopted for solving the problem of channel charge residue in the erasing process of the memory block, so that channel charges can be released from two ends of a channel, the channel charge residue after erasing is reduced, and the problem of subsequent reading errors caused by the fact that channel charges promote channel potential is further reduced.

Drawings

FIG. 1 is a schematic block diagram of an exemplary system provided by embodiments of the present disclosure;

fig. 2 is a schematic structural diagram of a memory card according to an embodiment of the disclosure;

fig. 3 is a schematic structural diagram of a Solid State Drive (SSD) according to an embodiment of the disclosure;

fig. 4 is a schematic structural diagram of a memory including a memory cell array and peripheral circuits according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a memory according to an embodiment of the disclosure;

FIG. 6 is a diagram illustrating a page buffer in a peripheral circuit of a memory according to an embodiment of the disclosure;

FIG. 7 is a diagram illustrating a memory string in a memory according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a word line and a common word line in a memory according to an embodiment of the disclosure;

FIG. 9 is a schematic diagram illustrating the principle of discharging channel charges controlled by the top and bottom select gates of a memory string according to an embodiment of the present disclosure;

FIG. 10 is a waveform diagram illustrating an erase operation of a memory according to an embodiment of the present disclosure;

FIG. 11 is a flowchart of a method for operating a memory according to an embodiment of the present disclosure;

FIG. 12 is a waveform diagram illustrating an erase operation in a method for operating a memory according to an embodiment of the present disclosure;

fig. 13 is a schematic diagram illustrating states of control switches of a page buffer in an operating method of a memory according to an embodiment of the disclosure;

FIG. 14 is a diagram illustrating a state distribution of memory cells in a memory according to an embodiment of the present disclosure;

fig. 15 is a schematic structural diagram of a memory according to an embodiment of the disclosure;

fig. 16 is a schematic structural diagram of a memory system according to an embodiment of the disclosure.

Detailed Description

To facilitate an understanding of the present disclosure, the present disclosure will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein in the description of the disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As shown in fig. 1, an exemplary system 10 is illustrated in the disclosed embodiments, and the exemplary system 10 may include a host 20 and a storage system 30. Exemplary system 10 may include, but is not limited to, a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual Reality (VR) device, augmented Reality (AR) device, or any other suitable electronic device having memory 34 therein; the host 20 may be a processor (e.g., a Central Processing Unit (CPU)) or a system on chip (SoC) (e.g., an Application Processor (AP)) of the electronic device.

In the disclosed embodiment, the host 20 may be configured to transmit data to the storage system 30 or receive data from the storage system 30. Here, the storage system 30 may include a controller 32 and one or more memories 34. The Memory 34 may include, but is not limited to, a NAND Flash Memory (NAND Flash Memory), a Vertical NAND Flash Memory (Vertical NAND Flash Memory), a NOR Flash Memory (NOR Flash Memory), a Dynamic Random Access Memory (DRAM), a Ferroelectric Random Access Memory (FRAM), a Magnetic Random Access Memory (MRAM), a Phase Change Random Access Memory (PCRAM), a Resistive Random Access Memory (RRAM), a Nano Random Access Memory (NRAM), and the like.

On the other hand, the controller 32 may be coupled to the memory 34 and the host 20, and used to control the memory 34. Illustratively, the controller may be designed for operation in a low duty cycle environment, such as a Secure Digital (SD) card, compact Flash (CF) card, universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like. In some embodiments, the controller may also be designed for operation in a high duty cycle environment SSD or embedded multimedia card (eMMC) that is used as a data storage and enterprise storage array for mobile devices such as smart phones, tablets, laptops, and the like. Further, the controller may manage data in the memory and communicate with the host. The controller may be configured to control memory read, erase, and program operations; may also be configured to manage various functions with respect to data stored or to be stored in memory, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like; may also be configured to handle Error Correction Codes (ECC) with respect to data read from or written to the memory. In addition, the controller may also perform any other suitable function, such as formatting the memory, or communicating with an external device (e.g., host 20 in FIG. 1) according to a particular communication protocol. Illustratively, the controller may communicate with the external device via at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.

In embodiments of the present disclosure, the controller and the one or more memories may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the storage system may be implemented and packaged into different types of end electronic products. As shown in fig. 2, the controller 32 and the single memory 34 may be integrated into a memory card 40. The memory card 40 may include a PC card (PCMCIA, personal computer memory card international association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), an UFS, and the like. The memory card 40 may also include a memory card connector 42 that couples the memory card 40 with a host (e.g., host 20 in FIG. 1). In another embodiment as shown in FIG. 3, the controller 32 and the plurality of memories 34 may be integrated into the SSD 50. The SSD 50 may also include an SSD connector 52 that couples the SSD 50 with a host (e.g., host 20 in fig. 1). In some embodiments, the storage capacity and/or operating speed of the SSD 50 is greater than the storage capacity and/or operating speed of the memory card 40.

It should be noted that the memory according to the embodiments of the present disclosure may be a semiconductor memory, which is a solid-state electronic device manufactured by using a semiconductor integrated circuit process and storing data information. Illustratively, fig. 4 is a schematic diagram of an alternative memory 60 in an embodiment of the present disclosure. The memory 60 may be the memory 34 in fig. 1 to 3, among others. As shown in fig. 4, the memory 60 may be composed of a memory cell array 62, a peripheral circuit 64 coupled to the memory cell array 62, and the like. Here, the memory cell array may be a NAND flash memory cell array, wherein the memory cells are provided in the form of an array of NAND memory strings 66, each NAND memory string 66 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 66 can include multiple memory cells coupled in series and stacked vertically. Wherein each memory cell is configured to hold a continuous analog value, e.g., a voltage or charge, that depends on the number of electrons trapped in the memory cell area. In addition, each memory cell in the above-described memory cell array 62 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

In the embodiments of the present disclosure, the memory Cell may be a Single Level Cell (SLC) having two possible memory states and thus may store one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In other embodiments, each memory Cell is a Multi-Level Cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per Cell, three bits per Cell (also referred to as Triple Level Cell, TLC)), or four bits per Cell (also referred to as Quad Level Cell, QLC). Each MLC may be programmed to assume a range of possible nominal stored values. For example, if each MLC stores two bits of data, the MLC may be programmed to assume one of three possible programming levels from the erased state by writing one of three possible nominal storage values to the memory cell. Wherein the fourth nominal storage value may be used for the erased state.

In the embodiment of the present disclosure, the peripheral circuit may be coupled to the memory cell array through a Bit Line (BL), a Word Line (WL), a Source Line (Source Line), a Source Select Gate (SSG), and a Drain Select Gate (DSG). Here, the peripheral circuits may include any suitable analog, digital, and mixed signal circuits for facilitating operation of the memory cell array by applying and sensing voltage and/or current signals to and from each target memory cell via the bit lines, word lines, sources, SSGs, and DSGs. Furthermore, the method is simple. The peripheral circuits may also include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. Exemplarily, as shown in fig. 5. The peripheral circuit 70 includes a Page Buffer (Page Buffer)/sense amplifier 71, a column decoder/bit line driver 72, a row decoder/word line driver 73, a voltage generator 74, a control logic unit 75, a register 76, an interface 77, and a data bus 78. It should be appreciated that the peripheral circuitry 70 described above may be the same as the peripheral circuitry 64 in fig. 4, and in other embodiments, the peripheral circuitry 70 may also include additional peripheral circuitry not shown in fig. 5.

As shown in fig. 6, a page buffer 90 is shown in an embodiment of the present disclosure. The page buffer 90 may be coupled with the memory cell array 80 via a bit line BL. Each page buffer includes a pass bit line bias switch VBL_BIASConnected register set 91 and through discharge switch VBL_DISCHA discharge path connected to ground. In addition, the page buffer may further include at least one sensing node between the register set and the word line. As shown in FIG. 6, the page buffer 90 includes a sensing node SO and a sensing node SO2, and a select pipe VSO is further included between the two sensing nodes_BLK. In addition, the page buffer may further include a bit line switch V between the bit line and the page buffer_PASSAnd is used for controlling the communication between the whole page buffer and the bit line.

In the disclosed embodiment, the memory cell array may be composed of memory strings 700 as shown in fig. 7, each of which is stacked by connecting a plurality of memory cells by a channel 720 perpendicular to a substrate 710. The word line 730 is perpendicular to the channel and may surround the channel for acting as a gate electrode of the memory cell. The memory structure 740 between the gate electrode and the channel of the memory cell at least includes a tunneling layer 741, a memory layer 742 (charge trapping layer), a blocking layer 743, and the like. The memory structure may generally be a tunneling layer comprising silicon oxide, a memory layer comprising silicon nitride and a blocking layer comprising silicon oxide, i.e. a so-called ONO structure.

Each memory cell may be in an erased state or a programmed state, and there may be a plurality of programmed states. The erase state is used to indicate an original state where the memory cell is not programmed, or a state where no data is stored, and may also be understood as storing data as "0"; the programmed state is used to indicate a state in which different data is stored. For example, for the memory cells of the above-mentioned SLC, it can hold 1 bit (bit) data, so only one erased state is required to represent data "0" and one programmed state represents data "1". For the memory cell of the above MLC, which can hold 2 bits of data, one erase state is required to represent data "00", and 3 program states represent data "01", "10", and "11".

The erased state and the programmed state are substantially represented by the threshold voltages of the memory cells. Since charge trapping can be achieved in a memory cell having an ONO structure, by applying a voltage between the gate electrode and the channel, tunneling effect can be utilized to cause charges to pass through the tunneling layer to the storage layer, i.e., the charge trapping layer, so that the charges are trapped in the storage layer. Variations in the amount of charge in the storage layer can result in variations in the threshold voltage of the memory cell. Therefore, if data is to be stored in the memory cell, it can be achieved that a corresponding charge is injected into the memory cell. The process of injecting charge may be referred to herein as "programming," i.e., programming a memory cell to adjust its state from an erased state to a different programmed state.

Accordingly, if the data in the memory cell is to be erased, i.e. the memory cell is to be restored from the programmed state to the erased state, an opposite process to the programming is required to apply an opposite voltage between the gate electrode and the channel, so that the charges trapped in the storage layer pass through the tunneling layer and return to the channel by using the tunneling effect, thereby releasing the charges in the storage layer and returning the threshold voltage of the memory cell to the range of the erased state.

In the embodiment of the present disclosure, the memory cell array of the memory may be composed of a plurality of memory blocks (blocks), each memory block has a source, the bottom of a channel of each memory string in the memory block may be connected to SL of the source through a doped region in the substrate, and the top of the memory string is connected to BL. The memory block is the minimum unit of erase operation, and when erasing, a high voltage may be applied to SL or BL while maintaining the channel of the memory string in a non-conductive state, for example, 0V to the word line of each memory cell on the memory string. At this time, a high voltage of the BL or SL is coupled to the channel to raise the voltage of the channel, so that the charges stored in the storage layer tunnel into the channel, thereby implementing the erase.

In some embodiments, after applying the erase voltage, it can be confirmed by a verification process whether the erase was successful. The verify process is similar to the principle of the read operation, for example, a verify voltage in an erase state is applied to a WL (which may be referred to as a selected word line, sel Blk WL) corresponding to a memory cell to be verified, and a pass voltage Vpass is applied to other WLs (unselected word lines), and then read through the BL. If the voltage is read, i.e., the memory cell is turned on, it indicates that the threshold voltage of the memory cell is less than the verify voltage, i.e., the memory cell has been successfully erased. If the voltage is not read, i.e., the memory cell is not turned on, it indicates that the threshold voltage of the memory cell is greater than the verify voltage, i.e., the memory cell has not been successfully erased.

However, it will be appreciated that the charges in the memory layer after erase are returned to the channel, which is substantially non-conductive, and thus affect subsequent read or other operations. Therefore, the charge in the channel needs to be discharged after erasing to ensure that the subsequent operation is not affected.

For the above-described verify process, since charges remain in the channel, the channel is discharged at the start of the verify. At this time, the current generated by the discharge will generate a coupling effect on the selected word line, which causes the voltage of the selected word line to be pulled down, even to reach a negative voltage. And since each Word Line of the memory block is also coupled to a common Word Line (LWL), as shown in fig. 8. The selected word line SEL _ WL is pulled down, which may cause voltage leakage of the unselected word line UNSEL _ WL, and further cause threshold voltage shift after verification is completed, and errors may occur in subsequent read operations.

In some embodiments, a Bottom Select Gate (BSG) of the memory string may be opened to make the channel partially conductive. As shown in fig. 9, by raising the voltage of SD Vg (String Driver Gate), the BSG voltage is raised after erasing. Here, SD Vg is a switch for controlling whether or not a voltage is applied to the string selection line of each memory string in the memory block. When the SD Vg is turned on, the voltage signals applied to the BSG line and the TSG line are loaded to the control electrode of the BSG and the control electrode of the TSG. As shown in fig. 10, SD Vg is maintained at 6V during the preparation phase and the erase phase, and an erase voltage Vers is applied to BL or SL during the erase phase, so that the voltages of BSG and TSG are coupled from a low voltage vss to a higher high voltage. When the erase voltage is applied, the recovery phase is entered, and the voltages of the BSG and TSG drop back, for example, about 3V. At this time, the voltage of SD Vg is raised to 15V, so that TSG and BSG are enabled to be selected, and since the voltage of BSG is 6V and the voltage of TSG is 0V, as shown in fig. 9, BSG is turned on again to achieve the discharge purpose, and TSG maintains the off state.

Since the BSG is located at the bottom of the memory string, channel discharge can be performed by opening one end of the BSG, which enables charge to flow to the substrate quickly for subsequent erase verify operations.

However, as the number of memory layers increases, it may also be difficult to satisfy the discharge requirement after erase by just turning on the BSG, a longer discharge period is required, and there is still a tendency for charge remaining to cause the above-described abnormality after erase verification.

Accordingly, as shown in fig. 11, an embodiment of the present disclosure provides an operating method of a memory, the memory including a memory cell array composed of a plurality of memory blocks, each memory block including at least a plurality of memory strings and a plurality of word lines coupled to the memory strings; the method comprises the following steps:

step S101, applying erasing voltage to a memory block to be erased in a first period;

step S102, in a second time interval after the first time interval, conducting a top selection tube and a bottom selection tube of each storage string in the storage block to be erased so as to release charges in the channel of each erased storage string from two ends of the storage string; (ii) a

And step S103, executing erasing verification operation on the memory block.

In the embodiment of the disclosure, after the erasing voltage is applied to the memory block, the top selection tube and the bottom selection tube are simultaneously turned on, so that charges in the channel are released from two ends of the channel, the discharging speed is further increased, and the residual charges can be further reduced, so that the discharging is more sufficient.

In some embodiments, the applying the erase voltage to the memory block to be erased in step S101 includes:

applying an erasing voltage to the source electrode of the memory block to be erased, and floating the bit line connected with each corresponding memory string; or applying an erasing voltage to each bit line of the memory block to be erased, and floating the source electrode; alternatively, the erase voltage is applied to the source and each bit line of the memory block at the same time.

During the erase process, the BL can be floated by applying an erase voltage to the source, i.e., a high voltage to the SL, so that the channel of the entire memory string is not turned on, but is coupled to a high level by the high voltage of the SL, thereby generating a voltage difference with the gate (word line) of each memory cell. Similarly, erasing the memory block may also be accomplished by applying an erase voltage to the bit line, i.e., applying a high level voltage to BL, while floating the source SL, so that the channel is coupled high. In addition, the BL and the SL can be simultaneously applied with erasing voltage, and the potential of the channel is wholly raised to a high level, so that the erasing of the memory block is realized.

It is understood that the application of the erase voltage to the memory block to be erased may be a high voltage applied to either BL or SL, during which the floating channel is coupled to a high level, while TSG and BSG may be coupled from a low state to a high state. The other WLs may be grounded or provide a low voltage. Holes in the P + (P type heavy doping) polysilicon enter the channel under the action of an electric field, then enter the storage layer under the action of the electric field generated by the voltage difference between the WL and the channel, and are neutralized with electrons in the storage layer, so that the erasing effect is realized.

After this process is finished, the application of the erase voltage is stopped, so that the holes stop continuing into the memory layer. In this case, a large number of residual holes exist in the channel.

Therefore, in step S102, the top select transistor and the bottom select transistor of the memory string are opened, so that the residual charges are discharged.

In some embodiments, in the step S102, turning on the top select pipe and the bottom select pipe of each memory string in the memory block in a second time period after the first time period includes:

applying a first turn-on voltage to a top select gate line in the memory block; wherein, the top selection grid line is connected to the control electrode of the top selection tube;

applying a second turn-on voltage to a bottom select gate line in the memory block; wherein, the bottom selection grid line is connected to the control electrode of the bottom selection tube;

and synchronously applying gating voltage to a first gating switch connected on the top selection grid line and a second gating switch connected on the bottom selection grid line in a second time interval so as to apply the first starting voltage to the top selection tube and apply the second starting voltage to the bottom selection tube.

The memory block is composed of a multi-layer stacked structure in which conductive layers and insulating layers, which are alternately stacked, are planarly arranged in a direction perpendicular to a memory string channel, and each of the conductive layers may be used as a word line of a memory cell to control the memory cell of an ONO structure located at a sidewall of the channel. The conductive layer at the top of the stacked structure, i.e., the top select gate line TSG, and the conductive layer at the bottom of the stacked structure, i.e., the bottom select gate line BSG, are shown in fig. 9.

In some embodiments, the first and second turn-on voltages V1 and V2 may be applied to the top and bottom select gate lines TSG and BSG, respectively, during the second period, so that the select tubes at both ends of the channel are turned on.

In addition, the TSG and the BSG may be connected to gate switches, respectively. That is, the first gate switch SD _ Vg1 is connected to the TSG for gating the TSG. The second gate switch SD _ Vg2 is connected to the BSG for gating the BSG.

Therefore, the time of applying the voltage to the transistors at two ends of the channel can be controlled by the gating switch without changing the voltage applied to the TSG and the BSG, so that the purpose of controlling the on-off of the channel is achieved.

In some embodiments, the first turn-on voltage is equal to the second turn-on voltage. The equal starting voltage is provided for the top selection grid line and the bottom selection grid line, so that the top selection tube and the bottom selection tube have the same starting degree, and the charge is conveniently released from the channel. Also, the TSG and BSG may be connected to the same gate switch SD. After the application of the erase voltage is completed, the first start voltage may be applied to the top selection gate line and the second start voltage may be applied to the bottom selection gate line by turning on the gate switch SD. Because the top selection grid line is connected with the control electrode of the TSG, and the bottom selection grid line is connected with the control electrode of the BSG, the first starting voltage and the second starting voltage can be synchronously applied to the TSG and the BSG, and then the TSG and the BSG are opened, and channel charges are released.

It should be noted that the first period may be in an erasing phase as shown in fig. 12, and the second period may be in a recovery phase after the erasing phase.

In some embodiments, the method further comprises:

in the first period, a second gate voltage is applied to the first gate switch and the second gate switch, and the second gate voltage is less than the first gate voltage.

Illustratively, as shown in fig. 12, the gate switches SD connected to the TSG and the BSG during the erase phase may provide a second lower gate voltage, such as ground, or 6V voltage. The TSG and BSG are actually off due to the high channel potential during the erase phase.

And switches to a second period, such as the recovery stage in fig. 12, the gate voltage of the gate switch SD may be raised to the first gate voltage, for example, 15V. At this time, the BSG and the TSG are synchronously turned on, so that both ends of the channel are in a conducting state, and channel charges are conveniently released from both ends.

In some embodiments, the method further comprises:

and in a second period, starting a discharge path in a page buffer coupled with a corresponding bit line of the memory string.

In some embodiments, the opening of the discharge path in the page buffer to which the bit line corresponding to the memory string is coupled includes:

In some embodiments, the method further comprises:

applying a turn-off voltage to a control switch between the bit line and a sense node in the page buffer to disconnect a precharge path in the page buffer and a path between latches during the second period.

It will be appreciated that the memory strings are connected to bit lines BL which are connected to other blocks of peripheral circuitry through page buffers as shown in figure 6. Since the bit line is not directly grounded, a path from the bit line BL to ground Gnd is also provided when channel charges are discharged by turning on the TSG.

Exemplarily, as shown in fig. 13, in the embodiment of the present disclosure, the control switch between the BL and the sensing nodes SO and SO2 of the page buffer 90 may be turned off, and the discharge switch of the discharge path may be turned on. Specifically, the switch VBL is biased to the bit line_BIASAnd switch VSO_BLKApplying a cut-off voltage causes the path to open, while the bit line switch V is open_PASSAnd to discharge switch VBL_DISCHAnd a bit line switch V_PASSThe turn-on voltage (i.e., the third turn-on voltage) is applied to turn on the discharge path. Thus, the residual charge in the channel can pass through the bitThe wire is released to the discharge path to achieve the purpose of releasing the charge quickly.

It should be noted that the step of performing the erase operation, that is, applying the erase voltage to the memory block to be erased in the first period of time, may specifically include:

In some embodiments, in step S103, the performing an erase verification operation on the memory block includes:

The verification process described above may be performed sequentially for different word lines, with an erase verify voltage applied to a selected word line of the memory block and a turn-on voltage applied to the other word lines, similar to the read process. The process of reading the memory cell corresponding to the selected word line specifically includes: applying a voltage on the bit line, it is possible to detect whether the channel is conducting through the sense node to which the bit line is connected. If the channel is turned on, it indicates that the erase verify voltage is greater than the threshold voltage of the memory cell coupled to the selected word line, i.e. the memory cell is successfully erased. If the channel is not conducted, it means that the erase verify voltage is less than the threshold voltage of the memory cell, i.e. the memory cell fails to erase.

It will be appreciated that the erase verify described above is shown in FIG. 14Voltage V_vf0Is defined based on the target threshold voltage Vth after erase. That is, the threshold voltage Vth of the successfully erased memory cell should be less than the erase verify voltage V_vf0Thus, during verification, the threshold voltage Vth is greater than the erase verify voltage V as long as the memory cell is still in the P1 state, P2 state, P3 state, and other states that have not been successfully erased_vf0Thereby causing the memory cell to fail to conduct; only after successful erase, the threshold voltage Vth of the memory cell is less than the erase verify voltage V_vf0. That is, if the erase success indicates that the memory cell has entered the erased state E0 with a maximum threshold voltage of V1, then the erase verify voltage V is set_vf0Should be greater than or equal to V1.

As shown in fig. 15, an embodiment of the present disclosure further provides a memory 100, including:

a peripheral circuit 110 and a memory cell array 120 composed of a plurality of memory blocks;

wherein the peripheral circuit 110 is at least configured to perform the operation method of any of the above embodiments. That is, the operation methods provided in any of the above embodiments can be applied to the memory 100.

As shown in fig. 16, an embodiment of the present disclosure further provides a memory system 200, including:

a memory 210 and a controller 220;

the memory 210 includes at least a peripheral circuit and a memory cell array composed of a plurality of memory blocks; the peripheral circuitry is at least configured to perform the method of operation as described in any of the embodiments above. The memory 210 may also be the memory 100 shown in fig. 12 in the above embodiment.

The features disclosed in the several method or apparatus embodiments provided in this disclosure may be combined in any combination to arrive at a new method or apparatus embodiment without conflict.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method for operating a memory, the memory comprising a memory cell array composed of a plurality of memory blocks, each of the memory blocks comprising at least a plurality of memory strings and a plurality of word lines coupled to the memory strings; the method comprises the following steps:

applying an erasing voltage to a memory block to be erased in a first period;

in a second time interval after the first time interval, conducting a top selection tube and a bottom selection tube of each memory string in the memory block to be erased so as to release charges in the channel of each memory string after erasing from two ends of the memory string;

an erase verify operation is performed on the memory block.

2. The operating method according to claim 1, wherein the turning on the top select pipe and the bottom select pipe of each memory string in the memory block to be erased in a second period after the first period comprises:

applying a first turn-on voltage to a top select gate line in the memory block; wherein the top select gate line is connected to a control electrode of the top select transistor;

applying a second turn-on voltage to a bottom select gate line in the memory block; wherein the bottom select gate line is connected to a control electrode of the bottom select transistor;

3. The method of claim 2, wherein the first turn-on voltage is equal to the second turn-on voltage.

4. The method of operation of claim 2, further comprising:

applying a second gate voltage to the first gate switch and the second gate switch for a first period; the second gate voltage is less than the first gate voltage.

5. The method of operation of claim 1, further comprising:

and in the second period, turning on a discharge path in a page buffer to which the corresponding bit line of the memory string is coupled.

6. The method of claim 5, wherein the turning on the discharge path in the page buffer to which the bit line corresponding to the memory string is coupled comprises:

applying a third open voltage to a control switch in a discharge path in a page buffer to which the bit line is coupled.

7. The method of operation of claim 5, further comprising:

8. The method of claim 1, wherein applying the erase voltage to the memory block to be erased in the first period of time comprises:

9. The method of operation of claim 8, further comprising:

switching the erase voltage applied on the respective bit line or source line to a ground voltage during the second period.

10. The operating method according to any one of claims 1 to 9, wherein the performing an erase verification operation on the memory block includes:

11. A memory, the memory comprising:

wherein the peripheral circuitry is at least configured to perform the method of operation of any of claims 1 to 10.

12. A memory system, the memory system comprising:

a memory and a controller;

the memory comprises at least a peripheral circuit and a memory cell array composed of a plurality of memory blocks; the peripheral circuitry is at least configured to perform the method of operation of any of claims 1 to 10.