CN114328333B - Silicon chip based on annular bus and configuration method thereof - Google Patents
Silicon chip based on annular bus and configuration method thereof Download PDFInfo
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- CN114328333B CN114328333B CN202111505362.2A CN202111505362A CN114328333B CN 114328333 B CN114328333 B CN 114328333B CN 202111505362 A CN202111505362 A CN 202111505362A CN 114328333 B CN114328333 B CN 114328333B
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 47
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 47
- 239000010703 silicon Substances 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims description 22
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Abstract
The invention provides a silicon chip based on a ring bus, which comprises an interface module, at least two functional modules and a first functional module, wherein the interface module corresponds to a master node; the interface module is connected with each functional module in series through a ring bus, and the interface module transmits a data packet through the ring bus to configure each functional module.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a silicon chip based on a ring bus and a configuration method thereof.
Background
The prior art discloses a method for connecting a plurality of modules in a ring bus mode, but the ring bus transmission rate is limited, so that the requirement of rapid configuration of the plurality of modules in a silicon chip cannot be met. In addition, the prior art also discloses a mixed ring bus interconnection piece based on a processor, so that the configuration of each functional unit by the ring bus is realized, but the configuration of the module in the silicon chip cannot be realized.
Disclosure of Invention
Aiming at the defects existing in the prior art, the invention mainly aims to provide a silicon chip based on a ring bus and a configuration method thereof, and adopts a ring bus structure, so that the time sequence convergence under the working frequency of up to 500MHz can be realized in the silicon chip based on the parallel multi-bit wide data transmission characteristic, the high data transmission can be realized, and the modules in the silicon chip can be rapidly configured.
In order to achieve the above object, the present invention provides a silicon chip based on a ring bus, comprising:
an interface module corresponding to a master node; and
at least two functional modules respectively corresponding to a slave node;
the interface module is connected with each functional module in series through a ring bus, and the interface module transmits a data packet through the ring bus to configure each functional module.
The silicon chip based on the annular bus, wherein the annular bus comprises:
an active signal line;
a handshake signal line; and
a 67-bit data line, comprising: a 32-bit addressing address signal line, a 32-bit operand signal line, a 1-bit parallel data packet valid signal line, a 1-bit write completion packet flag signal line, and a 1-bit read completion packet flag signal line.
The silicon chip based on the annular bus, wherein the interface module and each functional module respectively comprise a data input interface and a data output interface, and the annular bus is connected in series from beginning to end through the data input interface and the data output interface.
The silicon chip based on the annular bus, wherein the front ends of the silicon chip, the interface module and the at least two functional modules are designed by HDL language.
The silicon chip based on the ring bus, wherein registers are arranged in the master node and each slave node.
In order to achieve the above object, the present invention further provides a method for configuring a silicon chip based on a ring bus, which includes:
step 1, a master node corresponding to an interface module sends a configuration data packet to a slave node corresponding to a next function module connected with the configuration data packet through a ring bus;
step 2, the slave node analyzes the configuration data packet, judges whether the address of the configuration data packet hits the configuration space address, if yes, executes step 3, otherwise, executes step 4;
step 3, the slave node further analyzes the operation mode of the configuration data packet: if the operation mode is a write operation, writing the data in the configuration data packet into a register corresponding to the slave node; if the operation mode is a read operation, reading the data in the register corresponding to the slave node, writing the data into the configuration data packet, and forwarding the data to the next slave node of the current slave node until the data returns to the master node; and
and 4, forwarding the configuration data packet to the next slave node of the current slave node, and re-executing the operation of the step 2 by the next slave node.
In the configuration method of the silicon chip based on the ring bus, the configuration data packet is obtained by analyzing the configuration data packet by the master node according to the received instruction sent by a microcontroller connected with the interface module.
The configuration method of the silicon chip based on the annular bus comprises the steps that the annular bus comprises an effective signal line, a handshake signal line and a 67-bit data line;
the 67-bit data line comprises a 32-bit addressing address signal line, a 32-bit operand signal line, a 1-bit parallel data packet valid signal line, a 1-bit writing completion packet mark signal line and a 1-bit reading completion packet mark signal line.
In the above configuration method of a silicon chip based on a ring bus, in step 2, the slave node determines whether the address of the configuration data packet hits the configuration space address according to the data on the 32-bit addressing address signal line carried by the configuration data packet;
in step 3, the write operation is to write the data of the configuration data packet on the 32-bit operand signal line to the register corresponding to the address on the 32-bit address signal line, and set the 1-bit write completion packet flag signal line to 1; the read operation is to read the register data corresponding to the address on the 32-bit addressing address signal line and place the register data on the 67-bit data line, juxtapose the 1-bit read completion packet flag signal line as 1, then forward the configuration data packet to the next slave node, and after the next slave node receives the configuration data packet, parse the configuration data packet to the 1-bit read completion packet flag signal line as 1, directly forward the configuration data packet to the next slave node until the configuration data packet returns to the master node.
In the configuration method of the silicon chip based on the ring bus, after receiving the configuration data packet, the master node judges whether the master node completes the reading operation, if yes, the configuration data packet is returned to the microcontroller, and if not, the configuration data packet is discarded.
The invention will now be described in more detail with reference to the drawings and specific examples, which are not intended to limit the invention thereto.
Drawings
Fig. 1 is a schematic structural diagram of a silicon chip based on a ring bus according to an embodiment of the present invention.
Fig. 2 is a flowchart of a configuration method of a silicon chip based on a ring bus according to an embodiment of the present invention.
Detailed Description
The structural and operational principles of the present invention are described in detail below with reference to the accompanying drawings:
the ring bus is a data transmission path formed by a group of parallel buses in a ground ring topology, and is composed of a master node and a plurality of slave nodes. Each slave node is connected with a functional module and is used for configuring configuration parameters of the management functional module. Through the ring topology, the master node can realize broadcasting initiation of configuration data packets, namely, the configuration of registers with the same address on a loop can be completed by only sending one data packet. In addition, as each ring bus node is connected in series, the architecture avoids the problem of timing convergence in the design of a long lead pair back end.
The embodiment of the invention provides a silicon chip based on a ring bus, which comprises an interface module corresponding to a master node and at least two functional modules corresponding to slave nodes respectively; the interface module is connected with each functional module in series through a ring bus, and the interface module transmits a data packet through the ring bus to configure each functional module. In the present embodiment, referring to fig. 1, the silicon chip 1 is illustrated as including an interface module 80 and seven functional modules 10-70 (the first functional module 10 to the seventh functional module 70), but the present invention is not limited thereto, and in practical application, the silicon chip 1 may have other numbers of functional modules; the interface module 80 corresponds to the master node 81 and the first to seventh functional modules 10 to 70, and corresponds to the first to seventh slave nodes 11 to 71, respectively. The functional modules in the silicon chip 1, including the first functional module 10 to the seventh functional module 70 and the interface module 80, are connected by a ring bus, and the silicon chip is a chip developed under the silicon semiconductor process, and the front end design of the silicon chip and the functional modules inside the silicon chip are designed by HDL language, and the functional modules inside the silicon chip are separated according to the functions of the whole chip.
In the present embodiment, the master node 81 corresponding to the interface module 80 performs sending out configuration data packets and receiving looped-back data packets, each function module (the first function module 10 to the seventh function module 70) resides in each corresponding slave node (the first slave node 11 to the seventh slave node 71) of the ring bus, the configuration space of each function module is subjected to reading operation or writing operation by its corresponding slave node, the parameters of each function module in the silicon chip are configured through the ring bus, and the transmission task exists in the form of parallel data. Wherein parallel data refers to transmission of multi-bit data within 1 clock.
In this embodiment, the ring bus includes 1 effective signal line, 1 handshake signal line, and 67 bit data lines. The 67-bit data line is composed of a 32-bit addressing address signal line, a 32-bit operand signal line, a 1-bit parallel data packet valid signal line, a 1-bit write completion packet mark signal line and a 1-bit read completion packet mark signal line. The 67-bit data line is used for transmitting parallel configuration data packets, wherein a 32-bit addressing address signal line is used for indicating the configuration address of the current configuration data packet, a 32-bit operand signal line is used for indicating the data of the current configuration data packet for configuring the configuration address, a 1-bit parallel data packet valid signal line is used for indicating whether the 67-bit data line is valid, a 1-bit write completion packet mark signal line is used for indicating whether the current configuration data packet has a completion write operation, and a 1-bit read completion packet mark signal line is used for indicating whether the current configuration data packet has a completion read operation; and 1 effective signal line and 1 handshake signal line in the ring bus are used for guaranteeing that the configuration data packet of the functional module in the ring bus configuration silicon chip can be effectively and reliably transmitted, wherein the function of the 1-bit effective signal line is used for indicating whether the parallel data packet at the current moment is effective or not, and the function of the 1-bit handshake signal line is used for indicating whether the slave node is in a state capable of receiving data or not. In addition, each module (including the first functional module 10 to the seventh functional module 70 and the interface module 80) in the silicon chip 1 is provided with a group of ring bus data input interfaces and ring bus data output interfaces, and each functional module 10 to 70 in the silicon chip 1 is serially connected with the ring bus data input and output interfaces of the interface module 80 end to end, namely, the ring bus data output interface of the last node is connected to the ring bus data input interface of the node, the handshake signal line of the last node is connected to the handshake signal interface of the node, the effective signal line of the last node is connected to the effective signal interface of the node, and so on, so as to form a ring topology.
In this embodiment, the master node may implement configuration management on each functional module in the silicon chip 1 through the ring bus, and since each slave node of the ring bus has a configured register, the configured register may be configured by the ring bus data input and output interface, and the configuration result of the register directly acts on each functional module in the silicon chip 1, thereby implementing configuration on each functional module in the silicon chip 1.
Referring to fig. 2, based on the same inventive concept, an embodiment of the present invention further provides a configuration method of a silicon chip based on a ring bus, including:
step S10, the master node corresponding to the interface module sends a configuration data packet to the slave node corresponding to the next function module connected with the master node through the ring bus. For example, as shown in fig. 1, the master node 81 transmits a configuration data packet to the first slave node 11 connected thereto through the ring bus.
Step S20, the slave node parses the configuration data packet, determines whether the address of the configuration data packet hits the configuration space address, if yes, executes step S30, otherwise executes step S40. For example, as shown in fig. 1, the first slave node 11 analyzes the configuration packet transmitted from the master node 81, and determines whether it hits its own configuration space address.
Step S30, the slave node further analyzes the operation mode of the configuration data packet: if the operation mode is a write operation, writing the data in the configuration data packet into a register corresponding to the slave node (step S31); if the operation mode is a read operation, the data in the register corresponding to the slave node is read and written into the configuration data packet, and forwarded to the next slave node of the current slave node until the master node is returned (step S32). For example, as shown in fig. 1, if the address of the configuration data packet hits the configuration space address of the first slave node 11, the first slave node 11 further determines the operation mode of the configuration data packet; when the data in the configuration data packet is written into the register corresponding to the first slave node 11 in the write operation, when the data in the register corresponding to the first slave node 11 is read in the read operation, the data is written into the configuration data packet, the data is forwarded to the second slave node 21 to the seventh slave node 71, and the seventh slave node 71 loops the data back to the master node 81.
Step S40, forwarding the configuration data packet to the next slave node of the current slave node, where the next slave node re-executes the operation of step S20. For example. As shown in fig. 1, if the address of the configuration packet does not hit the configuration space address of the first slave node 11, the first slave node 11 directly forwards the configuration space address to the second slave node 21, and at this time, the second slave node 21 re-performs the operation of step S20.
In an embodiment of the present invention, the configuration data packet is parsed by the master node according to a command received by the master node and sent by a microcontroller connected to the interface module. As shown in fig. 1, the master node 81, for example, receives an instruction issued by an external MCU (micro control unit) of the chip through an I2C serial transmission bus interface, analyzes and processes the instruction into format data agreed by a ring bus, and the configuration data packet is initiated by the master node 81, and the master node 81 issues the configuration data packet to the first slave node 11.
In one embodiment of the present invention, the ring bus includes an active signal line, a handshake signal line, and a 67-bit data line; the 67-bit data lines include a 32-bit address signal line, a 32-bit operand signal line, a 1-bit parallel data packet valid signal line, a 1-bit write completion packet flag signal line, and a 1-bit read completion packet flag signal line.
In the above step S20, the slave node determines whether the address of the configuration data packet hits in its configuration space address according to the data on the 32-bit address signal line carried by the configuration data packet.
In the above step S30, the write operation is to write the data of the configuration data packet on the 32-bit operand signal line to the register corresponding to the address on the 32-bit address signal line, and set the 1-bit write completion packet flag signal line to 1; the read operation is to read the register data corresponding to the address on the 32-bit addressing address signal line and place the register data on the 67-bit data line, juxtapose the 1-bit read completion packet flag signal line as 1, then forward the configuration data packet to the next slave node, and after the next slave node receives the configuration data packet, parse the configuration data packet to the 1-bit read completion packet flag signal line as 1, directly forward the configuration data packet to the next slave node until the configuration data packet returns to the master node.
In an embodiment of the present invention, after receiving the configuration data packet, the master node determines whether it completes the read operation, if so, returns the configuration data packet to the microcontroller, otherwise, discards the configuration data packet.
The master node is a node that can send and receive the loopback data packet, i.e. the master node is a node that can actively send out the configuration data packet through the ring bus and receive the configuration data packet looped back by the slave node. The slave node is a node for receiving the configuration data sent from the master node and the configuration data packet of the return read request, namely, the slave node can only passively receive the configuration data packet sent from the last node, analyze the configuration data packet and process the configuration data packet, and send the processing result to the next node.
It should be noted that, for convenience and brevity, specific working procedures of the method, apparatus and module described above may refer to corresponding procedures in the foregoing embodiments, which are not described in detail herein.
Of course, the present invention is capable of other various embodiments and its several details are capable of modification and variation in light of the present invention, as will be apparent to those skilled in the art, without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (8)
1. A silicon chip based on a ring bus, comprising:
an interface module corresponding to a master node; and
at least two functional modules respectively corresponding to a slave node;
the interface module is connected with each functional module in series through a ring bus, and the interface module transmits a data packet through the ring bus to configure each functional module;
the ring bus includes:
an active signal line;
a handshake signal line; and
a 67-bit data line, comprising:
a 32-bit address signal line;
a 32-bit operand signal line;
a 1-bit parallel data packet valid signal line;
a 1-bit write completion packet flag signal line; and
a 1-bit read completion packet flag signal line.
2. The silicon chip based on the ring bus as set forth in claim 1, wherein the interface module and each of the functional modules respectively include a data input interface and a data output interface, and the ring bus is connected end to end in series through the data input interface and the data output interface.
3. The ring bus based silicon chip of claim 1, wherein the silicon chip, the interface module, and the at least two functional module front ends are designed by HDL language.
4. The ring bus based silicon chip of claim 1, wherein the master node and each of the slave nodes have registers therein.
5. A method for configuring a silicon chip based on a ring bus, comprising:
step 1, a master node corresponding to an interface module sends a configuration data packet to a slave node corresponding to a next function module connected with the configuration data packet through a ring bus;
step 2, the slave node analyzes the configuration data packet, judges whether the address of the configuration data packet hits the configuration space address, if yes, executes step 3, otherwise, executes step 4;
step 3, the slave node further analyzes the operation mode of the configuration data packet: if the operation mode is a write operation, writing the data in the configuration data packet into a register corresponding to the slave node; if the operation mode is a read operation, reading the data in the register corresponding to the slave node, writing the data into the configuration data packet, and forwarding the data to the next slave node of the current slave node until the data returns to the master node; and
step 4, forwarding the configuration data packet to the next slave node of the current slave node, and re-executing the operation of step 2 by the next slave node;
the ring bus comprises an effective signal line, a handshake signal line and a 67-bit data line;
the 67-bit data line comprises a 32-bit addressing address signal line, a 32-bit operand signal line, a 1-bit parallel data packet valid signal line, a 1-bit writing completion packet mark signal line and a 1-bit reading completion packet mark signal line.
6. The method for configuring a ring bus based silicon chip as defined in claim 5,
the configuration data packet is obtained by analyzing the main node according to the received instruction sent by a microcontroller connected with the interface module.
7. The method for configuring a ring bus based silicon chip as defined in claim 5,
in step 2, the slave node judges whether the address of the configuration data packet hits the configuration space address according to the data on the 32-bit addressing address signal line carried by the configuration data packet;
in step 3, the write operation is to write the data of the configuration data packet on the 32-bit operand signal line to the register corresponding to the address on the 32-bit address signal line, and set the 1-bit write completion packet flag signal line to 1; the read operation is to read the register data corresponding to the address on the 32-bit addressing address signal line and place the register data on the 67-bit data line, juxtapose the 1-bit read completion packet flag signal line as 1, then forward the configuration data packet to the next slave node, and after the next slave node receives the configuration data packet, parse the configuration data packet to the 1-bit read completion packet flag signal line as 1, directly forward the configuration data packet to the next slave node until the configuration data packet returns to the master node.
8. The method of claim 6, wherein the master node determines whether it has completed the read operation after receiving the configuration packet, and if so, returns the configuration packet to the microcontroller, otherwise discards the configuration packet.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101013312A (en) * | 2007-01-15 | 2007-08-08 | 大连光洋科技工程有限公司 | Private chip for implementing bus controller function in ring bus numerical control system |
| CN104461979A (en) * | 2014-11-04 | 2015-03-25 | 中国电子科技集团公司第三十八研究所 | Multi-core on-chip communication network realization method based on ring bus |
| CN108270652A (en) * | 2017-12-29 | 2018-07-10 | 北京纳米维景科技有限公司 | A kind of high speed real-time bus system and its data processing method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060041715A1 (en) * | 2004-05-28 | 2006-02-23 | Chrysos George Z | Multiprocessor chip having bidirectional ring interconnect |
-
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101013312A (en) * | 2007-01-15 | 2007-08-08 | 大连光洋科技工程有限公司 | Private chip for implementing bus controller function in ring bus numerical control system |
| CN104461979A (en) * | 2014-11-04 | 2015-03-25 | 中国电子科技集团公司第三十八研究所 | Multi-core on-chip communication network realization method based on ring bus |
| CN108270652A (en) * | 2017-12-29 | 2018-07-10 | 北京纳米维景科技有限公司 | A kind of high speed real-time bus system and its data processing method |
Non-Patent Citations (2)
| Title |
|---|
| 屈玉峰等.环形总线研究及实现.《2011年(第九届)中国通信集成电路技术与应用研讨会暨中国通信学会通信专用集成电路委员会十周年年会论文集》.2011,1 引言、2 环路的总体架构、3 数据格式、4.1 传输协议，图1-2. * |
| 环形总线研究及实现;屈玉峰等;《2011年(第九届)中国通信集成电路技术与应用研讨会暨中国通信学会通信专用集成电路委员会十周年年会论文集》;1 引言、2 环路的总体架构、3 数据格式、4.1 传输协议，图1-2 * |
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