CN108712242B - System and method for improving signaling processing capacity in packet equipment - Google Patents
System and method for improving signaling processing capacity in packet equipment Download PDFInfo
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Abstract
The invention discloses a system and a method for improving signaling processing capacity in packet equipment, and relates to the field of communication bearer networks. The system comprises an SoC FPGA, wherein the SoC FPGA comprises a logic processing module and an HPS, and the logic processing module and the HPS jointly realize the function of forwarding the signaling. The invention strips the signaling processing function from the board card CPU, and the SOC FPGA independently undertakes, and selects the logic processing module and the HPS in the SOC FPGA to process different types of signaling messages by a flexible configuration mode, thereby accelerating the issuing speed of service configuration.
Description
Technical Field
The invention relates to the field of communication bearing networks, in particular to a system and a method for improving signaling processing capacity in packet equipment.
Background
The grouping devices as the bearing network transmit management and control information through Ethernet messages, and the Ethernet messages carrying the management and control information are called signaling for short. Referring to fig. 1, an existing packet device includes a main control unit, a board CPU (Central processing unit), and a signaling transceiving interface, where the board CPU includes a signaling control unit and a single-disk management and configuration processing unit, and a signaling is generated by the main control unit of the packet device and transmitted to the main control unit of an adjacent packet device through a service channel or a dedicated channel interconnected between devices. The signaling control unit in the same grouping device realizes the signaling forwarding processing between the main control unit and the signaling transceiving interface, and the main process is as follows: from the direction of the main control unit to the signaling transceiving interface, the signaling control unit completes the processing from the encapsulation of the main control signaling to the encapsulation of the forwarding signaling; and in the direction from the signaling transceiving interface to the main control unit, the signaling control unit completes the processing from the signaling transmission and reception packaging to the main control signaling packaging.
And the board card CPU simultaneously realizes the function of the signaling control unit on the basis of completing board card management and service configuration processing. From the direction from the signaling transceiving interface to the main control unit, the signaling control unit classifies the signaling messages extracted according to the determined rule, and encapsulates the signaling messages in different formats outside according to the requirements of the main control unit, and the messages which do not accord with the matching rule are discarded.
Referring to fig. 1, the signaling control unit completes the logical judgment and forwarding of the message between the main control unit and the signaling transceiving interface, the main control unit completes the generation and termination of the standard signaling message, and the signaling transceiving interface completes the transmission of the standard signaling message at the physical interface and extracts the signaling message received by the node. From the direction of the main control unit to the signaling transceiving interface, the signaling control unit completes the encapsulation of the standard signaling message in the equipment, and after carrying certain processing information, the signaling transceiving interface correctly sends out the signaling; and in the direction from the signaling receiving and sending interface to the main control unit, after the signaling control unit carries certain processing information, the main control unit identifies the signaling receiving interface and corresponding service information, so that the main control unit can conveniently and correctly process signaling logic.
Specifically, in the direction from the main control unit to the signaling transceiving interface, the signaling control unit receives the signaling message transmitted by the main control unit, and interacts with the single-disk management and configuration processing unit to process the signaling type, the service type, the interface information and the like carried in the signaling message, convert the signaling type, the service type, the interface information and the like into information required by the forwarding flow identified by the signaling transceiving interface, and then transmit the information to the signaling transceiving interface. From the direction from the signaling receiving and transmitting interface to the main control unit, the signaling control unit interacts with the single-disk management and configuration processing unit, converts the forwarding flow information in the message transmitted by the signaling receiving and transmitting interface into the signaling type, the service type, the interface information and the like identified by the main control unit, and sends the signaling type, the service type, the interface information and the like to the main control unit together with the standard signaling message.
From the main control unit to the direction of the signaling transceiving interface, the signaling control unit extracts the signaling message according to the packaging format of the received message and sends the signaling message to the opposite-end grouping equipment from the designated port through the service processing unit.
In the existing signaling message processing process, as a large amount of burst signaling messages or some attack messages are received, the signaling control unit occupies too much CPU resources, which affects the normal management and service configuration processing of the CPU on the single disk, and the normal execution of the configuration cannot be realized due to the abnormal operation of the board card. Meanwhile, due to the burst normal signaling or abnormal signaling, the main control unit cannot receive the normal signaling, so that the normal communication among the packet devices is affected, and the packet devices work abnormally.
For example: when signaling messages such as LSP (Label Switched Path ) PING are sent to the main control unit, it needs to perform logic judgment: when the three conditions are met simultaneously, the signaling message is sent in a format required by a main control unit encapsulated outside the signaling message, and due to the fact that logical judgment needs to be carried out and then discarding or sending is carried out, message receiving and sending behaviors and logical operation occupy CPU operation resources.
The existence of signaling such as LSP PING/LSP TRACE causes the signaling control unit to be unable to be implemented by hardware such as FPGA (field programmable Gate Array). The signaling interaction and processing among the packet devices are the premise that the packet devices of the bearer network work normally, and when the signaling quantity is abnormal, the consumption of CPU resources and the influence on the normal configuration processing of the CPU also become the facing problems. Therefore, a technical scheme for rapidly processing signaling without affecting normal work of a single-disk CPU is urgently needed, a normal channel for signaling uploading and issuing is established, necessary message logic processing is performed, and meanwhile, the influence on a board CPU when signaling flow is abnormal is eliminated.
On the basis of normal board management and configuration processing, the board CPU needs to process the signaling message transmission master control and the issuing port. When the CPU controls management and signaling processing, the resource consumption of the CPU is random and uncontrollable, and the two functions can be influenced mutually. For example, when a link between two packet devices fails, topology change will be interacted between the main control units of the packet devices, and routing information will be updated, and the main control units will receive a large amount of signaling and, at the same time, will issue routing configuration update to the board CPU. Due to the fact that a board CPU processes a large number of configurations, when the CPU occupancy rate is high, some received or sent signaling is discarded, and therefore signaling of other adjacent grouping devices cannot be normally received or sent. Because the sending and receiving command message consumes CPU resources, the issued configuration is accumulated at the board card CPU, and the issuing speed of the service configuration is slower.
Disclosure of Invention
The invention aims to overcome the defects of the background technology, and provides a system and a method for improving the signaling processing capacity in packet equipment.
The invention provides a system for improving signaling processing capacity in grouping equipment, which comprises a field programmable gate array (SoC FPGA) of a system-on-chip, wherein the SoC FPGA comprises a logic processing module and a hard core processor system (HPS), and the logic processing module and the HPS jointly realize the function of forwarding signaling between a main control unit and a signaling transceiving interface by a signaling control unit in a board card CPU.
On the basis of the technical scheme, the SoC FPGA interacts with an external main control unit and a signaling transceiving interface, a logic processing module classifies all signaling messages according to a protocol corresponding to the signaling messages, the signaling messages are divided into signaling messages with simple mapping and signaling messages with complex mapping, internal encapsulation stripping from the main control unit to the signaling transceiving interface is completed according to a result after the signaling messages with simple mapping are matched, and internal encapsulation increase from the signaling transceiving interface to the main control unit is completed; and the HPS judges and searches according to the result after the complex mapping signaling message is matched, and performs corresponding encapsulation according to the search result.
On the basis of the above technical solution, the logic processing module includes a packet classification unit, a simple mapping processing unit, and a packet merging unit, and the HPS includes a complex mapping processing unit, where:
the message classification unit classifies all the signaling messages according to the protocol corresponding to the special field in the signaling message and outputs the signaling messages to the simple mapping processing unit and the complex mapping processing unit;
the simple mapping processing unit completes message packaging according to an agreed format and transmits the message to the message merging unit;
the complex mapping processing unit carries out logic judgment according to the message content, discards the message which does not accord with the rule, packages the message which accords with the rule and then transmits the message to the message merging unit;
the message merging unit merges the messages output by the simple mapping processing unit and the complex mapping processing unit into the same physical channel for transmission.
On the basis of the above technical solution, the data of the packet classification unit comes from the signaling transceiving interface in the uplink direction and comes from the main control unit in the downlink direction.
On the basis of the above technical solution, the data of the message merging unit is sent to the main control unit in the uplink direction and is sent to the signaling transceiving interface in the downlink direction.
The invention also provides a method for improving the signaling processing capability in the grouping equipment based on the system, which comprises the following steps:
the logic processing module of the SoC FPGA and the HPS jointly realize the function of the signaling control unit in the board card CPU for forwarding the signaling between the main control unit and the signaling transceiving interface.
On the basis of the technical scheme, the method specifically comprises the following steps: the SoCFPGA interacts with an external main control unit and a signaling transceiving interface, the logic processing module classifies all signaling messages into signaling messages with simple mapping and signaling messages with complex mapping according to a protocol corresponding to the signaling messages, internal encapsulation stripping from the main control unit to the signaling transceiving interface is completed according to the result after the signaling messages with simple mapping are matched, and internal encapsulation increasing from the signaling transceiving interface to the main control unit is completed; and the HPS judges and searches according to the result after the complex mapping signaling message is matched, and performs corresponding encapsulation according to the search result.
On the basis of the technical scheme, the method specifically comprises the following steps:
the logic processing module comprises a message classification unit, a simple mapping processing unit and a message merging unit, and the HPS comprises a complex mapping processing unit, wherein:
the message classification unit classifies all the signaling messages according to the protocol corresponding to the special field in the signaling message and outputs the signaling messages to the simple mapping processing unit and the complex mapping processing unit;
the simple mapping processing unit completes message packaging according to an agreed format and transmits the message to the message merging unit;
the complex mapping processing unit carries out logic judgment according to the message content, discards the message which does not accord with the rule, packages the message which accords with the rule and then transmits the message to the message merging unit;
the message merging unit merges the messages output by the simple mapping processing unit and the complex mapping processing unit into the same physical channel for transmission.
On the basis of the above technical solution, the data of the packet classification unit comes from the signaling transceiving interface in the uplink direction and comes from the main control unit in the downlink direction.
On the basis of the above technical solution, the data of the message merging unit is sent to the main control unit in the uplink direction and is sent to the signaling transceiving interface in the downlink direction.
Compared with the prior art, the invention has the following advantages:
the invention strips the signaling processing function from the board CPU, and the SOC FPGA independently undertakes the signaling processing function, separates the signaling control unit from the board CPU into the SoC FPGA, and the board management and service configuration functions of the board CPU and the signaling control unit are not mutually influenced. The invention classifies all signaling messages according to the protocol corresponding to the special field in the signaling message, and the signaling messages are divided into signaling messages which are simply mapped and do not need complex logic processing and signaling messages which are complexly mapped and need complex logic processing, the signaling messages which are simply mapped are processed by a logic processing module of SoCFPGA, the signaling messages which are complexly mapped are processed by HPS of SoCFPGA, the signaling messages which are simply mapped can not occupy HPS CPU resources, and the signaling messages which are complexly mapped can realize the signaling control function which can not be realized by the logic processing module by the HPS. The simple mapping processing realized by the logic processing module and the complex mapping processing realized by the HPS utilize the advantages of hardware processing and software processing to the maximum extent, and the logic processing module in the SOC FPGA and the HPS can be selected to process different types of signaling messages in a flexible configuration mode, so that the issuing speed of service configuration can be increased.
Drawings
Fig. 1 is a flow chart of signaling processing inside a conventional packet device.
Fig. 2 is a block diagram of the overall structure of a system for improving signaling processing capability in a packet device according to an embodiment of the present invention.
Fig. 3 is a detailed block diagram of a system for enhancing signaling processing capability in a packet device according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of SoC FPGA processing receive direction signaling in the embodiment of the present invention.
Fig. 5 is a schematic diagram of SoC FPGA processing sending direction signaling in the embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the figures and the embodiments.
Example 1
Referring to fig. 2, embodiment 1 of the present invention provides a System for improving signaling processing capability in a packet device, where the System includes a System on Chip (SoC FPGA), the SoC FPGA includes a logic processing module and a Hard Processor System (HPS) software, and the logic processing module and the HPS together implement a function of a signaling control unit in a board CPU for forwarding signaling between a main control unit and a signaling transceiving interface.
The SoC FPGA is an HPS integrated with an ARM (Advanced RISCMachine, ARM processor) in an FPGA architecture, and the ARM processor is a first RISC (reduced instruction set computer) microprocessor with low power consumption and low cost designed by Acorn limited, uk. The SoC FPGA further includes a processor, peripheral devices, a memory interface, and the like, and combines the performance and low power consumption characteristics of a hard core IP (Intellectual Property) and the flexibility of programmable logic.
The board CPU still completes the work of board management and service configuration, the embodiment of the invention strips the signaling processing function from the board CPU and is independently borne by the SOC FPGA, namely the realization of the function of the signaling control unit is transferred from the board CPU to the SoCFPGA. The embodiment of the invention utilizes the characteristic that the SoC FPGA simultaneously comprises the logic processing module and the HPS, and can flexibly realize the function of the signaling control unit.
The SoC FPGA specifically implements the following functions:
the SoC FPGA is interacted with an external main control unit and a signaling transceiving interface, the SoC FPGA classifies all signaling messages according to protocols corresponding to special fields in the signaling messages, the signaling messages are divided into signaling messages which are mapped simply and do not need complex logic processing and signaling messages which need complex logic processing and are mapped complicatedly, the signaling messages which are mapped simply are processed by a logic processing module of SoCFPGA, and the signaling messages which are mapped complicatedly are processed by HPS of the SoC FPGA.
The simply mapped signaling messages do not need complex logic processing such as searching and judging, and only the logic processing module needs to perform encapsulation increase or stripping of one-to-one mapping according to the result after the simply mapped signaling messages are matched; for example: when the management signaling message occurs, the signaling control unit directly sends the management signaling message to the signaling transceiving interface of the export disk according to the export interface appointed by the main control unit. In the opposite direction, the signaling control unit directly carries interface information and sends the management signaling message to the main control unit, and the whole process does not need logic processing such as searching and judging, so that the management signaling message is used as a signaling message for simple mapping.
The complex mapped signaling message needs to be searched and judged by complex logic processing, such as an LSPPING message, the HPS needs to judge and search according to the result after the complex mapped signaling message is matched, and corresponding packaging is carried out according to the search result, so that the LSP PING message is used as the complex mapped signaling message.
And the logic processing module of the SoC FPGA completes the internal packaging stripping from the main control unit to the signaling transceiving interface direction according to the result after the signaling message which is simply mapped is matched, and the internal packaging from the signaling transceiving interface to the main control unit is increased.
The logic processing module can not process the signaling message with complex mapping, and the HPS of the SoC FPGA realizes the logic judgment and search of the message. And the HPS judges and searches according to the result after the complex mapping signaling message is matched, and performs corresponding encapsulation according to the search result.
The embodiment of the invention separates the signaling control unit from the board card CPU, and reduces the dependence on the board card CPU capacity and the mutual influence. By adopting the scheme of realizing the signaling control unit by the SoC FPGA, the HPS can be utilized to realize the processing of complex signaling, and the logic processing module is used to realize the processing of simply mapped signaling messages, thereby reducing the pressure of the HPS for processing the signaling and enhancing the processing capacity of the whole service board card signaling.
Example 2
On the basis of embodiment 1, in a system for improving signaling processing capability in a packet device, as shown in fig. 3, a logic processing module of an SoC FPGA includes a packet classification unit, a simple mapping processing unit, and a packet merging unit, the packet classification unit has a capability of software configurable classification types, and an HPS of the SoC FPGA includes a complex mapping processing unit.
The message classification unit classifies all the signaling messages into simple mapped signaling messages which do not need complex logic processing and complex mapped signaling messages which need complex logic processing according to a protocol corresponding to a special field in the signaling messages, transmits the simple mapped signaling messages to the simple mapped processing unit, and transmits the complex mapped signaling messages to the complex mapped processing unit;
the simple mapping processing unit completes message packaging according to an agreed format and transmits the message to the message merging unit;
the complex mapping processing unit carries out logic judgment according to the message content, discards the message which does not accord with the rule, packages the message which accords with the rule and then transmits the message to the message merging unit;
the message merging unit merges the messages output by the simple mapping processing unit and the complex mapping processing unit into the same physical channel for transmission.
The uplink direction is a direction from the signaling transceiving interface to the main control unit, and the downlink direction is a direction from the main control unit to the signaling transceiving interface. The data of the message classification unit comes from the signaling transceiving interface in the uplink direction and comes from the main control unit in the downlink direction. The data of the message merging unit is sent to the main control unit in the uplink direction and is sent to the signaling transceiving interface in the downlink direction.
Example 3
On the basis of embodiment 2, in a system for improving signaling processing capability in a packet device, fig. 4 describes a processing process in which a main control unit receives a signaling message, and as shown in fig. 4, a message classification unit receives the signaling message transmitted by a signaling transceiving interface, classifies all the signaling messages transmitted by the signaling transceiving interface according to a protocol corresponding to a special field in the signaling message, divides the signaling messages into signaling messages that need simple mapping without complex logic processing and signaling messages that need complex mapping with complex logic processing, transmits the signaling messages that need simple mapping to a simple mapping processing unit implemented by a logic processing module, and transmits the signaling messages that need complex mapping to a complex mapping processing unit implemented by an HPS;
the simple mapping processing unit realized by the logic processing module completes message packaging according to the agreed format and transmits the message to the message merging unit;
the complex mapping processing unit realized by the HPS carries out logic judgment according to the message content, discards the message sent by the signaling transceiving interface which does not accord with the rule, packages the message sent by the signaling transceiving interface which accords with the rule, and then transmits the message to the message merging unit;
the message merging unit merges the messages output by the simple mapping processing unit realized by the logic processing module and the complex mapping processing unit realized by the HPS into the same physical channel and transmits the messages to the main control unit.
Example 4
On the basis of embodiment 2, in a system for improving signaling processing capability in a packet device, fig. 5 describes a processing process of a main control unit sending a signaling message, and as shown in fig. 5, a message classification unit implemented by a logic processing module receives the signaling message transmitted by the main control unit, classifies all the signaling messages transmitted by the main control unit according to a protocol corresponding to a special field in the signaling message, and divides the signaling messages into signaling messages requiring simple mapping without complex logic processing and signaling messages requiring complex mapping with complex logic processing; transmitting the simply mapped signaling message to a simple mapping processing unit realized by a logic processing module, and transmitting the complex mapped signaling message to a complex mapping processing unit realized by an HPS;
the simple mapping processing unit realized by the logic processing module completes message packaging according to the agreed format and transmits the message to the message merging unit;
the complex mapping processing unit realized by the HPS carries out logic judgment according to the content of the received message, discards the message sent by the main control unit which does not accord with the rule, encapsulates the message sent by the main control unit which accords with the rule, and then transmits the encapsulated message to the message merging unit;
the message merging unit merges the messages output by the simple mapping processing unit realized by the logic processing module and the complex mapping processing unit realized by the HPS into the same physical channel and transmits the messages to the signaling transceiving interface.
Example 5
On the basis of embodiment 1, embodiment 5 of the present invention provides a method for improving signaling processing capability in a packet device based on the system in embodiment 1, including the following steps:
the logic processing module of the SoC FPGA and the HPS jointly realize the function that a signaling control unit in the board card CPU forwards signaling between the main control unit and the signaling transceiving interface: according to the fact that whether logic processing of searching and judging is needed or not, the SoCFPGA divides the signaling message into a signaling message which does not need complex logic processing and is simply mapped and a signaling message which needs complex logic processing and is complexly mapped, the signaling message which is simply mapped is processed by a logic processing module of the SoC FPGA, and the signaling message which is complexly mapped is processed by an HPS of the SoC FPGA.
And the logic processing module completes internal packaging stripping from the main control unit to the signaling transceiving interface direction according to the result after the signaling message which is simply mapped is matched, and internal packaging between the signaling transceiving interface and the main control unit is increased.
And the HPS judges and searches according to the result after the complex mapping signaling message is matched, and performs corresponding encapsulation according to the search result.
The board CPU still completes the work of board management and service configuration, the embodiment of the invention strips the signaling processing function from the board CPU and is independently borne by the SOC FPGA, namely the realization of the function of the signaling control unit is transferred from the board CPU to the SoCFPGA. The embodiment of the invention utilizes the characteristic that the SoC FPGA simultaneously comprises the logic processing module and the HPS, and can flexibly realize the function of the signaling control unit.
The SoC FPGA divides the signaling message into a simple mapping signaling message which does not need complex logic processing and a complex mapping signaling message which needs complex logic processing according to whether the logic processing of searching judgment is needed or not, the simple mapping signaling message is processed by a logic processing module of the SoC FPGA, and the complex mapping signaling message is processed by an HPS of the SoC FPGA.
The simply mapped signaling messages do not need logic processing such as searching and judging, and only the logic processing module needs to perform encapsulation increase or stripping of one-to-one mapping according to the result after the simply mapped signaling messages are matched; for example: when the management signaling message occurs, the signaling control unit directly sends the management signaling message to the signaling transceiving interface of the export disk according to the export interface appointed by the main control unit. In the opposite direction, the signaling control unit directly carries interface information and sends the management signaling message to the main control unit, and the whole process does not need logic processing such as searching and judging, so that the management signaling message is used as a signaling message for simple mapping.
The complex mapped signaling message needs to be searched and judged, for example, the LSP PING message needs to be judged and searched by the HPS according to the result of the complex mapped signaling message after matching, and corresponding encapsulation is performed according to the search result, so that the LSP PING message is used as the complex mapped signaling message.
The SoC FPGA interacts with an external main control unit and a signaling transceiving interface, a logic processing module of the SoC FPGA completes internal packaging stripping from the main control unit to the signaling transceiving interface according to a result after the signaling message is simply mapped and the internal packaging between the signaling transceiving interface and the main control unit is increased.
The logic processing module can not process the signaling message with complex mapping, and the HPS of the SoC FPGA realizes the logic judgment and search of the message. And the HPS judges and searches according to the result after the complex mapping signaling message is matched, and performs corresponding encapsulation according to the search result.
The embodiment of the invention separates the signaling control unit from the board card CPU, and reduces the dependence on the board card CPU capacity and the mutual influence. By adopting the scheme of realizing the signaling control unit by the SoC FPGA, the HPS can be utilized to realize the processing of complex signaling, and the logic processing module is used to realize the processing of simply mapped signaling messages, thereby reducing the pressure of the HPS for processing the signaling and enhancing the processing capacity of the whole service board card signaling.
Example 6
On the basis of embodiment 5, embodiment 6 of the present invention provides a method for improving signaling processing capability in a packet device, which specifically includes the following steps:
referring to fig. 3, the logic processing module includes a packet classifying unit, a simple mapping processing unit, and a packet merging unit, and the HPS includes a complex mapping processing unit;
the message classification unit classifies all the signaling messages into simple mapped signaling messages which do not need complex logic processing and complex mapped signaling messages which need complex logic processing according to a protocol corresponding to a special field in the signaling messages, transmits the simple mapped signaling messages to the simple mapped processing unit, and transmits the complex mapped signaling messages to the complex mapped processing unit;
the simple mapping processing unit completes message packaging according to an agreed format and transmits the message to the message merging unit;
the complex mapping processing unit carries out logic judgment according to the message content, discards the message which does not accord with the rule, packages the message which accords with the rule and then transmits the message to the message merging unit;
the message merging unit merges the messages output by the simple mapping processing unit and the complex mapping processing unit into the same physical channel for transmission.
The uplink direction is a direction from the signaling transceiving interface to the main control unit, and the downlink direction is a direction from the main control unit to the signaling transceiving interface. The data of the message classification unit comes from the signaling transceiving interface in the uplink direction and comes from the main control unit in the downlink direction. The data of the message merging unit is sent to the main control unit in the uplink direction and is sent to the signaling transceiving interface in the downlink direction.
Example 7
On the basis of embodiment 6, embodiment 7 of the present invention provides a method for improving signaling processing capability in a packet device, which specifically includes the following steps:
referring to fig. 4, the packet classifying unit receives the signaling packets transmitted by the signaling transceiving interface, classifies all the signaling packets transmitted by the signaling transceiving interface according to the protocol corresponding to the special field in the signaling packets, divides the signaling packets into signaling packets that are simply mapped and signaling packets that are complex mapped and do not require complex logic processing, transmits the signaling packets that are simply mapped to the simple mapping processing unit implemented by the logic processing module, and transmits the signaling packets that are complex mapped to the complex mapping processing unit implemented by the HPS;
the simple mapping processing unit realized by the logic processing module completes message packaging according to the agreed format and transmits the message to the message merging unit;
the complex mapping processing unit realized by the HPS carries out logic judgment according to the message content, discards the message transmitted by the signaling transceiving interface which does not accord with the rule, encapsulates the message transmitted by the signaling transceiving interface which accords with the rule, and transmits the encapsulated message to the message merging unit;
the message merging unit merges the messages output by the simple mapping processing unit realized by the logic processing module and the complex mapping processing unit realized by the HPS into the same physical channel and transmits the messages to the main control unit.
Example 8
On the basis of embodiment 6, embodiment 8 of the present invention provides a method for improving signaling processing capability in a packet device, which specifically includes the following steps:
referring to fig. 5, the message classifying unit receives the signaling message transmitted by the main control unit, and classifies all the signaling messages transmitted by the main control unit according to the protocol corresponding to the special field in the signaling message, and divides the signaling messages into signaling messages that need simple mapping without complex logic processing and signaling messages that need complex mapping with complex logic processing; transmitting the simply mapped signaling message to a simple mapping processing unit realized by a logic processing module, and transmitting the complex mapped signaling message to a complex mapping processing unit realized by an HPS;
the simple mapping processing unit realized by the logic processing module completes message packaging according to the agreed format and transmits the message to the message merging unit;
the complex mapping processing unit realized by the HPS carries out logic judgment according to the content of the received message, discards the message sent by the main control unit which does not accord with the rule, encapsulates the message sent by the main control unit which accords with the rule, and then transmits the encapsulated message to the message merging unit;
the message merging unit merges the messages output by the simple mapping processing unit realized by the logic processing module and the complex mapping processing unit realized by the HPS into the same physical channel and transmits the messages to the signaling transceiving interface.
The embodiment of the invention overcomes the influence on the single disk management and the configuration processing unit caused by the signaling processing of the CPU, realizes the processing of the signaling by combining the logic processing module and the HPS processing, exerts the high-efficiency and quick effect caused by the processing of the logic processing module, and also keeps the flexible and convenient effect caused by the HPS processing. Through the configuration of the message classification unit realized by the logic processing module, the signaling classification needing simple mapping and complex mapping can be flexibly configured, the impact on the signaling message processing caused by configuration issuing is solved, and the hidden danger of high occupation of a CPU (Central processing Unit) during the processing of a large number of signaling messages can be reduced.
Various modifications and variations of the embodiments of the present invention may be made by those skilled in the art, and they are also within the scope of the present invention, provided they are within the scope of the claims of the present invention and their equivalents.
What is not described in detail in the specification is prior art that is well known to those skilled in the art.
Claims (8)
1. A system for enhancing signaling processing capability in a packet device, comprising: the system comprises a system-on-chip field programmable gate array (SoC FPGA), wherein the SoC FPGA comprises a logic processing module and a hard core processor system (HPS), and the logic processing module and the HPS jointly realize the function of forwarding the signaling: the SoC FPGA interacts with an external main control unit and a signaling transceiving interface, a logic processing module classifies all signaling messages according to a protocol corresponding to the signaling messages, the signaling messages are divided into signaling messages with simple mapping and signaling messages with complex mapping, internal encapsulation stripping from the main control unit to the signaling transceiving interface is completed according to the result after the signaling messages with simple mapping are matched, and internal encapsulation increasing from the signaling transceiving interface to the main control unit is completed; and the HPS judges and searches according to the result after the complex mapping signaling message is matched, and performs corresponding encapsulation according to the search result.
2. The system for enhancing signaling processing capability within a packet device as recited in claim 1, wherein: the logic processing module comprises a message classification unit, a simple mapping processing unit and a message merging unit, and the HPS comprises a complex mapping processing unit, wherein:
the message classification unit classifies all the signaling messages according to the protocol corresponding to the special field in the signaling message and outputs the signaling messages to the simple mapping processing unit and the complex mapping processing unit;
the simple mapping processing unit completes message packaging according to an agreed format and transmits the message to the message merging unit;
the complex mapping processing unit carries out logic judgment according to the message content, discards the message which does not accord with the rule, packages the message which accords with the rule and then transmits the message to the message merging unit;
the message merging unit merges the messages output by the simple mapping processing unit and the complex mapping processing unit into the same physical channel for transmission.
3. The system for enhancing signaling processing capability within a packet device as recited in claim 2, wherein: the data of the message classification unit comes from the signaling transceiving interface in the uplink direction and comes from the main control unit in the downlink direction.
4. The system for enhancing signaling processing capability within a packet device as recited in claim 2, wherein: and the data of the message merging unit is sent to the main control unit in the uplink direction and is sent to the signaling transceiving interface in the downlink direction.
5. A method for improving signaling processing capability in a packet device based on the system of claim 1, comprising the steps of:
the logic processing module of the SoC FPGA and the HPS jointly realize the function that the signaling control unit in the board card CPU forwards the signaling between the main control unit and the signaling transceiving interface: the SoC FPGA interacts with an external main control unit and a signaling transceiving interface, a logic processing module classifies all signaling messages according to a protocol corresponding to the signaling messages, the signaling messages are divided into signaling messages with simple mapping and signaling messages with complex mapping, internal encapsulation stripping from the main control unit to the signaling transceiving interface is completed according to the result after the signaling messages with simple mapping are matched, and internal encapsulation increase from the signaling transceiving interface to the main control unit is completed; and the HPS judges and searches according to the result after the complex mapping signaling message is matched, and performs corresponding encapsulation according to the search result.
6. The method for enhancing signaling processing capability within a packet device as recited in claim 5, wherein: the method specifically comprises the following steps:
the logic processing module comprises a message classification unit, a simple mapping processing unit and a message merging unit, and the HPS comprises a complex mapping processing unit, wherein:
the message classification unit classifies all the signaling messages according to the protocol corresponding to the special field in the signaling message and outputs the signaling messages to the simple mapping processing unit and the complex mapping processing unit;
the simple mapping processing unit completes message packaging according to an agreed format and transmits the message to the message merging unit;
the complex mapping processing unit carries out logic judgment according to the message content, discards the message which does not accord with the rule, packages the message which accords with the rule and then transmits the message to the message merging unit;
the message merging unit merges the messages output by the simple mapping processing unit and the complex mapping processing unit into the same physical channel for transmission.
7. The method for enhancing signaling processing capability within a packet device as recited in claim 6, wherein: the data of the message classification unit comes from the signaling transceiving interface in the uplink direction and comes from the main control unit in the downlink direction.
8. The method for enhancing signaling processing capability within a packet device as recited in claim 6, wherein: and the data of the message merging unit is sent to the main control unit in the uplink direction and is sent to the signaling transceiving interface in the downlink direction.
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