CN114328326B

CN114328326B - Bus matrix port configurable microcontroller and internal data transmission method thereof

Info

Publication number: CN114328326B
Application number: CN202111628427.2A
Authority: CN
Inventors: 刘根贤; 崔海; 金前文; 陈建军; 罗煜森
Original assignee: Hunan Aerospace Economic Development Co ltd
Current assignee: Hunan Aerospace Economic Development Co ltd
Priority date: 2021-12-28
Filing date: 2021-12-28
Publication date: 2022-08-26
Anticipated expiration: 2041-12-28
Also published as: CN114328326A

Abstract

The invention provides a microcontroller with configurable bus matrix ports and an internal data transmission method thereof, wherein the microcontroller comprises a master device, a slave device, a bus matrix, a port module and a port configuration module arranged in a register; the port module comprises an FIFO module, a byte sequence functional module, a bit sequence functional module and a bit width functional module, wherein data entering the port module is output after passing through the FIFO module, the byte sequence functional module, the bit sequence functional module and the bit width functional module; configuration bit data of byte order, bit width and bit order are stored in the port configuration module; according to the method and the device, automatic data transmission among functional modules with different bit widths, different byte sequences and different bit sequences is realized, the interference of a processor core is reduced, and the communication efficiency among the modules of the MCU is improved.

Description

Bus matrix port configurable microcontroller and internal data transmission method thereof

Technical Field

The application relates to the technical field of single-chip microcomputers, in particular to a microcontroller with configurable bus matrix ports and an internal data transmission method thereof.

Background

MCU (micro Control unit) is also called microcontroller, which integrates CPU, RAM, ROM, timing counter and multiple I/O interfaces of computer on one chip to form chip-level computer for different combined Control in different application fields.

Fig. 1 shows a basic structural diagram of an MCU, which may specifically include:

the processor Core (CPU Core) is used to implement access and control to each functional module through a BUS MATRIX (BUS MATRIX), thereby implementing a desired function.

And the BUS MATRIX (BUS MATRIX) is used for realizing the access of system data, instructions and addresses through BUS transmission.

The function module comprises a FLASH memory, a Static Random Access Memory (SRAM), an analog-to-digital conversion module (A/D), a digital-to-analog conversion module (D/A), a TIMER (TIMER), a Direct Memory Access (DMA), a Serial Peripheral Interface (SPI) for communication between the MCU and the outside, a Controller Area Network (CAN), an Ethernet, a Universal Serial Bus (USB), a universal asynchronous receiver/transmitter (UART)Receiving/transmitting devices), I ² C (two-wire serial bus), etc. for respectively completing corresponding functions according to access or control instructions transmitted by a processor Core (CPU Core) through a bus matrix (BUSMATRIX).

Fig. 2 shows a schematic diagram of a bus matrix working structure in an existing MCU, when a master device (e.g., a CPU or a DMA) performs data transmission between a bus matrix and slave devices (e.g., a memory, various peripherals, etc.), a processor core generally initiates transmission, and through an address, a read/write control signal, etc., the slave device at the corresponding address responds to the operation of the master device, the CPU needs to initialize information of the master device and the slave device, configure parameters such as the number of data transmissions, bit sequence, bit width, etc., of the master device and the slave device, and once the bit width or bit sequence of the master device and the slave device is inconsistent, the CPU needs to convert to a consistent format to perform the transmission.

With the development of electronic technology, the CPU core is continuously upgraded and updated, and is developed from 8-bit 8031 series to 16-bit CPU core, the mainstream CPU core is 32-bit processor at present, 64-bit CPU core is also appeared, however, many peripheral interfaces, such as serial ports, SPI ports, etc., have become standard, and still transmit in 8-bit or 16-bit format, this has the problem of inconsistent bit width, and in addition, various kinds of peripheral modules have the problems of different bit widths and bit sequences, some peripheral modules are in a big-end mode, the high order is in the front, e.g., b7b6b5b4b3b2b1b0, with peripheral modules in a small-end mode, low-end front, e.g., b0b1b2b3b4b5b6b7, there are also endian problems in half-word or word transfers, such as 32-bit data 4 bytes, big-end mode Byte3Byte2Byte1Byte0, little-end mode Byte0Byte1Byte2Byte3, therefore, different types of master-slave modules are transmitted through a traditional bus matrix, and the CPU is required to be frequently intervened for conversion, so that the CPU efficiency is low.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a port function configurable bus matrix for a microcontroller and a control method thereof, which realize the automatic data transmission among master and slave modules with different bit widths, different byte sequences and different bit sequences, reduce the intervention of a processor core, improve the communication efficiency among the modules of an MCU, reduce the terminal cost of a CPU core and ensure that the CPU core can work more efficiently.

The specific scheme of the invention is as follows:

a microcontroller with configurable bus matrix ports comprises a bus matrix, a plurality of master devices and a plurality of slave devices, wherein the master devices access and control the slave devices through the bus matrix, and data transmission is realized between the master devices and the slave devices through the bus matrix; the controller also comprises a port module 4 arranged between the master device 1 and the bus matrix 3 and/or between the slave device 2 and the bus matrix 3, and a port configuration module arranged in the register;

the port module comprises an FIFO module, a byte sequence functional module, a bit sequence functional module and a bit width functional module, wherein data entering the port module is output after passing through the FIFO module, the byte sequence functional module, the bit sequence functional module and the bit width functional module;

configuration bit data of byte order, bit width and bit order are stored in the port configuration module;

the FIFO module is used for caching data, the byte sequence function module realizes byte sequencing of output data according to parameters of the port configuration module, the bit sequence function module realizes bit sequencing of the output data according to the parameters of the port configuration module, and the bit width function module realizes conversion from input bit width to output bit width according to the parameters of the port configuration module.

In the microcontroller with the configurable bus matrix port, the FIFO module, the byte sequence functional module, the bit sequence functional module and the bit width functional module are interconnected in a logic circuit connection mode.

In the microcontroller with the configurable bus matrix port, the array transmission bit width of the main equipment is the same as the bit number of the CPU core.

In the microcontroller with the configurable bus matrix port, the byte sequence functional module, the bit sequence functional module and the bit width functional module respectively realize gating configuration through corresponding two-bit decoders.

In the microcontroller with the configurable bus matrix port, the master device is a CPU or a DMA, and the slave device is a memory or an external device.

The internal data transmission method of the microcontroller with the configurable bus matrix port comprises the following steps:

【1】 The CPU core program selects a master device and a slave device which need to transmit data;

【2】 The CPU core program reads the parameter information of the port configuration module and configures the bit width, the bit sequence and the byte sequence of data for the port module corresponding to the master device or the slave device, so that the format of data transmission of the master device is matched with the format of data transmission of the slave device;

【3】 And after the transmission data is stored in an FIFO module of the port entry module, the transmission data is output through the byte sequence functional module, the bit sequence functional module and the bit width functional module.

In the internal data transmission method of the microcontroller with the configurable bus matrix ports, the data transmission mode is 1-to-1 single-point transmission, a port module is arranged between the bus matrix and the main equipment, and data of the main equipment is output after data storage and format conversion through the port module.

In the internal data transmission method of the microcontroller with the configurable bus matrix ports, the data transmission mode is 1-to-1 single-point transmission, a port module is arranged between the bus matrix and the slave equipment, and data of the slave equipment is output after data storage and format conversion through the port module.

In the internal data transmission method of the microcontroller with the configurable bus matrix ports, the data transmission mode is 1 to 1 single-point transmission, port modules are arranged between the bus matrix and the slave equipment and between the bus matrix and the master equipment, and data of the master equipment and data of the slave equipment are output after data storage and format conversion through the corresponding port modules.

In the internal data transmission method of the microcontroller with the configurable bus matrix ports, the data transmission mode is 1 to n multipoint transmission, n port modules are arranged between the bus matrix and n slave devices, and the data of the n slave devices are converted into a format matched with the master device through the corresponding port modules and then output.

Compared with the prior art, the method has the following advantages:

1. according to the method and the device, the port modules are constructed among the bus matrix, the master equipment and the slave equipment and are configured in advance, so that the data formats among different ports are matched, automatic data transmission among functional modules with different bit widths, different byte sequences and different bit sequences is realized, interference of a processor core is reduced, and the communication efficiency among the modules of the MCU is improved.

2. According to the method and the device, the existing MCU structure can be utilized for configuration, the original hardware IP and the logic circuit are still utilized for the master device, the slave device, the bus matrix and the port module, and the hardware design does not need to be carried out again for the CPU core and the existing peripheral IP core, so that the MCU has strong compatibility and expansibility, can be completely adapted to users, does not need to develop software and hardware systems aiming at new MCUs, and saves development cost.

3. The application provides a mode that a master device transmits data to a plurality of slave devices simultaneously in MCU, through setting up byte order functional module, bit sequence functional module, bit wide functional module between the different slave devices for different slave devices can receive the data of master device simultaneously, have overcome current MCU and have not possessed the many defects of transmitting data of a owner simultaneously.

Drawings

FIG. 1 is a schematic diagram of a prior art microcontroller;

FIG. 2 is a schematic diagram of a bus matrix structure in a prior art microcontroller;

FIG. 3 is a schematic diagram of a port module and bus matrix structure according to the present application;

FIG. 4 is a schematic diagram of the port module of the present application;

fig. 5 is a schematic diagram illustrating the principle of the bit sequence functional sub-module according to the present application.

The reference signs are: 1-a master device; 2-a slave device; 3-a bus matrix; 4-port module.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.

The core concept of the application is that: four functional modules which work in series, namely an FIFO module, a byte sequence functional module, a bit sequence functional module and a bit width functional module, are added in front of a port of a bus matrix to realize conversion of the byte sequence, the bit sequence and the bit width of data.

As shown in fig. 3 and fig. 4, the microcontroller with configurable bus matrix ports of the present application includes a plurality of master devices 1, a plurality of slave devices 2, and a bus matrix 3; the main device 1 comprises a CPU core and a DMA module; slave device 2 includes memory or peripherals, e.g. serial UART, SPI, I ² C and the like. The master device 1 realizes access and control to the slave device 2 through the bus matrix 3, and data transmission is realized between the master device 1 and the slave device 2 through the bus matrix 3.

Between the master 1 and the bus matrix 3 and/or between the slave 2 and the bus matrix 3, a port module 4 is arranged. In practical application, the port module 4 may be disposed between the master device 1 and the bus matrix 3, or the port module 4 may be disposed between the slave device 2 and the bus matrix 3, or the port modules 4 may be disposed between the master device 1 and the bus matrix 3, and between the slave device 2 and the bus matrix 3. Only the master device and the slave device of the port module 4 are set, so that the data direct transmission effect of the application is achieved. Fig. 3 shows port modules 4 at both ends of the bus matrix 3.

The port module 4 comprises an FIFO module, a byte sequence functional module, a bit sequence functional module and a bit width functional module, and data entering the port module 4 is output after passing through the FIFO module, the byte sequence functional module, the bit sequence functional module and the bit width functional module; the FIFO module is used for caching data, the byte order function module realizes byte ordering of output data according to parameters of the port configuration module, the bit order function module realizes bit ordering of the output data according to parameters of the port configuration module, and the bit width function module realizes conversion from input bit width to output bit width according to parameters of the port configuration module.

The port configuration module is arranged in the register, and configuration bit data of data byte order, bit width and bit order are stored in the register of the port configuration module. Before starting data transmission, the port module needs to read configuration bit data in the port configuration module by a CPU core program, configure the transmission attribute of the master device 1 or the slave device 2, and set the unit bit width, bit order, and byte order of the data transmitted by the master device 1 and the slave device 2, respectively.

As shown in fig. 4, the FIFO module is used to buffer the input data, and the endian function module implements endian selection of each output data; the bit sequence function module is used for realizing bit sequencing of output data, and the bit width function module is used for realizing conversion from input bit width to output bit width. Data first enters the FIFO module, then enters the last three functional modules which are arranged in series, but the sequence can be changed and optimized.

The FIFO module is configured to buffer a data stream sent by the main module, output data with a bit width of 32 bits (4 bytes), and is set according to an array transmission format of the MCU master 1 currently in mainstream.

The endian function module is shown in table 1, and is used to implement data byte ordering, and select and output an ordering according to 2-bit configuration bit data. Four sorts are selected according to common peripherals, and configuration bit data 00, 01, 10 and 11 of byte order are required to be placed in the port configuration module.

TABLE 1 control schematic of endian function

Configuring bit data	Output endian
		00	BYTE0BYTE1BYTE2BYTE3
01	BYTE3BYTE2BYTE1BYTE0
		10	BYTE0BYTE2BYTE1BYTE3
11	BYTE1BYTE3BYTE0BYTE2

The bit sequence function module is shown in table 2, and is configured to implement bit sequencing of bytes, and select and output a sequence according to 2-bit configuration bit data. Four bit sequences are selected according to common peripherals, and bit sequence configuration bit data 00, 01, 10 and 11 need to be placed in the port configuration module.

TABLE 2 control schematic of bit-sequence functional blocks

Configuring bit data	Output endian
		00	b0b1b2b3b4b5b6b7
01	b7b6b5b4b3b2b1b0
		10	b3b2b1b0b7b6b5b4
11	b1b0b3b2b5b4b7b6

The bit width functional module realizes output of different bit widths, and selects and outputs one bit width according to 2-bit configuration bit data, for example, when the configuration bit is 00, 1byte is output every time, and 32-bit data needs to be output 4 times, and when the configuration bit is 01, 2 bytes are output every time, and 32-bit data needs to be output 2 times. Similarly, bit width configuration bit data 00, 01, 10, 11 needs to be placed in the port configuration module.

TABLE 3 control schematic of bit wide functional block

The method for transmitting the internal data of the MCU comprises the following steps:

【1】 The CPU core program selects a master device 1 and a slave device 2 which need to transmit data;

【2】 Before starting transmission, a CPU core program reads parameter information of a port configuration module and configures transmission attributes of a master device and a slave device, wherein the transmission attributes comprise unit bit width, bit sequence and byte sequence, so that the format of data transmitted by the master device 1 is matched with the format of data transmitted by the slave device 2;

【3】 After the transmission data is stored in the FIFO module of the port entering module 4, the transmission data is output through the byte sequence functional module, the bit sequence functional module and the bit width functional module, so that the transmission of the matched data format between the master device 1 and the slave device 2 is realized.

In data transmission, 1 to 1 unicast transmission may be adopted, and 1 to n multicast transmission may also be adopted.

When 1-to-1 single-point transmission is adopted, three selectable modes are available:

(1) only between the bus matrix 3 and the master 1 is provided a port module 4:

if the master device 1 is a data sending unit and the slave device 2 is a data receiving unit, the data of the master device 1 is subjected to data format conversion by the port module 4 and then reaches the slave device 2 through the bus matrix 3.

If the master device 1 is a data receiving unit and the slave device 2 is a data transmitting unit, the data of the slave device 2 passes through the bus matrix 3, reaches the port module 4, performs data format conversion, and then is transmitted to the master device 1.

(2) Only between the bus matrix 3 and the slave 2 is provided a port module 4:

if the master device 1 is a data sending unit and the slave device 2 is a data receiving unit, the data of the master device 1 passes through the bus matrix 3, then reaches the port module 4, performs data format conversion, and then is sent to the slave device 2.

If the master device 1 is a data receiving unit and the slave device 2 is a data transmitting unit, the data of the slave device 2 is converted into a data format by the port module 4 and then reaches the master device 1 through the bus matrix 3.

(3) Independent port modules 4 are arranged between the bus matrix 3 and the slave 2 and between the bus matrix and the master:

the data of the master device 1 and the data of the slave device 2 are output after being subjected to data storage and format conversion by the corresponding port module 4.

In a similar principle, when 1-to-n multipoint transmission is adopted, n port modules 4 are arranged between the bus matrix 3 and n slave devices 2, and data of the n slave devices 2 is converted into a format matched with the master device 1 through the corresponding port modules 4 and then output.

As shown in fig. 5, the principle of the structure of each functional block will be described by taking a bit-sequential functional submodule as an example.

The former stage of the bit sequence functional module is assumed to be a byte sequence functional module, each byte sequence functional module comprises 32 bits and consists of 4 byte functional submodules side by side in total, and each byte functional submodule outputs 8-bit byte data. Likewise, each bit-sequence functional module comprises 4 bit-sequence functional sub-modules side by side.

Each byte function submodule at the front stage is connected with the bit sequence function submodule at the rear stage in a hard wire mode through a logic circuit, and the parallel outputs of 4 bit sequences are b0b1b2b3b4b5b6b7, b7b6b5b4b3b2b1b0, b3b2b1b0b7b6b5b4 and b1b0b3b2b5b4b7b6 respectively; and then a 2-4 decoder controlled by 2-bit configuration bit data gates one path of bit sequence output, so that the bit sequence functional sub-module realizes the reordering output of 8-bit bytes input at the front stage. And when the design is carried out, according to a common sorting mode, a certain logic circuit hardware channel is gated according to the data of the two-bit configuration bits, and which sort is output is selected.

It should be noted that fig. 5 only shows a construction principle of a certain bit sequence functional sub-module, and the other three bit sequence functional sub-modules, the front-stage and rear-stage byte sequence functional modules and the bit width functional module are all formed by the same principle, and are not described herein again.

Specific examples are given below:

embodiment one, 1 to 1 unicast:

for example, a master module (DMA) sends a set of 32-bit array data to a slave module (serial port), if the original mode is adopted, the CPU is needed, and the process is as follows: the CPU core needs to read the 32-bit array first, convert it into 4 bytes of 8 bits, then transfer it to DMA 4 times, 1byte to the serial port each time, thus every 32 bits need to be converted by the CPU.

And the MCU of the application can realize the function of automatic transmission. It is assumed that corresponding port modules 4 are provided between the master 1 and the bus matrix 3, and between the slave 2 and the bus matrix 3.

The CPU core program firstly reads the parameter information of the port configuration module and configures the parameters of the byte sequence functional module, the bit sequence functional module and the bit width functional module; in the default mode, the byte order configuration bit 00 is not changed, that is, the byte order does not change, the bit order configuration bit 00, that is, the bit order does not change, and the bit width configuration bit needs to be set to 10, that is, 8 bits are output, and one 32-bit data is automatically converted into 4 8-bit data.

The converted data enters a port function module at a serial port through a bus matrix, the slave module is 8-bit peripheral equipment, and a bit width configuration bit is set to be 10, so that the CPU conversion is not needed. The serial port transmission of a group of 32-bit arrays can be completed, and the number of bytes transmitted is 4 times of the original number of bytes.

And if the serial port protocol needs BYTE order recombination, the serial port protocol is not sent according to the default BYTE0-BYTE1-BYTE2-BYTE3 sequence, but is sent according to the default BYTE3-BYTE2-BYTE1-BYTE0 sequence, the configuration bit of the BYTE order function module is set to be 01 by the protocol, and therefore CPU conversion is still not needed. Serial port transmission of a group of 32-bit arrays can be completed, the number of BYTEs transmitted is 4 times of the original number of BYTEs, and the sequence of the BYTEs is BYTE3-BYTE2-BYTE1-BYTE 0.

Further, if the high order bits of the peripheral protocol bytes are transmitted first, i.e., not in the default 8-bit order of b0b1b2b3b4b5b6b7, but in the b7b6b5b4b3b2b1b0 format, the protocol sets the configuration bit of the bit-order function block to 01, which still requires no CPU translation. Serial transfer of a 32-bit array can be completed, the number of bytes transferred is 4 times of the original number of bytes, and the bit order of the bytes is b7b6b5b4b3b2b1b 0.

Embodiment two, 1-to-2 multipoint transmission:

it is assumed that the master needs to send data to two first slaves and two second slaves simultaneously, and that the new MCU has only a separate port module between the slave and the bus matrix. Assume the master is 32 bits of data; the first slave device is 8 bits wide and adopts a byte high bit first transmission mode; the second slave device is 16 bits wide and adopts a byte low bit first transmission mode.

When the method is applied, a byte sequence functional module, a bit sequence functional module and a bit width functional module corresponding to a first slave device and a second slave device can be respectively set, so that the byte sequence configuration bit of the first slave device is 00 in default, the bit sequence is 01, the byte sequence configuration bit is transmitted first according to high bits, the bit width configuration bit is 10, and 8 bits are output; the second slave device sets the configuration bit data of the functional module, the byte order configuration bit is 00 default, the bit order is 00 default, the bit width configuration bit is 01, and 16 bits are output. Therefore, only according to the data format requirements of the two slave devices, the port module between the slave device and the bus matrix is correspondingly set, so that the transmission function that different slave devices can receive the data of the master device at the same time can be realized, and the defect that the existing MCU does not have the simultaneous transmission of data between one master device and multiple slave devices is overcome.

Claims

1. A microcontroller with a configurable bus matrix port comprises a bus matrix (3) and a plurality of master devices (1) and a plurality of slave devices (2) which are connected to a functional port of the bus matrix, wherein the master devices (1) access and control the slave devices (2) through the bus matrix (3), and data transmission is realized between the master devices (1) and the slave devices (2) through the bus matrix (3);

the method is characterized in that: the microcontroller also comprises a port module (4) arranged between the master device (1) and the bus matrix (3) and/or between the slave device (2) and the bus matrix (3), and a port configuration module arranged in the register;

the port module (4) comprises an FIFO module, a byte sequence functional module, a bit sequence functional module and a bit width functional module, and data entering the port module (4) is output after passing through the FIFO module, the byte sequence functional module, the bit sequence functional module and the bit width functional module;

the FIFO module is used for caching data, the byte order function module realizes byte ordering of output data according to parameters of the port configuration module, the bit order function module realizes bit ordering of the output data according to parameters of the port configuration module, and the bit width function module realizes conversion from input bit width to output bit width according to parameters of the port configuration module.

2. The bus matrix port configurable microcontroller of claim 1, wherein: the FIFO module, the byte sequence functional module, the bit sequence functional module and the bit width functional module are connected through a logic circuit to realize the interconnection between the front-stage module and the rear-stage module.

3. The bus matrix port configurable microcontroller of claim 1, wherein: the array transmission bit width of the main device (1) is the same as the number of CPU core bits.

4. The bus matrix port configurable microcontroller of claim 1, wherein: the byte sequence functional module, the bit sequence functional module and the bit width functional module respectively realize gating configuration through corresponding two-bit decoders.

5. The bus matrix port configurable microcontroller of claim 1, wherein: the master device (1) is a CPU or a DMA, and the slave device (2) is a memory or an external device.

6. The internal data transmission method of a bus matrix port configurable microcontroller according to any of claims 1-5, characterized in that it comprises the following steps:

【1】 The CPU core program selects a master device (1) and a slave device (2) which need to transmit data;

【2】 The CPU core program reads the parameter information of the port configuration module and configures the bit width, bit sequence and byte sequence of data for the port module (4) corresponding to the master device (1) or the slave device (2), so that the format of data transmission of the master device (1) is matched with the format of data transmission of the slave device (2);

【3】 And after the transmission data is stored in an FIFO (first in first out) module of the port entering module (4), the transmission data is output through a byte sequence functional module, a bit sequence functional module and a bit width functional module.

7. The method of claim 6, wherein the bus matrix port is configurable to transmit data internally to the microcontroller: the data transmission mode is 1-to-1 single-point transmission, a port module (4) is arranged between the bus matrix (3) and the main device (1), and data of the main device (1) are output after being subjected to data storage and format conversion through the port module (4).

8. The method of claim 6, wherein the bus matrix port is configurable to transmit data internally to the microcontroller: the data transmission mode is 1-to-1 single-point transmission, a port module (4) is arranged between the bus matrix (3) and the slave equipment (2), and data of the slave equipment (2) are output after data storage and format conversion through the port module (4).

9. The method of claim 6, wherein the bus matrix port is configurable to transmit data internally to the microcontroller: the data transmission mode is 1-to-1 single-point transmission, port modules (4) are arranged between the bus matrix (3) and the slave device (2) and between the bus matrix and the master device, and data of the master device (1) and data of the slave device (2) are output after data storage and format conversion through the corresponding port modules (4).

10. The method of claim 6, wherein the bus matrix port is configurable to transmit data internally to the microcontroller: the data transmission mode is 1-to-n multipoint transmission, n port modules (4) are arranged between the bus matrix (3) and n slave devices (2), and data of the n slave devices (2) are converted into a format matched with the master device (1) through the corresponding port modules (4) and then output.