CN114325807A - Digital SiPM array detector - Google Patents
Digital SiPM array detector Download PDFInfo
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- CN114325807A CN114325807A CN202111535806.7A CN202111535806A CN114325807A CN 114325807 A CN114325807 A CN 114325807A CN 202111535806 A CN202111535806 A CN 202111535806A CN 114325807 A CN114325807 A CN 114325807A
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Abstract
The application relates to a digitized SiPM array detector comprising: an SiPM array and a data acquisition board, the SiPM array transmitting an original summation signal to the data acquisition board, wherein the data acquisition board comprises: the amplifying circuit amplifies the original summation signal transmitted by the SiPM array, and the amplified signal comprises a first path of amplified signal; the analog-to-digital converter is used for digitizing the first path of amplified signal; the FPGA is used for processing the data digitized by the analog-to-digital converter; the communication circuit transmits the data processed by the FPGA to external equipment; and the voltage conversion circuit receives the input voltage of the communication circuit and converts the input voltage into the voltage required by the SiPM array and the operational amplifier voltage required by the amplifying circuit. The detector of the present application can be coupled to a variety of different scintillation crystals, and thus radiation detector products for different purposes can be rapidly developed.
Description
Technical Field
The present application relates to the field of radiation detectors, and more particularly to a digitized SiPM array detector.
Background
In the past, a scintillation crystal is usually coupled with a photomultiplier tube (PMT) and then used for developing a radiation detector, but because the PMT is large in size, high in working voltage (1000-. Since silicon photomultiplier (SiPM) has the advantages of small volume, low working voltage, insensitivity to magnetic field, low cost and the like, it is replacing PMT in many application directions, and gradually becomes the first choice photoelectric conversion device of scintillation crystal detector, and large size SiPM array detector also becomes the focus of related researchers in recent years.
Disclosure of Invention
The application aims to provide a digital SiPM array detector to replace a scintillator detector based on a PMT so as to solve the problems of large volume, high working voltage, sensitivity to electromagnetic fields, low application range and the like of the PMT.
The purpose of the application is realized by adopting the following technical scheme:
the application provides a digital SiPM array detector, includes: an SiPM array and a data acquisition board, the SiPM array transmitting an original summation signal to the data acquisition board, wherein the data acquisition board comprises: the amplifying circuit is used for amplifying the original summation signal transmitted by the SiPM array, and the amplified signal comprises a first path of amplified signal; the analog-to-digital converter is used for digitizing the first path of amplified signal; the FPGA is used for processing the data digitized by the analog-to-digital converter; the communication circuit is used for transmitting the data processed by the FPGA to external equipment; and the voltage conversion circuit is used for receiving the input voltage of the communication circuit and converting the input voltage into the voltage required by the SiPM array and the operational amplifier voltage required by the amplifying circuit.
The technical scheme has the beneficial effects that the digital SiPM array detector has the advantages of small volume, low power consumption, strong environmental adaptability, large working temperature range and excellent performance index, and can be widely applied to various nuclear radiation detection and nuclide identification directions.
Preferably, the SiPM array is a square SiPM array comprising M SiPMs.
The technical scheme has the beneficial effect that the square SiPM array adopting M SiPMs is beneficial to large-area expansion.
Preferably, the SiPM array is a circular SiPM array comprising M SiPMs.
The technical scheme has the beneficial effects that the circular SiPM array adopting M SiPMs is beneficial to large-area detection of multi-channel independent output, and position information is convenient to obtain.
Preferably, the front surface of the SiPM array includes M sipms, the back surface of the SiPM array includes M-way summing circuits and a board-to-board connector, and the raw summing signals obtained by the M-way summing circuits are output to the power supply board via the board-to-board connector.
The technical scheme has the beneficial effects that the total energy of the SiPM array is estimated through the M-path summing circuit, and the board-to-board connector conveniently transmits the signal of the SiPM array of the data acquisition power supply board to the data acquisition power supply board.
Preferably, the communication circuit includes a first communication circuit and a second communication circuit, and the voltage conversion circuit is connected to the first communication circuit or the second communication circuit, respectively, and receives an input voltage of the first communication circuit or the second communication circuit.
The technical scheme has the advantages that the first communication circuit and the second communication circuit are arranged, so that various data communication modes can be supported, amplified analog signals can be output, and the method can be used for diagnosing the quality of output signals of the front-end detector or other acquisition equipment.
Preferably, the first communication circuit is a USB communication chip, and the USB communication chip is connected to the external device through a TypeC interface.
The technical scheme has the advantages that the USB communication chip is a novel, efficient, quick, low-price and small-size serial communication interface supporting hot plugging, and can support connection and communication of a plurality of external devices.
Preferably, the second communication circuit is an RS485 communication chip, and the RS485 communication chip is connected to the external device through an RS485 interface.
The technical scheme has the advantages that the RS-485 adopts a half-duplex working mode to support a multi-node, long-distance and troublesome high-sensitivity standard, and the RS-485 bus network topology generally adopts a bus type structure matched with a terminal.
Preferably, the analog-to-digital converter is an 80MSPS ADC.
The technical scheme has the beneficial effect that the 80Msps ADC establishes a new standard for a high-performance ADC with a signal-to-noise ratio (SNR) of 80dB or higher. The device adopts space-saving packaging and works in an industrial temperature range of-40 ℃ to +85 ℃. Therefore, the method is very suitable for a cellular Base Transceiver System (BTS), a multi-carrier and multi-standard communication receiver, an E911 positioning receiver, antenna matrix processing, a high-end detection and measurement instrument and the like.
Preferably, the signals amplified by the amplifying circuit further include a second path of amplified signals, and the second path of amplified signals are output to the outside of the detector in an analog manner through the SMA interface.
The technical scheme has the advantages that the second path of amplified signals can be subjected to analog output, the second path of amplified signals has extremely accurate resolution, the resolution of the analog signals even tends to infinity under the condition of particularly ideal conditions, and the processing method of the analog signals is simpler and more convenient than that of digital signals.
Preferably, the voltage conversion circuit provides a bias voltage for the SiPM array through a DC-DC positive voltage boost module matched to a low dropout linear regulator.
The technical scheme has the beneficial effects that the low-noise SiPM bias voltage is efficiently provided by arranging the DC-DC positive voltage boosting chip to be matched with the low-dropout linear regulator. The method has the advantages of high efficiency, wide input voltage range, small quiescent current, stable output voltage and the like.
In summary, compared with the prior art, the method has the following beneficial effects:
the whole digital SiPM array detector has a compact structure and comprehensive functions, supports multiple data communication modes, can output amplified analog signals, can be used for diagnosing the quality of output signals of a front-end detector or connecting with other acquisition equipment (an oscilloscope or other acquisition modules) for later use, and can be used for quickly developing radiation detector products with different purposes by coupling the digital SiPM array detector with various different scintillation crystals.
Drawings
The present application is further described below with reference to the drawings and examples.
Fig. 1 is a schematic diagram of a digital SiPM array detector provided in the present application.
Fig. 2 is a schematic diagram of an embodiment of a digitized SiPM array (SiPM array is a square SiPM array including M sipms) detector provided in the present application.
Fig. 3 is a schematic diagram of another embodiment of a digitized SiPM array (the SiPM array is a circular SiPM array including M sipms) detector provided in the present application.
Fig. 4 is a schematic diagram of a communication circuit portion of a digitized SiPM array detector provided herein.
Fig. 5 is a schematic diagram of an embodiment of a communication circuit portion of a digitized SiPM array detector provided by the present application.
Fig. 6 is a schematic diagram of another embodiment of a digitized SiPM array detector provided herein.
Detailed Description
The present application is further described with reference to the accompanying drawings and the detailed description, and it should be noted that, in the present application, the embodiments or technical features described below may be arbitrarily combined to form a new embodiment without conflict.
As shown in fig. 1, a schematic diagram of a digitized SiPM array detector provided by the present application is shown, and the digitized SiPM array detector of the present application can be used for developing a large-size gamma ray energy spectrum probe. The digital SiPM array detector comprises a SiPM array 1 and a digital power supply board 2, wherein the SiPM array 1 is in communication connection with the digital power supply board 2, wherein,
the SiPM array 1 may be an SiPM array 10 including M sipms, for example, a square SiPM array 11 (see fig. 2) including M sipms or a circular SiPM array 12 (see fig. 3) including M sipms, the front surface of the SiPM array 11 includes M sipms arranged in a certain shape, the back surface includes an M-way summing circuit 13 and a board-to-board connector 14, the M-way summing circuit 13 sums up the summed signals of the square or circular SiPM arrays of M sipms to obtain a raw summed signal, the board-to-board connector 14 is configured to connect the SiPM array 1 with the power supply board 2, and the raw summed signal obtained by the M-way summing circuit 13 is output to the power supply board 2 via the board-to-board connector 14.
The data acquisition power supply board 2 includes: an amplifying circuit 21, an analog-to-digital converter 22, an FPGA 23, a communication circuit 24, and a voltage conversion circuit 25. The amplifying circuit 21 further amplifies the original summation signal transmitted by the SiPM array 1, and the amplified signal includes a first path of amplified signal and a second path of amplified signal; the first of these amplified signals is output to the analog-to-digital converter 22 for digitization, which digitizes the original exponential waveform of the SiPM output. The result of the digitization is an ADC value for a succession of voltage values at the ADC sampling rate (e.g., 2048 for a 12-bit ADC output with an input range of +/-1V corresponds to a 1V voltage). That is to say, the analog-to-digital converter 22 performs analog-to-digital conversion on the first amplified signal amplified by the amplifying circuit 21; the second path of amplified signal is directly output to the outside of the detector through the SMA interface in an analog manner, that is, the second path of amplified signal is an analog signal and can be used for diagnosing the quality of the output signal of the front-end detector or used after being connected with other acquisition equipment (an oscilloscope or other acquisition modules).
The waveform of the original summation signal is related to the type of the front-end scintillation crystal, and generally is an exponential waveform with different waveform widths (different crystals have corresponding time constants), the amplitude is also related to the scintillation crystal, and the amplitude of the output waveform is higher after the scintillation crystal with high light output is coupled with the SiPM. The signal is typically amplified to within 20mV-1V to match the back-end ADC input range.
The waveforms digitized by the analog-to-digital converter 22 are transmitted to the FPGA 23 for further data processing and compression, and then transmitted to an external device through the communication circuit 24. The voltage conversion circuit 25 receives the input voltage of the communication circuit 24 and converts the input voltage into a voltage required by the SiPM array 1 and an operational amplifier voltage required by the amplifier circuit 21.
The FPGA 23 performs threshold detection on sampling points of the continuously input digitized waveforms, determines that the digitized waveforms are valid signals, generates an initial signal from the waveforms passing the threshold, and performs peak calculation or area (integral) calculation on the portions of the waveforms passing the threshold by using the initial signal in cooperation with an integrator to obtain energy of each waveform. The energy information corresponding to the screened effective signals is transmitted to the external equipment, so that the signal transmission bandwidth is greatly reduced, and the lossless storage of data is facilitated. The transmission energy value can be added with the time (the precision is equal to the sampling precision of the ADC) of each waveform crossing the threshold, and the method can be used for other purposes such as time coincidence or counting rate statistics.
Fig. 4 is a schematic diagram of a communication circuit portion of a digitized SiPM array detector according to the present application. The communication circuit 24 may include a first communication circuit 241 and a second communication circuit 242, both the first communication circuit 241 and the second communication circuit 242 are connected to the FPGA 23, the digitized waveforms are subjected to data processing and compression in the FPGA 23 and then transmitted to an external device through the first communication circuit 241 and the second communication circuit 242, and the voltage conversion circuit 25 may receive input voltages (1 selected from 2) from the first communication circuit 241 end and the second communication circuit 242 end, respectively, and convert the input voltages into a bias voltage required by the front-end SiPM and an operational amplifier voltage required by the amplifier circuit.
The voltage conversion circuit 25 receives a direct current voltage of 5-12V, and provides a bias voltage (with the amplitude of 25V-32V) of the low-noise SiPM array through a DC-DC positive voltage boost chip matching LDO (low dropout regulator). The 3.3V voltage required by the operational amplifier is provided by matching a DC-DC positive voltage step-down chip with the LDO, and the-3.3V voltage required by the operational amplifier is provided by matching a DC-DC negative voltage step-down chip with the LDO.
Fig. 5 is a schematic diagram of an embodiment of a communication circuit portion of a digitized SiPM array detector according to the present application. The first communication circuit 241 is, for example, a USB communication chip, and the second communication circuit 242 is, for example, an RS485 communication chip. The external device is, for example, a computer for portable applications or other control devices for long-distance transmission. In the present application, the USB communication chip outputs the digital signal to the computer of the portable application through the TypeC interface. And the RS485 communication chip outputs the digital signal to other control equipment for remote transmission through an RS485 interface.
Fig. 6 is a schematic diagram of an embodiment of a digitized SiPM array detector provided by the present application. In this embodiment, the analog-to-digital converter 22 selects the 80MSPS ADC, the first communication circuit 241 selects the USB communication chip, and the second communication circuit 242 selects the RS485 communication chip.
The application digital SiPM array detector comprises a SiPM array and a power supply board, wherein the SiPM array can be a square SiPM array containing M SiPMs or a circular SiPM array containing M SiPMs, the front faces of the two arrays contain M SiPMs arranged according to a certain shape, the back faces contain an M-way summing circuit and a board-to-board connector, and the board-to-board connector is used for being connected with the power supply board through the number. The data acquisition power supply board comprises an amplifying circuit, an 80MSPS ADC, an FPGA, a voltage conversion circuit, a USB communication chip and an RS485 communication chip. The amplifying circuit is used for further amplifying the original summation signal transmitted by the front end SiPM array, one path of the amplified signal is output to the 80MSPS ADC for digitalization, and the other path of the amplified signal is directly output to the outside of the detector through the SMA interface. The waveforms after the digitization of the 80MSPS ADC are transmitted to the FPGA for further data processing and compression, and then can be transmitted to external equipment in two modes of a USB communication chip and an RS485 communication chip, wherein the external equipment is a portable application computer or other control equipment for remote transmission. The voltage conversion circuit can respectively receive input voltages (1 in 2) from the USB communication chip end and the RS485 communication chip end and convert the input voltages into bias voltages required by the front-end SiPM and operational amplifier voltages required by the amplifying circuit. The analog signal amplified by the amplifying circuit can be used for diagnosing the output signal quality of the front-end detector or used after being connected with other acquisition equipment (an oscilloscope or other acquisition modules), and the digital SiPM array detector can be coupled with various different scintillation crystals.
Compared with the prior art, the method has the following beneficial effects:
1. the whole digital SiPM array detector is compact in structure and comprehensive in function.
2. The method supports various data communication modes, can output amplified analog signals, and can be used for diagnosing the output signal quality of the front-end detector or being connected with other acquisition equipment (an oscilloscope or other acquisition modules) for use.
3. Can be coupled with various scintillation crystals, so that radiation detector products with different purposes can be rapidly developed.
While the present application is described in terms of various aspects, including exemplary embodiments, the principles of the invention should not be limited to the disclosed embodiments, but are also intended to cover various modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A digitized SiPM array detector, comprising: an SiPM array for transmitting raw summation signals to a digital power generation board, wherein,
the data acquisition power board includes:
the amplifying circuit is used for amplifying the original summation signal transmitted by the SiPM array, and the amplified signal comprises a first path of amplified signal;
the analog-to-digital converter is used for digitizing the first path of amplified signal;
the FPGA is used for processing the data digitized by the analog-to-digital converter;
the communication circuit is used for transmitting the data processed by the FPGA to external equipment; and
and the voltage conversion circuit is used for receiving the input voltage of the communication circuit and converting the input voltage into the voltage required by the SiPM array and the operational amplifier voltage required by the amplifying circuit.
2. The digitized SiPM array detector of claim 1,
the SiPM array is a square SiPM array comprising M SiPMs.
3. The digitized SiPM array detector of claim 1,
the SiPM array is a circular SiPM array comprising M SiPMs.
4. A digitized SiPM array detector as claimed in any one of claims 1 to 3,
the front surface of the SiPM array comprises M SiPMs, the back surface of the SiPM array comprises M paths of summation circuits and a board-to-board connector, and the original summation signals obtained by the M paths of summation circuits are output to the power supply board through the board-to-board connector.
5. The digitized SiPM array detector of claim 1,
the communication circuit comprises a first communication circuit and a second communication circuit, and the voltage conversion circuit is respectively connected with the first communication circuit or the second communication circuit and receives input voltage of the first communication circuit or the second communication circuit.
6. The digitized SiPM array detector of claim 5,
the first communication circuit is a USB communication chip, and the USB communication chip is connected with the external equipment through a TypeC interface.
7. The digitized SiPM array detector of claim 5,
the second communication circuit is an RS485 communication chip, and the RS485 communication chip is connected with the external equipment through an RS485 interface.
8. The digitized SiPM array detector of claim 1,
the analog-to-digital converter is an 80MSPS ADC.
9. The digitized SiPM array detector of claim 1,
the signals amplified by the amplifying circuit also comprise a second path of amplified signals, and the second path of amplified signals are output to the outside of the detector in an analog mode through the SMA interface.
10. The digitized SiPM array detector of claim 1,
the voltage conversion circuit provides a bias voltage for the SiPM array through a DC-DC positive voltage boost chip matched low dropout linear regulator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111535806.7A CN114325807A (en) | 2021-12-15 | 2021-12-15 | Digital SiPM array detector |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111535806.7A CN114325807A (en) | 2021-12-15 | 2021-12-15 | Digital SiPM array detector |
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| CN114325807A true CN114325807A (en) | 2022-04-12 |
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| CN202111535806.7A Pending CN114325807A (en) | 2021-12-15 | 2021-12-15 | Digital SiPM array detector |
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