CN114325335A

CN114325335A - Synchronous testing device and synchronous testing method

Info

Publication number: CN114325335A
Application number: CN202111660781.3A
Authority: CN
Inventors: 林楷辉; 陈宏毅; 倪建兴
Original assignee: Radrock Shenzhen Technology Co Ltd
Current assignee: Radrock Shenzhen Technology Co Ltd
Priority date: 2021-12-30
Filing date: 2021-12-30
Publication date: 2022-04-12

Abstract

The application belongs to the technical field of chip testing and provides a synchronous testing device and a synchronous testing method. A synchronization test apparatus comprising: the device comprises a digital excitation response unit, a signal source unit, a signal analysis unit and a power supply unit; the digital excitation response unit is configured to output a control signal and a first trigger signal to the tested chip and the signal source unit respectively, because the control signal and the first trigger signal are synchronously associated in a time domain, and the control signal is used for indicating the working state of the tested chip, when the signal source unit responds to the first trigger signal, the signal source unit can output a radio frequency input signal to the tested chip and simultaneously output a second trigger signal to the signal analysis unit and the power supply unit, and the power supply unit is triggered to supply power to the tested chip.

Description

Synchronous testing device and synchronous testing method

Technical Field

The invention belongs to the technical field of chip testing, and particularly relates to a synchronous testing device and a synchronous testing method.

Background

At present, when a chip is tested, an automatic test device tests the chip by configuring a corresponding test case and executing the test case. However, the existing automatic test equipment is provided with a plurality of test components with different test functions, and accordingly, when configuring a test case of a chip, the cooperation or synchronization between the test components with different test functions needs to be considered, so that the configuration of the test case is too cumbersome, which is not beneficial to improving the test and production of the chip.

Disclosure of Invention

In view of this, embodiments of the present application provide a synchronous testing apparatus and a synchronous testing method, so as to solve the problem of low testing efficiency in testing a chip in the prior art.

A first aspect of an embodiment of the present application provides a synchronous testing device, including: the device comprises a digital excitation response unit, a signal source unit, a signal analysis unit and a power supply unit;

the digital excitation response unit is configured to output a control signal to the chip to be tested and output a first trigger signal to the signal source unit; the control signal is synchronously associated with the first trigger signal in a time domain, and the control signal is used for indicating the working state of the chip to be tested;

the signal source unit is configured to respond to the first trigger signal to output a radio frequency input signal to the chip under test and output a second trigger signal to the signal analysis unit and the power supply unit, where the radio frequency input signal is used for being input to the chip under test for processing and outputting a radio frequency output signal, and the second trigger signal is used for triggering the signal analysis unit to analyze and process the radio frequency output signal and triggering the power supply unit to supply power to the chip under test.

Further, the synchronous testing device further comprises: the control backplate and set up and be in multiunit test screens unit on the control backplate, every group test screens unit includes at least one test connection screens, test connection screens is used for connecting the digital excitation response unit signal source unit with the electrical unit.

Furthermore, different test connection cards on the same test card unit are connected with each other to trigger synchronization, and different test connection cards on different test card units are configured with a trigger bus to trigger synchronization.

Furthermore, a trigger bus with an initial state of low level is connected with the control back plate and all the test connection clamps, all the test connection clamps use the trigger bus pulled high to high level as a trigger signal, or the trigger bus with the initial state of high level is connected with the control back plate and all the test connection clamps, and all the test connection clamps use the trigger bus pulled low to low level as a trigger signal.

A second aspect of the embodiments of the present application provides a synchronization testing method, applied to a synchronization testing apparatus, including:

the digital excitation response unit outputs a control signal to the chip to be tested and outputs a first trigger signal to the signal source unit; the control signal is synchronously associated with the first trigger signal in a time domain, and the control signal is used for indicating the working state of the chip to be tested;

the signal source unit responds to the first trigger signal to output a radio frequency input signal to the chip to be tested and output a second trigger signal to the signal analysis unit and the power supply unit;

the power supply unit supplies power to the chip to be tested based on the first trigger signal;

the tested chip amplifies the radio frequency input signal and outputs a radio frequency output signal;

the signal analysis unit analyzes and processes the radio frequency output signal based on the second trigger signal.

Further, controlling the back panel to obtain a preset script file, wherein the preset script file comprises a back panel configuration script segment;

the control back plate sends a trigger instruction to the digital excitation response unit according to the back plate configuration script section so as to trigger the digital excitation response unit to output a control signal to the chip to be tested and output a first trigger signal to the signal source unit.

Further, the preset script further comprises a trigger configuration script segment, and the trigger configuration script segment comprises a trigger mode, a first group of transmission ports and a second group of transmission ports;

the digital excitation response unit responds to the trigger instruction, outputs a control signal to the tested chip and outputs a first trigger signal to the signal source unit, and comprises:

and the digital excitation response unit responds to a trigger instruction, outputs the control signal to the chip to be tested through the first group of transmission ports according to the trigger mode, and outputs the first trigger signal to the signal source unit through the second group of transmission ports.

Further, the trigger configuration script segment includes a first flag signal;

the digital excitation response unit responds to a trigger instruction, outputs the control signal to the chip to be tested through the first group of transmission ports according to the trigger mode, and outputs the first trigger signal to the signal source unit through the second group of transmission ports, and the method comprises the following steps:

and the digital excitation response unit responds to a trigger instruction, outputs a control signal to the chip to be tested through the first group of transmission ports based on the first marking signal, and outputs a first trigger signal to the signal source unit through the second group of transmission ports.

Further, the preset script text further comprises a signal source configuration script segment, and the signal source configuration script segment comprises a second marking signal;

the signal source unit responds to the first trigger signal to output a radio frequency input signal to the chip to be tested and output a second trigger signal to the signal analysis unit and the power supply unit, and the method comprises the following steps:

the signal source unit outputs a radio frequency input signal to the chip to be tested and outputs a second trigger signal to the signal analysis unit and the power supply unit when detecting the first trigger signal based on the second marking signal.

Further, the first trigger signal is a first rising edge signal or a first falling edge signal, and the second trigger signal is a second rising edge signal or a second falling edge signal.

The synchronous testing device and the synchronous testing method provided by the embodiment of the application have the following beneficial effects:

the synchronous testing device that this application embodiment provided includes: the device comprises a digital excitation response unit, a signal source unit, a signal analysis unit and a power supply unit; the digital excitation response unit is configured to output a control signal and a first trigger signal to the tested chip and the signal source unit respectively, because the control signal and the first trigger signal are synchronously associated in a time domain, and the control signal is used for indicating a working state of the tested chip, when the signal source unit responds to the first trigger signal, the signal source unit can output a second trigger signal to the signal analysis unit and the power supply unit while outputting a radio frequency input signal to the tested chip, the power supply unit is triggered to supply power to the tested chip, so that the tested chip processes the radio frequency input signal in the working state indicated by the control signal and outputs a radio frequency output signal, the trigger signal analysis unit analyzes and processes the radio frequency output signal output by the tested chip, and under the condition that a test case is not required to be configured, the digital excitation response unit and the signal source unit are realized in a more simplified manner when the tested chip is tested, The signal source unit, the signal analysis unit and the power supply unit work cooperatively and act synchronously, so that the implementation process of testing the tested chip is simplified, and the testing efficiency of the chip is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

Fig. 1 is a schematic structural diagram of a synchronous testing device according to an embodiment of the present disclosure;

FIG. 2 is a schematic structural diagram of a synchronous testing apparatus according to another embodiment of the present application;

fig. 3 is a flowchart of an implementation of a synchronization testing method according to an embodiment of the present application;

fig. 4 is a flowchart illustrating an implementation of a synchronization testing method according to another embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The following describes in detail a synchronization testing apparatus provided in this embodiment by a specific implementation manner.

Fig. 1 shows a schematic structural diagram of a synchronous testing device according to an embodiment of the present application. As shown in fig. 1, the synchronous testing apparatus 100 provided in this embodiment includes: a digital stimulus response unit 10, a signal source unit 20, a signal analysis unit 30 and a power supply unit 40.

The digital excitation response unit 10 is configured to output a control signal to the chip under test 110 and output a first trigger signal to the signal source unit 20; the control signal is synchronously associated with the first trigger signal in the time domain, and the control signal is used for indicating the working state of the tested chip 110. The synchronous correlation between the control signal and the first trigger signal in the time domain refers to that the digital excitation response unit 10 outputs the control signal to the chip under test 110 and outputs the first trigger signal to the signal source unit 20 at the same time point, and the working states of the chip under test 110 in the time domain correspond to the working states of the signal source unit 20 in the time domain one to one, that is, the digital excitation response unit 10, the chip under test 110, and the signal source unit 20 are synchronous in the time domain.

The signal source unit 20 is configured to respond to a first trigger signal to output a radio frequency input signal to the chip under test for processing, and output a second trigger signal to the signal analysis unit 30 and the power supply unit 40, where the radio frequency input signal is used to input the radio frequency input signal to the chip under test for processing, and output a radio frequency output signal, and the second trigger signal is used to trigger the signal analysis unit 30 to analyze and process the radio frequency output signal, and trigger the power supply unit 40 to supply power to the chip under test.

In the present embodiment, when the chip under test 110 is tested by the synchronous testing apparatus 100, the chip under test 110 is electrically connected to the synchronous testing apparatus 100. Here, the chip under test 110 may be a radio frequency signal processing chip, for example, a radio frequency signal amplifying chip, etc. When the chip under test 110 is tested, the digital stimulus response unit 10 sends a control signal to the chip under test 110, and sends a first trigger signal to the signal source unit 20. Here, the control signal is used to indicate the working state of the chip under test 110, that is, the chip under test 110 works according to the working state indicated by the control signal after receiving the control signal, in this embodiment, the control signal indicates the working state of the chip under test 110 includes the control signal indicates the working state of the chip under test 110 in the time domain.

It should be noted that the signal source unit 20 outputs the rf input signal and the second trigger signal to the signal analyzing unit 30 and the power supply unit 40, respectively, in response to the first trigger signal. Here, since the control signal is associated with the first trigger signal in time domain synchronously, the signal source unit 20 also has an association relationship with the first trigger signal in time domain respectively through the rf input signal output in response to the first trigger signal and the second trigger signal. That is, since the control signal is synchronously associated with the first trigger signal in the time domain, the time point of outputting the radio frequency input signal and the time point of outputting the second trigger signal by the signal source unit 20 in response to the first trigger signal are associated with the time domain of the control signal.

In all embodiments of the present application, the digital excitation response unit 10 outputs the time-domain synchronized control signal and the first trigger signal, so that the signal source unit 20 can output the radio frequency input signal and output the second trigger signal according to the trigger timing set by the first trigger signal when responding to the first trigger signal. Because the second trigger signal is used to trigger the power supply unit 40 to supply power to the chip under test, and the second trigger signal is also used to trigger the signal analysis unit 30 to analyze and process the rf output signal, the power supply unit 40 responds to the second trigger signal, and supplies power to the chip under test 110 according to the time domain signal indicated by the second trigger signal, therefore, after the power supply unit 40 supplies power to the chip under test 110, according to the received rf input signal, the rf output signal is output to the signal analysis unit 30 in the working state indicated by the control signal, and after receiving the rf output signal output by the chip under test 110, the signal analysis unit 30 responds to the second trigger signal, analyzing the radio frequency output signal according to the time domain signal indicated by the second trigger signal to obtain an analysis result, namely, the digital stimulus response unit 10, the chip under test 110, the signal source unit 20, the signal analysis unit 30 and the power supply unit 40 are synchronously associated in the time domain.

It is easy to understand that, while the digital stimulus response unit 10 sends the control signal to the chip under test 110 to instruct the chip under test 110 to enter the corresponding working state, by outputting the first trigger signal to the signal source unit 20, the signal source unit 20 is triggered to output the rf input signal to the dut 110, so that the dut 110 processes the rf input signal to output the rf output signal, and outputs a second trigger signal to the signal analysis unit 30 and the power supply unit 40, the second trigger signal triggers the source unit 40 to supply power to the chip under test 110, and the trigger signal analysis unit 30 performs data analysis on the rf output signal, so that during the process of testing the chip under test 110, the signal source unit 20, the signal analysis unit 30 and the power supply unit 40 are synchronized with the operating state of the chip under test 110 under the control of the digital excitation response unit 10.

In particular, the digital stimulus response unit 10 may be implemented by using an existing digital stimulus response device, such as an MDSR board. As an example, when testing the chip 110 under test, the MDSR board outputs a control signal to the chip 110 under test through a corresponding configuration port, such as a Mobile Industry Processor Interface (MIPI).

Illustratively, the chip under test 110 is a radio frequency signal amplification chip, and the radio frequency signal amplification chip is configured to amplify a radio frequency input signal and output the amplified radio frequency input signal as a radio frequency output signal. The radio frequency signal amplifying chip works in a time division duplex mode, and the work in the time division duplex mode is not continuous in time sequence but periodic in a section. That is, the radio frequency signal amplification chip works in a time period and outputs certain power; the rf signal amplifier chip does not operate in a time period and has no power output, so that the rf signal amplifier chip operates periodically in the tdd mode, and therefore it is necessary that the operating modes of all functional components in the synchronous testing apparatus 100 can be adapted to the operating mode of the rf signal amplifier chip. Here, since the radio frequency signal amplification chip operates periodically in the time division duplex mode, when the radio frequency signal amplification chip is tested in the time division duplex mode, the MDSR board card is required to indicate that the operating timing of other functional units is synchronous with the operating timing of the radio frequency signal amplification chip, so as to implement the operating mode adaptation with the radio frequency signal amplification chip.

In connection with the above example, the digital stimulus response unit 10 (e.g., MDSR board) outputs the first trigger signal to the signal source unit 20 through the GPIO port, or the digital stimulus response unit 10 (e.g., MDSR board) outputs the first trigger signal to the signal source unit 20 through the trigger line of the modular instrument platform. Here, the modular fast instrument platform may be a PCI extension for Instrumentation (PXI) backplane configured based on Peripheral Component Interconnect (PCI) standards, that is, the digital stimulus response unit 10 outputs the first trigger signal to the signal source unit 20 through a trigger line of the PXI backplane. The signal source unit 20 may be an existing rf transceiver, and outputs an rf input signal to the rf signal amplifying chip by responding to the first trigger signal of the M digital excitation response unit 10 (e.g., MDSR board), and also outputs a second trigger signal to the signal analysis unit 30 and the power supply unit 40.

In an embodiment, the first trigger signal and the second trigger signal are preferably pulse signals, and the signal source unit 20 outputs the rf input signal and the second trigger signal when detecting that the first trigger signal jumps from a low level to a high level, i.e. when detecting a rising edge of the first trigger signal. The power supply unit 40 can be an ac/dc power supply or a dc voltage-regulating power supply, when detecting that the second trigger signal jumps from the low level to the high level, that is, after detecting the rising edge of the second trigger signal, the power supply unit 40 supplies power to the radio frequency signal amplification chip, the radio frequency signal amplification chip can amplify the radio frequency input signal and output a radio frequency output signal, and simultaneously, the signal analysis unit 30 can receive the radio frequency output signal when detecting that the second trigger signal jumps from the low level to the high level, that is, after detecting the rising edge of the second trigger signal, and then analyze and process the radio frequency output signal and output an analysis result.

Fig. 2 shows a schematic structural diagram of a synchronous testing device according to another embodiment of the present application. As shown in fig. 2, as an embodiment, the synchronization test apparatus 100 further includes: the test card unit comprises a control backboard 50 and a plurality of groups of test card units 51 arranged on the control backboard 50, wherein each group of test card units 51 comprises at least one test connection card 511, and the test connection card 511 is used for connecting the digital excitation response unit 10, the signal source unit 20 and the power supply unit 40.

In the embodiment, since the control backplane 50 is provided with a plurality of sets of test card locations 51, and each set of test card locations 51 includes at least one test connection card 511, the digital stimulus response unit 10, the signal source unit 20, and the power supply unit 40 can be disposed on the control backplane 50 by using the test connection card 511. Here, since each set of test card units 51 includes at least one test connection card 511, a sufficient number of test connection cards 511 can be provided on a set of test card units 51, and the digital stimulus response unit 10, the signal source unit 20, and the power supply unit 40 can be provided on the same set of test card units 51. Alternatively, at least one test connection card 511 may be provided on one group of test card units 51, and the digital stimulus response unit 10, the signal source unit 20, and the power supply unit 40 may be provided on different groups of test card units 51, respectively.

It can be understood that, if the digital excitation response unit 10, the signal source unit 20, and the power supply unit 40 are disposed on the same group of test card-clamping units 51, the multiple test connection cards on the same group of test card-clamping units 51 can be connected by internal routing, that is, synchronous triggering can be directly realized between the functional units connected to different test connection cards in the same group of test card-clamping units 51, and synchronous transmission of the trigger signal can be realized by configuring a port transmission mode among the digital excitation response unit 10, the signal source unit 20, and the power supply unit 40.

As shown in FIG. 2, as an embodiment, different test connection pads 511 on the same test card unit 51 are connected to each other to trigger synchronization, and different test connection pads 511 on different test card units 51 are connected to each other through a configuration trigger bus 52 to trigger synchronization.

In the present embodiment, if the digital stimulus response unit 10 and the signal source unit 20 are disposed on two test connection pads 511 of the same set of test connection pads 51, the two test connection pads 511 are connected by an internal cable, so that the digital stimulus response unit 10 can output the first trigger signal to the signal source unit 20 through the internal cable between the two test connection pads 511, thereby realizing the trigger synchronization of the first trigger signal. Alternatively, if the digital stimulus response unit 10 and the signal source unit 20 are respectively disposed on two test connection pads 511 of two sets of test connection pads 51, the digital stimulus response unit 10 can output the first trigger signal to the signal source unit 20 through the trigger bus 52 between the two test connection pads 511, thereby realizing the trigger synchronization of the first trigger signal. Similarly, if the signal source unit 20 and the power source unit 40 are disposed on two test connection pads 511 of the same set of test connection pads 51, the two test connection pads 511 are connected by an internal cable, so that the signal source unit 20 can output a second trigger signal to the power source unit 40 through the internal cable between the two test connection pads 511, thereby implementing trigger synchronization of the second trigger signal. Alternatively, if the signal source unit 20 and the power source unit 40 are respectively disposed on two test connection pads 511 of two sets of test connection pads 51, the signal source unit 20 can output the second trigger signal to the power source unit 40 through the trigger bus 52 between the two test connection pads 511, thereby realizing the trigger synchronization of the second trigger signal.

In a practical application process, since the signal source unit 20 outputs the second trigger signal to the signal analysis unit 30 and the power supply unit 40 simultaneously by responding to the first trigger signal, when the signal source unit 20 is connected to the signal analysis unit 30, the signal analysis unit 30 may also be disposed on the test connection card 511, or the signal source unit 20 is connected to the signal analysis unit 30 by an external trigger bus. Similarly, if the signal source unit 20 and the signal analysis unit 30 are disposed on two test connection pads 511 of the same set of test connection pads 51, the two test connection pads 511 are connected by an internal bus, so that the signal source unit 20 can output a second trigger signal to the signal analysis unit 30 through the internal bus between the two test connection pads 511, thereby implementing trigger synchronization of the second trigger signal. Alternatively, if the signal source unit 20 and the signal analysis unit 30 are respectively disposed on two test connection pads 511 of two sets of test connection pads 51, the signal source unit 20 can output the second trigger signal to the signal analysis unit 30 through the trigger bus 52 between the two test connection pads 511, thereby implementing trigger synchronization of the second trigger signal.

In some embodiments, the signal source unit 20 and the signal analysis unit 30 may be integrated on the same instrument device. For example, a spectrometer VXT with a signal source is provided with a radio frequency signal generating unit (RF Generator) and a radio frequency signal analyzing unit (RF Analyzer), the radio frequency signal generating unit outputs a radio frequency input signal to the chip 110 under test in response to a first trigger signal, and outputs a second trigger signal to the radio frequency signal analyzing unit, the radio frequency signal analyzing unit analyzes and processes the radio frequency output signal output by the chip 110 under test, and the radio frequency signal generating unit also outputs the second trigger signal to the power supply unit 40, and the trigger power supply unit 40 supplies power to the chip 110 under test.

In all embodiments of the present application, the second trigger signal is used to trigger the signal analysis unit 30 to analyze the rf output signal, so as to obtain a corresponding analysis result. Here, the analysis result may include: at least one of gain data, output power data, signal-to-noise ratio, efficiency, and standing wave ratio.

It can be understood that the signal analysis unit may analyze and process the radio frequency output signal according to a preset parameter configuration, so as to determine each performance index of the chip under test 110, and how to analyze the signal analysis unit to obtain the analysis result is not described herein again.

As an embodiment, the trigger bus 52 with the high level in the initial state is connected to the control backplane 50 and all the test connection cards 511, and all the test connection cards 511 use the trigger bus 52 pulled down to the low level as the trigger signal.

In this embodiment, the trigger bus 52 is used to connect the control backplane 50 and all test connection cards 511. That is, signals can be transmitted between the control backplane 50 and all the test connection cards 511 via the trigger bus 52.

In a specific embodiment, the trigger bus with the initial state of high level is connected to the control backplane and all the test connection cards, that is, the initial state of the signal transmitted on the trigger bus 52 is high level, that is, when the trigger bus 52 sends the trigger signal to the test connection card 511, the electrical pulse signal corresponding to the trigger signal changes from high level to low level, the unit component connected to the test connection card 511 receives the trigger signal, and when the electrical pulse signal changes from low level to high level, the sending of the trigger signal is completed, that is, the trigger bus 52 returns to the initial state.

In another embodiment, the trigger bus with the initial state of low level is used to connect the control backplane and all the test connection cards, that is, the initial state of the signal transmitted on the trigger bus 52 is low level, that is, when the trigger signal is sent to the test connection card 511 through the trigger bus 52, the electrical pulse signal corresponding to the trigger signal changes from low level to high level, the unit component connected to the test connection card 511 receives the trigger signal, and when the electrical pulse signal changes from high level to low level, the sending of the trigger signal is completed, that is, the trigger bus 52 returns to the initial state.

In a specific implementation, the control backplane 50 and all the test connection cards 511 are connected by the trigger bus 52, and all the test connection cards 511 use the signal transmitted on the trigger bus 52 as a trigger signal, which is pulled high or pulled low. That is, the trigger signal transmitted through the trigger bus 52 between the functional units on the test connection card 511 is preferably a pulse signal, and if the initial state of the signal transmitted through the trigger bus 52 is low for all the functional units on the test connection card 511, that is, if the pulse signal is not transmitted through the trigger bus 52, the initial state of the signal transmitted through the trigger bus 52 is low, when the pulse signal is detected by the test connection card 511 or the units on the test connection card 511 to be converted from low to high, the corresponding action and function are started. For example: when detecting that the first trigger signal is converted from low level to high level, the signal source unit starts to output a radio frequency input signal to the chip to be tested, and outputs a second trigger signal to the signal analysis unit and the power supply unit. And the power supply unit starts to supply power to the chip to be tested when the second trigger signal is converted from the low level to the high level. Similarly, if the signal transmitted through the trigger bus 52 is a pulse signal provided between the units on the test connection card 511, and if the initial state of the signal transmitted through the trigger bus 52 is high level for all the units on the test connection card 511, that is, if the pulse signal is not transmitted through the trigger bus 52, the initial state of the signal transmitted through the trigger bus 52 is high level, when the low level of the pulse signal is detected by the unit on the test connection card 511 or the test connection card 511, the corresponding action and function are started. For example: when detecting that the first trigger signal is converted from high level to low level, the signal source unit starts to output a radio frequency input signal to the chip to be tested, and outputs a second trigger signal to the signal analysis unit and the power supply unit. And the power supply unit starts to supply power to the chip to be tested when the second trigger signal is converted from high level to low level.

As an example, the trigger bus 52 with the low level in the initial state is connected to the control backplane 50 and all the test connection cards 511, and all the test connection cards 511 have the trigger bus 52 pulled high as the trigger signal.

Illustratively, as shown in fig. 2, the digital excitation response unit 10 and the signal source unit 20 are connected to the same set of test card units 51, assuming that the initial state of the signal transmitted between different test connection cards on the same test card unit is low level, when the signal source unit 20 detects that the pulse signal corresponding to the first trigger signal is converted from low level to high level, the signal source unit outputs a radio frequency input signal to the chip under test 110 in response to the first trigger signal, and also outputs a second trigger signal to the signal analysis unit 30 and the power supply unit 40.

In connection with the above example, in fig. 2, the signal source unit 20 and the power source unit 40 are respectively connected to two test connection pads 511 of different test pad units, and between the signal source unit 20 and the power source unit 40, the second trigger signal transmitted through the trigger bus 52 between the two test connection pads 511 is a pulse signal, and if the initial state of the signal transmitted on the trigger bus 52 is a low level, that is, when the pulse signal is not sent through the trigger bus 52, the signal transmitted on the trigger bus 52 is a low level. When the signal source unit 20 detects that the pulse signal corresponding to the first trigger signal is converted from the low level to the high level, the second trigger signal is output to the power supply unit 40, and when the power supply unit 40 detects that the pulse signal is converted from the low level to the high level, power is supplied to the chip 110 under test.

In the above scheme, the digital excitation response unit is configured to output a control signal to the chip to be tested, and output a first trigger signal to the signal source unit, because the control signal is synchronously associated with the first trigger signal in the time domain, and the control signal is used to indicate the working state of the chip to be tested, when the signal source unit responds to the first trigger signal, the signal source unit can output a second trigger signal to the signal analysis unit and the power supply unit while outputting a radio frequency input signal to the chip to be tested, and further trigger the power supply unit to supply power to the chip to be tested, so that the chip to be tested processes the radio frequency input signal in the working state indicated by the control signal and outputs a radio frequency output signal, and simultaneously the trigger signal analysis unit analyzes and processes the radio frequency output signal output by the chip to be tested, and when the chip to be tested is tested without configuring a test case, the digital excitation response unit, the signal source unit, the signal analysis unit and the power supply unit are in cooperative work and synchronous action in a more simplified mode, the implementation process of testing the tested chip is simplified, and the testing efficiency of the chip is improved.

The embodiment of the application also provides an implementation flow chart of the chip testing method, which is detailed as follows:

s11: the digital excitation response unit outputs a control signal to the chip to be tested and outputs a first trigger signal to the signal source unit; the control signal is synchronously associated with the first trigger signal in a time domain, and the control signal is used for indicating the working state of the tested chip.

In step S11, the digital stimulus response unit outputs a control signal to the chip under test according to a trigger instruction, where the trigger instruction is an instruction for instructing the digital stimulus response unit to output the control signal to the chip under test and simultaneously output a first trigger signal to the signal source unit. In this embodiment, the trigger instruction is sent to the digital excitation response unit by the control backplane to trigger the digital excitation response unit to execute a corresponding function. The digital excitation response unit outputs control signals to the tested chip through two different paths by responding to the trigger instruction, and outputs a first trigger signal to the signal source unit.

In this embodiment, the digital stimulus response unit is pre-configured with a signal transmission strategy, where the signal transmission strategy includes a transmission path through which the digital stimulus response unit outputs the control signal to the chip under test and outputs the first trigger signal to the signal source unit.

In a specific implementation, the trigger instruction may be generated by the digital excitation response unit after detecting that the chip under test is connected to the synchronous test device, or may be generated periodically, or may be generated by the control backplane connected to the digital excitation response unit by executing a preset test script file.

It can be understood that, because the control signal is synchronously associated with the first trigger signal in the time domain, a rising edge/a falling edge during high-low level conversion between the pulse signal corresponding to the control signal and the pulse signal corresponding to the first trigger signal corresponds, that is, a high-low level conversion time point between the pulse signal corresponding to the control signal and the pulse signal corresponding to the first trigger signal is synchronous, so that a working state of the chip to be tested in the time domain is synchronous with a working state of the signal source unit in the time domain.

In this embodiment, the specific selection and implementation of the working state of the chip under test and the digital stimulus response unit are described in detail in the embodiment corresponding to fig. 1, and refer to the relevant portions in the embodiments of fig. 1 and 1, which are not described herein again.

S12: the signal source unit responds to the first trigger signal to output a radio frequency input signal to the chip to be tested and output a second trigger signal to the signal analysis unit and the power supply unit.

In step S12, the rf input signal is used as a signal to be input to the chip under test for processing, and the chip under test outputs an rf output signal after processing the signal according to the operating state indicated by the control signal. The second trigger signal is used for triggering the signal analysis unit to analyze the radio frequency output signal output by the tested chip and is also used for triggering the power supply unit to supply power to the tested chip.

In this embodiment, since the control signal is synchronously associated with the first trigger signal in the time domain, the signal source unit also has an association relationship with the first trigger signal respectively through the rf input signal and the second trigger signal output in response to the first trigger signal. That is, since the control signal is synchronously associated with the first trigger signal in the time domain, the signal source unit responds to the first trigger signal, and the time point of outputting the radio frequency input signal and the time point of outputting the second trigger signal are synchronously associated with the time point of the control signal in the time domain. Here, the signal source unit responds to the first trigger signal, and then outputs a radio frequency input signal to the chip to be tested, and simultaneously outputs a second trigger signal to the signal analysis unit and the power supply unit, so that when the chip to be tested is tested, the signal source unit can provide the radio frequency input signal to the chip to be tested, and the power supply unit can provide a working power supply synchronous with the working state of the chip to be tested, and further, the working state of the signal analysis unit when analyzing and processing the radio frequency output signal output by the chip to be tested is synchronous with the working state of the chip to be tested in the time domain.

S13: the power supply unit supplies power to the chip to be tested based on the second trigger signal.

In step S13, since the first trigger signal is synchronously associated with the control signal in the time domain, and the control signal is used to indicate the operating state of the chip under test, the signal source unit responds to the first trigger signal to output the second trigger signal to the power supply unit, and the power supply unit supplies power to the chip under test based on the second trigger signal, which is equivalent to that the operating state of the chip under test supplied power by the power supply unit is synchronous with the operating state of the chip under test in the time domain.

In this embodiment, the working state of the chip under test is used to characterize the working time or the non-working time of the chip under test, that is, the control signal indicates when the chip under test works and when the chip under test does not work. Here, the switching between different working states of the chip under test may be set according to different working modes or different working strategies of the chip under test.

Taking the tested chip as the radio frequency signal amplification chip as an example, the radio frequency signal amplification chip is used for amplifying the radio frequency input signal, and outputting the amplified radio frequency input signal as a radio frequency output signal.

As an example, the rf signal amplifying chip operates in a tdd mode, since the operation of the tdd mode is not continuous in time sequence, but periodic in a segment. That is, the radio frequency signal amplification chip works in a time period and outputs certain power; the rf signal amplifier chip does not operate in a time period and has no power output, so that the rf signal amplifier chip operates periodically in the tdd mode, and therefore it is necessary that the operating modes of all functional components in the synchronous testing apparatus 100 can be adapted to the operating mode of the rf signal amplifier chip. Here, since the radio frequency signal amplification chip operates periodically in the time division duplex mode, when the radio frequency signal amplification chip is tested in the time division duplex mode, the MDSR board card is required to indicate that the operating timing of other functional units is synchronous with the operating timing of the radio frequency signal amplification chip, so as to implement the operating mode adaptation with the radio frequency signal amplification chip.

In this embodiment, specific selection and implementation of the related unit units are described in detail in the embodiment corresponding to fig. 1, and refer to fig. 1 and relevant portions in the embodiment of fig. 1 for details, which are not described herein again.

As one example, step S13 includes: and the power supply unit supplies power to the chip to be tested according to the second trigger signal.

In this embodiment, the second trigger signal is synchronously associated with the control signal in a time domain, and the control signal is used to indicate the operating state of the chip to be tested, so that the duration of the high level or the duration of the low level of the first trigger signal can be used to determine the operating time of the chip to be tested, and can also be used to indicate the operating time of the power supply unit supplying power to the chip to be tested. For example, the second trigger signal may be a rising edge signal converted from a low level to a high level, and when the power supply unit receives the rising edge signal converted from the low level to the high level, the power supply unit may supply power to the chip to be tested according to a working period of the chip to be tested, and then a working state of the power supply unit supplying power to the chip to be tested is synchronized with a working state of the chip to be tested in a time domain. For example, when the power supply unit detects that the first trigger signal is converted from a low level to a high level, power is supplied to the chip to be tested.

S14: the tested chip amplifies the radio frequency input signal and outputs a radio frequency output signal.

In step S14, the amplifying process is to amplify the rf input signal by the chip under test according to the configuration command carried by the control signal, and then output the rf output signal. That is, the rf output signal is a signal output by the chip under test after the rf input signal is amplified, and various performance indexes of the chip under test can be determined by analyzing the rf output signal, for example: gain, linearity, maximum output power, etc.

In this embodiment, when the chip to be tested receives the control signal, the signal source unit outputs the radio frequency input signal to the chip to be tested according to the first trigger signal, and simultaneously, the signal source unit also outputs the second trigger signal to the power supply unit, so as to trigger the power supply unit to supply power to the chip to be tested. It can be understood that the working state of the chip under test for processing the received rf input signal is synchronously associated with the working state of the power supply unit for supplying power to the chip under test in the time domain.

It is understood that, in other embodiments, the chip under test may also perform other processing on the rf input signal, such as filtering, frequency conversion, etc., and accordingly, the output rf output signal may also be a filtered rf input signal or a frequency-converted rf input signal, which is not limited herein.

S15: the signal analysis unit analyzes and processes the radio frequency output signal based on the second trigger signal.

In step S15, the second trigger signal may trigger the signal analysis unit to analyze the rf signal, and the operation state of the chip under test processing the received rf input signal is synchronously related in time domain.

In this embodiment, when the power supply unit supplies power to the chip to be tested, the chip to be tested amplifies the rf input signal in the operating state indicated by the control signal, and outputs the rf output signal to the signal analysis unit.

It is easily understood that in all embodiments of the present application, whether the first trigger signal or the second trigger signal is a pulse signal with high-low level switching.

As an example, the rising edge of the pulse signal may be used as a response timing, that is, when the signal source unit detects the rising edge of the first trigger signal, the signal source unit starts to perform an action of outputting the radio frequency input signal to the chip under test, and outputting the second trigger signal to the signal analysis unit and the power supply unit. Correspondingly, the signal analysis unit starts to execute the action of analyzing and processing the radio frequency output signal when detecting the rising edge of the second trigger signal. And when detecting the rising edge of the second trigger signal, the power supply unit starts to execute the action of supplying power to the chip to be tested. As another example, a falling edge of the pulse signal may be used as a response timing, that is, when the signal source unit detects a falling edge of the first trigger signal, the signal source unit starts to perform an action of outputting the radio frequency input signal to the chip under test, and outputting the second trigger signal to the signal analysis unit and the power supply unit. Correspondingly, the signal analysis unit starts to execute the action of analyzing and processing the radio frequency output signal when detecting the falling edge of the second trigger signal. And when the power supply unit detects the falling edge of the second trigger signal, the power supply unit starts to execute the action of supplying power to the chip to be tested.

In this embodiment, the signal analysis unit analyzes and processes the rf output signal based on the second trigger signal to obtain a corresponding analysis result. Here, the analysis result may include: at least one of gain data, output power data, signal-to-noise ratio, efficiency, and standing wave ratio.

It can be understood that, since the rf input signal is a known signal and the operating state of the chip to be tested is also a known parameter, the signal analysis unit can perform band analysis on the rf output signal to obtain a corresponding analysis result. Since the existing band analysis technology can be preferably used for analyzing and processing the radio frequency output signal, how to analyze the signal analysis unit to obtain the analysis result is not described herein again.

Fig. 4 shows a flowchart of an implementation of a synchronization testing method according to another embodiment of the present application. As shown in fig. 4, the difference from fig. 3 is that the present embodiment further includes steps S21 to S22 before step S11. Specifically, the method comprises the following steps:

s21: and controlling the back plate to obtain a preset script file, wherein the preset script file comprises a back plate configuration script section.

S22: and the control back plate sends a trigger instruction to the digital excitation response unit according to the back plate configuration script segment.

In this embodiment, the trigger command is sent from the control backplane to the digital stimulus response unit. Here, since the control backplane is configured with the preset script file, and the preset script file includes the backplane configuration script segment, the control backplane can execute the preset script file, and further send a trigger instruction to the digital excitation response unit to trigger the digital excitation response unit to output a control signal to the chip to be tested, and output a first trigger signal to the signal source unit.

It should be noted that the backplane configuration script segment is used to describe a manner for controlling the backplane to send the trigger instruction to the digital stimulus response unit. The specific port for controlling the backboard to generate the trigger instruction, the transmission port of the trigger instruction and the transmission path of the trigger instruction are defined in the backboard configuration script.

A schematic diagram of the synchronization test apparatus 100 shown in connection with fig. 2. Illustratively, a plurality of sets of test card-positioning units 51 are disposed on the control backplane 50, and at least one test connection card 511 is disposed on each set of test card-positioning units 51. In addition, all the test connection cards 511 can trigger synchronization through the configuration trigger bus 52, and based on this, a specific port for controlling the backplane to generate the trigger instruction, a transmission port for the trigger instruction, and a transmission path for the trigger instruction are defined in the backplane configuration script segment, so that the control backplane can accurately transmit the trigger instruction to the digital excitation response unit.

In the present embodiment corresponding to fig. 4, when steps S21 to S22 are completed, steps S11 to S15 are started. As a possible implementation manner of this embodiment, the preset script further includes a trigger configuration script segment, where the trigger configuration script segment includes a trigger manner, a first group of transmission ports, and a second group of transmission ports. Accordingly, step S11 includes:

and the digital excitation response unit responds to a trigger instruction, executes the trigger configuration script segment, outputs the control signal to the chip to be tested through the first group of transmission ports according to the trigger mode, and outputs the first trigger signal to the signal source unit through the second group of transmission ports.

In this embodiment, the triggering manner is specifically a triggering manner in which the digital excitation response unit outputs a control signal to the chip to be tested and outputs the first trigger signal to the signal source unit by responding to the trigger instruction when receiving the trigger instruction.

In specific implementation, the digital excitation response unit may be configured to output the control signal and the first trigger signal time point in the trigger configuration script segment, and configure the working state of the signal source unit in the time domain, so that the working state of the signal source unit in the working state domain in the time domain is synchronously associated with the working state of the chip to be tested in the time domain. And when the digital excitation response unit responds to the trigger instruction and executes the trigger configuration script segment, outputting a corresponding first pulse signal as a control signal to the chip to be tested through the first group of transmission ports, and outputting a corresponding second pulse signal as the first trigger signal to the signal source unit through the second group of transmission ports.

For one embodiment, the trigger configuration script segment includes a first flag signal. And the trigger configuration script segment takes the first marking signal as the trigger time point of the digital excitation response unit to output the control signal to the chip to be tested and output the first trigger signal to the signal source unit. And the digital excitation response unit outputs a control signal to the tested chip and outputs a first trigger signal to the signal source unit based on the first marking signal when executing the trigger configuration script section. Correspondingly, in the steps: outputting the control signal to the chip under test through the first group of transmission ports and outputting the first trigger signal to the signal source unit through the second group of transmission ports according to the trigger mode, including:

and the digital excitation response unit responds to a trigger instruction, and based on the first marking signal, the control signal is output to the chip to be tested through the first group of transmission ports, and the first trigger signal is output to the signal source unit through the second group of transmission ports.

In this embodiment, the triggering mode is that a rising edge signal when the trigger signal is switched from a low level to a high level is used as a triggering time point, or a falling edge signal when the trigger signal is switched from a high level to a low level is used as a triggering time point, when the digital excitation response unit responds to the trigger instruction and executes the trigger configuration script segment, the control signal is switched from a low level to a high level based on the first flag signal and is output to the chip under test through the first group of transmission ports, and similarly, the first trigger signal is switched from a low level to a high level based on the first flag signal and is output to the signal source unit through the second group of transmission ports.

It is easy to understand that, in specific implementation, different forms of pulse signal pairs can be selected as the control signal and the first trigger signal according to actual requirements, and only the pulse signal pairs are required to be ensured to be in correlation synchronization in the time domain and to be in correlation synchronization in the time domain with the working state of the chip to be tested.

As a possible implementation manner of this embodiment, the preset script further includes a signal source configuration script segment, and the signal source configuration script segment includes the second markup signal. And the signal source configuration script section comprises a response strategy of the signal source unit responding to the first trigger signal. In this embodiment, the response policy of the signal source unit responding to the first trigger signal is that the signal source unit executes the trigger configuration script segment, outputs a control signal to the chip under test based on the second flag signal, and outputs the first trigger signal to the signal source unit. The signal source configuration script section takes the second marking signal as an output control signal to the tested chip and outputs a first trigger signal to a trigger time point of the signal source unit. Accordingly, step S12 includes:

the signal source unit outputs a radio frequency input signal to the chip to be tested and outputs a second trigger signal to the signal analysis unit and the power supply unit when detecting a rising edge or a falling edge of the first trigger signal based on the second marking signal.

In this embodiment, the signal source configuration script segment is used to describe a response policy of the signal source unit in response to the first trigger signal, where the response policy indicates a response action performed by the signal source unit when receiving the first trigger signal.

When the signal source unit detects the rising edge or the falling edge of the first trigger signal, the radio frequency input signal can be output to the chip to be tested, and the second trigger signal can be output to the signal analysis unit and the power supply unit.

In this embodiment, the first trigger signal is a first rising edge signal or a first falling edge signal, and the second trigger signal is a second rising edge signal or a second falling edge signal.

It is easily understood that the "first rising edge signal" and the "first falling edge signal" appearing in the embodiment of the present application are examples of the first trigger signal, and the "second rising edge signal" and the "second falling edge signal" are examples of the second trigger signal, and are only used for distinguishing different types of signals output by different units.

In the embodiment corresponding to fig. 4, when step S12 is completed, steps S13 to S15 are started. For specific implementation of steps S13-S15, reference may be made to the embodiment corresponding to fig. 3, which is not described herein again.

As an embodiment, the synchronous testing method further includes the steps of:

and the power supply unit is used for measuring and outputting the electrical attribute data of the tested chip based on the analysis result of the radio frequency output signal and the power supply data of the tested chip after stopping supplying power to the tested chip and waiting for a preset time.

In the present embodiment, the preset time period is used to describe the waiting time of the power supply unit. The electrical property data includes: at least one of the working current value of the tested chip, the power value of the tested chip and the loss electric quantity value of the tested chip. The power supply data is electrical data when the power supply unit supplies power to the chip to be tested, such as a power supply voltage value, a power supply current value, power supply duration and the like.

It should be noted that the power supply unit supplies power to the chip to be tested by responding to the second trigger signal, wherein the second trigger signal triggers the power supply unit to be able to provide a working power supply synchronized with the working state of the chip to be tested, and after the power supply unit stops supplying power to the chip to be tested, the power supply unit performs electrical attribute data analysis based on the analysis result of the radio frequency output signal and the power supply data after waiting for a preset time period to obtain an electrical attribute analysis result.

It is easy to understand that, since the power supply data is the electrical data when the power supply unit supplies power to the chip under test, the analysis result of the rf output signal may include: at least one of gain data, output power data, signal-to-noise ratio, efficiency, and standing wave ratio.

In the scheme, the digital excitation response unit responds to the trigger instruction to output a control signal to the chip to be tested and output a first trigger signal to the signal source unit, because the control signal is synchronously associated with the first trigger signal in a time domain and is used for indicating the working state of the chip to be tested, when the signal source unit responds to the first trigger signal, the signal source unit can output a second trigger signal to the signal analysis unit and the power supply unit while outputting a radio frequency input signal to the chip to be tested, and further triggers the power supply unit to supply power to the chip to be tested, so that the chip to be tested can process the radio frequency input signal and output a radio frequency output signal in the working state indicated by the control signal, and meanwhile, the trigger signal analysis unit analyzes and processes the radio frequency output signal output by the chip to be tested, and when the chip to be tested is tested under the condition of not configuring a test case, the digital excitation response unit, the signal source unit, the signal analysis unit and the power supply unit are in cooperative work and synchronous action in a more simplified mode, the implementation process of testing the tested chip is simplified, and the testing efficiency of the chip is improved.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims

1. A synchronization test apparatus, comprising: the device comprises a digital excitation response unit, a signal source unit, a signal analysis unit and a power supply unit;

2. The synchronization test apparatus of claim 1, further comprising: the control backplate and set up and be in multiunit test screens unit on the control backplate, every group test screens unit includes at least one test connection screens, test connection screens is used for connecting the digital excitation response unit signal source unit with the electrical unit.

3. The synchronous testing device as claimed in claim 2, wherein different test connection cards on the same test card unit are connected to each other to trigger synchronization, and different test connection cards on different test card units are connected to each other to trigger synchronization by configuring the trigger bus.

4. The synchronous testing device as claimed in claim 3, wherein the control backplane and all the test connection cards are connected by a trigger bus whose initial state is low, and all the test connection cards use the trigger bus pulled high as a trigger signal, or the control backplane and all the test connection cards are connected by a trigger bus whose initial state is high and all the test connection cards use the trigger bus pulled low as a trigger signal.

5. A synchronous testing method is characterized by being applied to a synchronous testing device and comprising the following steps:

the power supply unit supplies power to the chip to be tested based on the second trigger signal;

6. The synchronous testing method of claim 5, wherein the digital stimulus response unit outputs the control signal to the chip under test and outputs the trigger signal to the signal source unit, further comprising;

controlling a back plate to obtain a preset script file, wherein the preset script file comprises a back plate configuration script section;

7. The synchronous testing method according to claim 6, wherein the preset script further comprises a trigger configuration script segment, and the trigger configuration script segment comprises a trigger mode, a first set of transmission ports and a second set of transmission ports;

8. The synchronous test method of claim 7, wherein the trigger configuration script segment comprises a first flag signal;

9. The synchronous test method according to claim 8, wherein the preset script further comprises a signal source configuration script segment, the signal source configuration script segment comprising a second flag signal;

10. The synchronous test method according to claim 9, wherein the first trigger signal is a first rising edge signal or a first falling edge signal, and the second trigger signal is a second rising edge signal or a second falling edge signal.