CN114325199A - Supercapacitor internal resistance detection method and device and storage medium - Google Patents
Supercapacitor internal resistance detection method and device and storage medium Download PDFInfo
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Abstract
The invention discloses a method and a device for detecting the internal resistance of a super capacitor and a storage medium, wherein the method comprises the following steps: during the shutdown period of the super capacitor, charging and discharging are carried out by constant current, and the voltage value during charging and the corresponding charging time as well as the voltage value during discharging and the corresponding discharging time are periodically collected; acquiring a preset initial value of an equivalent internal resistance estimation value; performing a cyclic operation for each charging voltage value: calculating a first capacitance estimation value during charging and a second capacitance estimation value during discharging, and a difference value between the first capacitance estimation value and the second capacitance estimation value, wherein the voltage value during charging is equal to the voltage value during discharging; judging whether the difference value meets a preset condition or not; and if the equivalent internal resistance value does not meet the preset condition, the equivalent internal resistance estimated value is determined as the equivalent internal resistance value. The technical scheme provided by the invention can solve the technical problem that the internal resistance of the super capacitor can be detected only by high-precision mathematical modeling in the field of the energy storage system in the prior art.
Description
Technical Field
The invention relates to the technical field of supercapacitor detection, in particular to a supercapacitor internal resistance detection method and device and a storage medium.
Background
The super capacitor is a novel electric energy storage device, has the advantages of high power density, high charging and discharging efficiency, long cycle life, wide use temperature range, environmental protection and the like, and is widely applied to occasions such as electric vehicles, voltage compensation, braking energy recovery, new energy power generation and the like. The internal resistance is an important parameter of the super capacitor, and can effectively reflect the charge state, the health state and the operation temperature information of the super capacitor. The online accurate detection of the internal resistance parameters can provide support for the performance test, the optimized control and the efficient operation and maintenance of the super-capacitor energy storage system, and has important significance for the safe, reliable and efficient operation of the system.
In the prior art, two methods are mainly used for detecting the internal resistance parameter of the super capacitor, one method is an off-line testing method based on special equipment, the detection method can be used only when the capacitor is in an off-line state, the detection method is difficult to implement on the site of an energy storage system, a set of special equipment is needed, the detection cost is high, and the operation is inconvenient. The other method is an online capacitance parameter identification method based on a mathematical model, which has high requirement on the capacitance-voltage stability of the super capacitor, and if the data precision for mathematical modeling is not enough, the detection result of the internal resistance of the super capacitor is influenced. With the continuous aging of the super capacitor in the using process, the robustness and the practicability of the mathematical model can be reduced due to the change of the internal physical and chemical parameters of the super capacitor, and the internal resistance measurement deviation is caused.
Disclosure of Invention
The invention provides a method and a device for detecting the internal resistance of a super capacitor and a storage medium, and aims to effectively solve the technical problem that the internal resistance of the super capacitor can be detected only by high-precision mathematical modeling in the field of an energy storage system in the prior art.
According to an aspect of the present invention, the present invention provides a supercapacitor internal resistance detection method, including:
during the shutdown period of the super capacitor, charging and discharging the super capacitor at a preset constant current, periodically collecting the voltage value of the super capacitor in a charging state and the charging time corresponding to the voltage value according to a preset time interval in a preset interval of the charging and discharging process to obtain a voltage value-charging time sequence, and periodically collecting the voltage value of the super capacitor in a discharging state and the discharging time corresponding to the voltage value according to the preset time interval to obtain a voltage value-discharging time sequence;
acquiring a preset initial value of an equivalent internal resistance estimation value;
sequentially performing, for each charging voltage value in the voltage value-charging time sequence, the following cyclic operation: calculating a first capacitance estimation value according to the equivalent internal resistance estimation value, the charging voltage value and the charging time corresponding to the charging voltage value, and the preset constant current value, calculating a second capacitance estimation value according to the discharging voltage value in the voltage value-discharging time sequence, which is equal to the charging voltage value, the discharging time corresponding to the charging voltage value, the equivalent internal resistance estimation value, and the preset constant current value, calculating a difference value between the first capacitance estimation value and the second capacitance estimation value, and then judging whether the difference value meets a preset condition;
and if the difference value does not meet the preset condition, updating the equivalent internal resistance estimated value based on a preset increment value, executing the cyclic operation according to the charging voltage value in the voltage value-charging time sequence, and if the difference value meets the preset condition, determining the current equivalent internal resistance estimated value as the equivalent internal resistance value of the supercapacitor.
Further, the calculating a first capacitance estimation value according to the equivalent internal resistance estimation value, the charging voltage value and the corresponding charging time thereof, and the preset value of the constant current for each charging voltage value in the voltage value-charging time sequence includes:
calculating a charging capacitor voltage estimated value according to the charging voltage value, the preset constant current value and the equivalent internal resistance estimated value;
and calculating the first capacitance estimated value according to the charging capacitance voltage estimated value, the preset constant current value, the charging time corresponding to the charging voltage value and the initial capacitance value of the super capacitor in the shutdown period.
Further, the calculating a charging capacitor voltage estimation value according to the charging voltage value, the preset constant current value and the equivalent internal resistance estimation value includes:
calculating the estimated value of the charge capacitor voltage according to the following formula:
UC_est_1＝Usc_1-Isc_1Req_est
wherein, Usc_1Representing said charging voltage value, Req_estRepresenting the estimated value of equivalent internal resistance, Isc_1Representing the value of said preset constant current during charging, UC_est_1Representing the charge capacitor voltage estimate.
Further, the calculating the first capacitance estimation value according to the charging voltage value, the charging capacitance voltage estimation value, the preset constant current value, the charging time corresponding to the charging voltage value, and the initial capacitance value of the super capacitor during the shutdown period includes:
calculating the first capacitance estimate as follows:
wherein, UC_est_1Representing the estimated value of the charge capacitor voltage, t1Represents the charging time corresponding to the charging voltage value, Isc_1Representing the value of said preset constant current during charging, Ceq_est_1Represents an initial capacitance value of the supercapacitor during the shutdown.
Further, the calculating, for each charging voltage value in the voltage value-charging time sequence, a second capacitance estimation value according to a discharging voltage value in the voltage value-discharging time sequence that is equal to the charging voltage value and a corresponding discharging time thereof, the equivalent internal resistance estimation value, and the preset value of the constant current includes:
calculating a discharge capacitance voltage estimated value according to the discharge voltage value, the preset constant current value and the equivalent internal resistance estimated value;
and calculating the second capacitance estimated value according to the discharge capacitance voltage estimated value, the preset constant current value, the discharge time corresponding to the discharge voltage value and the initial capacitance value of the super capacitor in the shutdown period.
Further, the calculating a discharge capacitance voltage estimation value according to the charge voltage value, the discharge voltage value, the preset constant current value and the equivalent internal resistance estimation value includes:
calculating the discharge capacitance voltage estimate according to:
UC_est_2＝Usc_2-Isc_2Req_est
wherein, Usc_2Represents the discharge voltage value, Req_estRepresenting the estimated value of equivalent internal resistance, Isc_2Representing the value of said preset constant current during discharge, UC_est_2Representing the discharge capacitance voltage estimate.
Further, the calculating the second capacitance estimation value according to the discharge capacitance voltage estimation value, the preset constant current value, the discharge time corresponding to the discharge voltage value, and the initial capacitance value of the super capacitor during the shutdown period includes:
calculating the second capacitance estimate as follows:
wherein, UC_est_2Representing the discharge capacitance voltage estimate, t2Indicating the discharge time corresponding to the discharge voltage value, Isc_2Representing the value of said preset constant current during discharge, Ceq_est_2Represents an initial capacitance value of the supercapacitor during the shutdown.
Further, the preset interval of the charging and discharging process refers to a charging interval of the voltage value of the super capacitor between 30% of the maximum voltage and a discharging interval of the voltage value of the super capacitor between 30% of the maximum voltage and the maximum voltage.
Further, the preset time interval is 1 μ s, and the preset initial value of the estimated equivalent internal resistance value is 0m Ω or 0.01m Ω.
Further, the preset condition is that the ratio of the difference to the average value of the first capacitance estimation value and the second capacitance estimation value is less than 1%.
Further, the preset increment value is 0.01m Ω.
Further, the updating the equivalent internal resistance estimation value based on a preset increment value includes:
and adding the current equivalent internal resistance estimated value and the preset incremental value to serve as a new equivalent internal resistance estimated value.
According to another aspect of the present invention, the present invention provides a method for detecting the internal resistance of a super capacitor, comprising:
the data acquisition and preprocessing module is used for charging and discharging the super capacitor at preset constant current during the shutdown period of the super capacitor, periodically acquiring the voltage value of the super capacitor in a charging state and the charging time corresponding to the voltage value according to preset time intervals in a preset interval of the charging and discharging process to obtain a voltage value-charging time sequence, periodically acquiring the voltage value of the super capacitor in a discharging state and the discharging time corresponding to the voltage value according to the preset time intervals to obtain a voltage value-discharging time sequence, and acquiring a preset initial value of the equivalent internal resistance estimation value;
a calculating module, configured to sequentially perform the following cyclic operations for each charging voltage value in the voltage value-charging time sequence: calculating a first capacitance estimation value according to the equivalent internal resistance estimation value, the charging voltage value and the charging time corresponding to the charging voltage value, and the preset constant current value, calculating a second capacitance estimation value according to the discharging voltage value in the voltage value-discharging time sequence, which is equal to the charging voltage value, and the discharging time corresponding to the charging voltage value, the equivalent internal resistance estimation value, and the preset constant current value, and calculating a difference value between the first capacitance estimation value and the second capacitance estimation value;
and the judging module is used for judging whether the difference value meets a preset condition, updating the equivalent internal resistance estimated value based on a preset increment value if the difference value does not meet the preset condition, triggering the calculating module to execute the circulating operation aiming at the charging voltage value in the voltage value-charging time sequence, and determining the current equivalent internal resistance estimated value as the equivalent internal resistance value of the super capacitor if the difference value meets the preset condition.
According to another aspect of the present invention, there is provided a storage medium having stored therein a plurality of instructions adapted to be loaded by a processor to execute any one of the supercapacitor internal resistance detection devices described above.
Through one or more of the above embodiments in the present invention, at least the following technical effects can be achieved:
the invention provides an on-line detection method of super capacitor internal resistance parameters based on charge-discharge hysteresis characteristics from the perspective of physical characteristics, which fully utilizes the shutdown clearance of a super capacitor and the existing hardware conditions to control the super capacitor through an energy storage converter to carry out symmetrical charge-discharge tests, obtains the capacitor internal resistance parameters and the characteristics thereof on site, does not set limit conditions on the implementation scene of super capacitor resistance detection, and is convenient to implement.
The resistance detection is carried out by charging and discharging the super capacitor with constant current, and the voltage value and the current value of the super capacitor are acquired in real time in the charging and discharging process. After charging and discharging are finished, calculating a charging capacitance value and a discharging capacitance value under the same voltage according to the collected data and the equivalent internal resistance estimated value, and continuously iteratively adjusting the equivalent internal resistance estimated value to enable the capacitance difference between the charging capacitance value and the discharging capacitance value to reach a preset condition, so as to obtain the actual resistance value of the super capacitor.
Compared with the prior art, on one hand, the method for detecting the internal resistance of the super capacitor based on the hysteresis characteristic makes full use of the test data obtained in the charging and discharging process, can effectively eliminate the measurement error of the super capacitor caused by the influence of the nonlinear characteristic, and improves the detection precision. On the other hand, the method can fully utilize the existing software and hardware conditions of the super-capacitor energy storage system to carry out regular or irregular detection under the condition of system shutdown, has no requirement on an internal resistance detection scene, and is convenient to implement. The technical scheme provided by the invention is used as a quasi-online testing technology, has the advantages of safety, simplicity, convenience, accuracy and the like, and can solve the technical problem that the internal resistance of the super capacitor can be detected only by high-precision mathematical modeling in the field of an energy storage system in the prior art.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
Fig. 1 is a flowchart illustrating steps of a method for detecting an internal resistance of a super capacitor according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of capacitance-voltage hysteresis characteristics generated in a charging and discharging process of a super capacitor according to an embodiment of the present disclosure;
FIG. 3 is a schematic circuit diagram of an ultracapacitor energy storage system provided by an embodiment of the present application;
fig. 4 is a schematic structural diagram of a supercapacitor internal resistance detection device according to a third embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that, unless explicitly stated or limited otherwise, the term "and/or" herein is only one kind of association relationship describing the associated object, and means that there may be three kinds of relationships, for example, a and/or B, and may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" in this document generally indicates that the preceding and following related objects are in an "or" relationship unless otherwise specified.
Example one
Fig. 1 is a flowchart illustrating steps of a method for detecting an internal resistance of a super capacitor according to an embodiment of the present invention. The supercapacitor internal resistance detection method comprises the following steps:
step 101: during the shutdown period of the super capacitor, charging and discharging the super capacitor at a preset constant current, periodically collecting the voltage value of the super capacitor in a charging state and the charging time corresponding to the voltage value according to a preset time interval in a preset interval of the charging and discharging process to obtain a voltage value-charging time sequence, and periodically collecting the voltage value of the super capacitor in a discharging state and the discharging time corresponding to the voltage value according to the preset time interval to obtain a voltage value-discharging time sequence;
step 102: acquiring a preset initial value of an equivalent internal resistance estimation value;
step 103: sequentially performing, for each charging voltage value in the voltage value-charging time sequence, the following cyclic operation: calculating a first capacitance estimation value according to the equivalent internal resistance estimation value, the charging voltage value and the charging time corresponding to the charging voltage value, and the preset constant current value, calculating a second capacitance estimation value according to the discharging voltage value in the voltage value-discharging time sequence, which is equal to the charging voltage value, the discharging time corresponding to the charging voltage value, the equivalent internal resistance estimation value, and the preset constant current value, calculating a difference value between the first capacitance estimation value and the second capacitance estimation value, and then judging whether the difference value meets a preset condition;
step 104: and if the difference value does not meet the preset condition, updating the equivalent internal resistance estimated value based on a preset increment value, executing the cyclic operation according to the charging voltage value in the voltage value-charging time sequence, and if the difference value meets the preset condition, determining the current equivalent internal resistance estimated value as the equivalent internal resistance value of the supercapacitor.
The invention relates to a super capacitor parameter online detection method based on charge-discharge hysteresis characteristics, which charges and discharges a super capacitor with constant current when the super capacitor is in a non-working state, wherein in the charge-discharge process, the terminal voltage of the super capacitor changes along with time, the voltage continuously increases during charge, the actual capacitance value of the capacitor increases along with the increase of the voltage, and the discharge process is vice versa. Fig. 2 is a schematic diagram showing capacitance-voltage hysteresis characteristics of a supercapacitor during charging and discharging, in which the abscissa in a coordinate system is a terminal voltage of the supercapacitor, and the ordinate is an actual capacitance value of the capacitor. In the charging process, the capacitance is increased along with the increase of the terminal voltage of the super capacitor; in the discharging process, the capacitance is reduced along with the reduction of the terminal voltage of the super capacitor, and the polarity of the equivalent resistance voltage drop of the super capacitor is changed along with the polarity of the current in an alternating way, namely, the voltage drop in the charging process is positive and the voltage drop in the discharging process is negative, so that the capacitance-voltage hysteresis characteristic shown in fig. 2 is generated, and a hysteresis comparison cycle is formed. The invention fully utilizes the shutdown clearance of the super capacitor and the existing hardware conditions to control the super capacitor to carry out symmetrical charging and discharging through the energy storage converter and collect relevant detection data, and obtains the internal resistance parameters of the super capacitor on site.
In step 101, during the shutdown period of the super capacitor, the super capacitor is charged and discharged with a preset constant current, and in a preset interval of the charging and discharging process, the voltage value of the super capacitor in the charging state and the charging time corresponding to the voltage value are periodically collected according to a preset time interval to obtain a voltage value-charging time sequence, and the voltage value of the super capacitor in the discharging state and the discharging time corresponding to the voltage value are periodically collected according to a preset time interval to obtain a voltage value-discharging time sequence. Illustratively, the supercapacitor is charged and discharged with a preset constant current when the supercapacitor is in an inactive state, i.e., during a shutdown. In the charging and discharging process, when the capacitance value and the voltage of the super capacitor are close to a linear relation, namely within a preset period, the voltage value is periodically collected according to a preset time interval. Specifically, in the charging process, the collected data includes a voltage value of the supercapacitor in a charging state and a charging time corresponding to the voltage value, and the voltage value-charging time sequence can be obtained through the charging time. In the discharging process, the voltage value of the super capacitor in the discharging state and the discharging time corresponding to the voltage value are periodically collected according to the same preset time interval, wherein the voltage value-discharging time sequence can be obtained through the discharging time.
After the step 101 is executed, the step 102 is executed to obtain a preset initial value of the equivalent internal resistance estimation value. Illustratively, fig. 3 is a schematic circuit diagram of an ultracapacitor energy storage system, wherein the equivalent internal resistance estimate is an estimated value of the internal resistance of the ultracapacitor. In the process of compensating the supercapacitor internal resistance parameter by an iterative mode with the aim of eliminating hysteresis deviation to obtain the supercapacitor internal resistance parameter meeting a certain precision requirement, a preset initial value of an equivalent internal resistance estimated value in an initial state needs to be set before calculation is started. In the process of detecting the internal resistance of the super capacitor, after data acquired by charging and discharging are acquired, a preset initial value of the equivalent internal resistance estimation value needs to be acquired before internal resistance parameters are calculated.
After step 102 is executed, step 103 is executed, and the following loop operation is executed for each charging voltage value in the voltage value-charging time sequence in sequence: and calculating a first capacitance estimation value according to the equivalent internal resistance estimation value, the charging voltage value, the charging time corresponding to the charging voltage value and a preset constant current value, calculating a second capacitance estimation value according to the discharging voltage value which is equal to the charging voltage value in the voltage value-discharging time sequence, the discharging time corresponding to the discharging voltage value, the equivalent internal resistance estimation value and the preset constant current value, calculating a difference value between the first capacitance estimation value and the second capacitance estimation value, and then judging whether the difference value meets a preset condition. For example, for the voltage values collected during the charging process, according to the voltage and time data collected during the charging process, a cyclic operation is performed for each charging voltage value in the voltage value-charging time sequence in the collection time sequence, that is, the cyclic operation is performed for each voltage value collected during the charging process. Specifically, for a selected voltage value in the charging process, a first capacitance estimation value corresponding to the charging voltage value is calculated, and a second capacitance estimation value corresponding to the same voltage in the discharging process, that is, two capacitance estimation values corresponding to the charging voltage and the discharging voltage value being equal, are calculated.
After the step 103 is executed, step 104 is executed, if the difference value does not satisfy the preset condition, the equivalent internal resistance estimated value is updated based on the preset increment value, the cyclic operation is executed for the charging voltage value in the voltage value-charging time sequence, and if the difference value satisfies the preset condition, the current equivalent internal resistance estimated value is determined as the equivalent internal resistance value of the supercapacitor. Illustratively, the internal resistance of the super capacitor can be calculated by utilizing the hysteresis characteristic of the terminal voltage of the capacitor in the constant current charging and discharging process according to the reversibility of constant current charging and discharging. And if the equivalent internal resistance estimated value is equal to the actual internal resistance value of the super capacitor, the values of the first capacitance estimated value and the second capacitance estimated value are equal. According to the invention, the difference value between the first capacitance estimated value and the second capacitance estimated value is eliminated by iterating the equivalent internal resistance estimated value layer by layer, if the difference value does not meet the preset condition, the equivalent internal resistance estimated value is updated based on the preset increment value, and in order to improve the internal resistance detection precision, the cyclic operation is executed according to the charging voltage value in the voltage value-charging time sequence. When the difference value is small enough and meets the preset condition in each cycle operation, determining that the equivalent internal resistance estimated value is close to the actual internal resistance value of the super capacitor, wherein the equivalent internal resistance estimated value at the moment is the internal resistance parameter value of the super capacitor. Of course, in practical applications, according to different requirements for measurement accuracy, when the ratio of the number of charging voltage values meeting the preset condition in the voltage value-charging time sequence is greater than a certain percentage, the equivalent internal resistance estimated value is determined to be the actual internal resistance value of the supercapacitor.
The invention provides an on-line detection method of super capacitor internal resistance parameters based on charge-discharge hysteresis characteristics from the perspective of physical characteristics, which fully utilizes the shutdown clearance of a super capacitor and the existing hardware conditions to control the super capacitor through an energy storage converter to carry out symmetrical charge-discharge tests, obtains the capacitor internal resistance parameters and the characteristics thereof on site, does not set limit conditions on the implementation scene of super capacitor resistance detection, and is convenient to implement.
The resistance detection is carried out by charging and discharging the super capacitor with constant current, and the voltage value and the current value of the super capacitor are acquired in real time in the charging and discharging process. After charging and discharging are finished, calculating a charging capacitance value and a discharging capacitance value under the same voltage according to the collected data and the equivalent internal resistance estimated value, and continuously iteratively adjusting the equivalent internal resistance estimated value to enable the capacitance difference between the charging capacitance value and the discharging capacitance value to reach a preset condition, so as to obtain the actual resistance value of the super capacitor.
Compared with the prior art, on one hand, the method for detecting the internal resistance of the super capacitor based on the hysteresis characteristic makes full use of the test data obtained in the charging and discharging process, can effectively eliminate the measurement error of the super capacitor caused by the influence of the nonlinear characteristic, and improves the detection precision. On the other hand, the method can fully utilize the existing software and hardware conditions of the super-capacitor energy storage system to carry out regular or irregular detection under the condition of system shutdown, has no requirement on an internal resistance detection scene, and is convenient to implement. The technical scheme provided by the invention is used as a quasi-online testing technology, has the advantages of safety, simplicity, convenience, accuracy and the like, and can solve the technical problem that the internal resistance of the super capacitor can be detected only by high-precision mathematical modeling in the field of an energy storage system in the prior art.
Example two
Based on the same inventive concept as the supercapacitor internal resistance detection method in the first embodiment of the invention, the supercapacitor internal resistance detection method in the second embodiment of the invention comprises the following steps:
further, calculating a charging capacitor voltage estimated value according to the charging voltage value, a preset constant current value and an equivalent internal resistance estimated value; and calculating a first capacitance estimated value according to the charging capacitance voltage estimated value, a preset constant current value, the charging time corresponding to the charging voltage value and the initial capacitance value of the super capacitor during the shutdown period. Illustratively, FIG. 3 is a schematic circuit diagram of an ultracapacitor energy storage system, wherein the data periodically collected according to time intervals is ultracapacitor terminal voltage UscAnd super capacitor current IscAnd the internal resistance R of the super capacitoreqThe estimated value of the equivalent internal resistance is preset. According to the relation of capacitance current and voltage in the circuit, a charging capacitance voltage estimated value is calculated according to a charging voltage value, a preset constant current value and an equivalent internal resistance estimated value, and then a first capacitance estimated value is calculated according to the charging capacitance voltage estimated value, the preset constant current value, charging time corresponding to the charging voltage value and an initial capacitance value of the super capacitor during shutdown.
Further, referring to the circuit relationship of the super capacitor energy storage system shown in fig. 3, the estimated value of the charge capacitor voltage is calculated according to the following formula:
UC_est_1＝Usc_1-Isc_1Req_est
wherein, Usc_1Representing the value of the charging voltage, Req_estRepresenting an estimated value of equivalent internal resistance, Isc_1Representing the value of a preset constant current, U, during chargingC_est_1Representing the charge capacitor voltage estimate.
Further, the first capacitance estimate is calculated according to the following equation:
wherein, UC_est_1Representing the estimated value of the charge capacitor voltage, t1Represents the charging time corresponding to the charging voltage value, Isc_1Representing the value of a constant current preset during charging, Ceq_est_1Representing the initial capacitance value of the supercapacitor during shutdown.
Further, calculating a discharge capacitance voltage estimated value according to the discharge voltage value, a preset constant current value and an equivalent internal resistance estimated value; and calculating a second capacitance estimation value according to the discharge capacitance voltage estimation value, a preset constant current value, the discharge time corresponding to the discharge voltage value and the initial capacitance value of the super capacitor during the shutdown period, wherein the principle of calculating the second capacitance estimation value is the same as that of calculating the first capacitance estimation value.
Further, the discharge capacitance voltage estimation value is calculated according to the following formula:
UC_est_2＝Usc_2-Isc_2Req_est
wherein, Usc_2Represents the discharge voltage value, Req_estRepresenting an estimated value of equivalent internal resistance, Isc_2Representing a value of a preset constant current, U, during dischargeC_est_2Representing the discharge capacitance voltage estimate.
Further, the second capacitance estimate is calculated according to:
wherein, UC_est_2Representing the discharge capacitance voltage estimate, t2Indicating the discharge time corresponding to the discharge voltage value, Isc_2Representing a value of a constant current preset during discharge, Ceq_est_2Representing the initial capacitance value of the supercapacitor during shutdown.
Further, the preset interval of the charging and discharging process refers to a charging interval of the voltage value of the super capacitor between 30% of the maximum voltage and a discharging interval of the voltage value of the super capacitor between 30% of the maximum voltage and the maximum voltage. For example, in the charging process and the discharging process of the super capacitor, the process that the capacitance increases with the voltage is nonlinear, as shown in fig. 2, when the voltage value is less than 30% of the maximum voltage, the increase rate of the capacitance value changes greatly with the increase of the voltage value, so the current-voltage data collected when the voltage value is less than 30% of the maximum voltage is not suitable for calculating the internal resistance value of the super capacitor. In the interval where the voltage value is greater than 30% of the maximum voltage, the increase rate of the capacitance value is relatively stable as the voltage value increases, and this interval is defined as a steady-state interval, i.e., a preset interval. In order to improve the accuracy of the internal resistance detection, data for internal resistance detection needs to be acquired within the preset interval.
Further, the preset time interval is 1 μ s, and the preset initial value of the estimated equivalent internal resistance value is 0m Ω or 0.01m Ω. Illustratively, the predetermined time interval is a time interval between every two consecutive samples when the current-voltage data is acquired. The smaller the preset time interval is, the more the acquired data is, the higher the internal resistance detection precision is, in order to meet the requirement of measurement precision and improve the detection speed, the preset time interval is set to be 1 mus, and in practical application, an operator can adjust the preset time interval according to specific conditions. The preset initial value of the equivalent internal resistance estimation value is 0m omega or 0.01m omega, when the initial state of the equivalent internal resistance estimation value is not started to be calculated, the equivalent internal resistance estimation value which is brought into an iterative calculation program firstly needs to be determined, the equivalent internal resistance estimation value in the initial state is determined to be 0m omega or 0.01m omega according to the conventional value range of the resistance value of the super capacitor, and similarly, in practical application, an operator can determine the preset initial value of the equivalent internal resistance estimation value according to specific data of the resistance value of the super capacitor, and the invention is not limited.
Further, the preset condition is that the ratio of the difference value to the average value of the first capacitance estimation value and the second capacitance estimation value is less than 1%. Illustratively, in the process of continuously iterating the equivalent internal resistance estimation value, the calculated difference value between the first capacitance estimation value and the second capacitance estimation value becomes smaller and smaller, and a determination condition needs to be formulated to determine that the error between the equivalent internal resistance estimation value and the actual resistance value of the supercapacitor is within an acceptable range. Specifically, when the ratio of the difference to the average value of the first capacitance estimation value and the second capacitance estimation value is less than 1%, it is determined that the difference satisfies the preset condition.
Further, the preset increment value is 0.01m Ω. In practical applications, in order to improve the detection accuracy, 0.01m Ω may be changed to a smaller value.
And further, adding the current equivalent internal resistance estimated value to a preset incremental value to serve as a new equivalent internal resistance estimated value. Illustratively, in the iterative calculation process, if the calculated difference value of the capacitances does not meet the preset condition, the equivalent internal resistance estimated value is updated, and the current equivalent internal resistance estimated value is added with a preset incremental value to serve as a new equivalent internal resistance estimated value.
EXAMPLE III
Based on the same inventive concept as the method for detecting the internal resistance of the super capacitor in the first embodiment of the present invention, an embodiment of the present invention provides a device, please refer to fig. 4, where the device includes:
the data acquisition and preprocessing module 201 is configured to, during a shutdown period of the super capacitor, charge and discharge the super capacitor at a preset constant current, and periodically acquire, according to a preset time interval, a voltage value of the super capacitor in a charging state and a charging time corresponding to the voltage value in a preset interval of a charging and discharging process to obtain a voltage value-charging time sequence, and periodically acquire, according to the preset time interval, the voltage value of the super capacitor in a discharging state and a discharging time corresponding to the voltage value to obtain a voltage value-discharging time sequence, and acquire a preset initial value of an equivalent internal resistance estimation value;
a calculating module 202, configured to sequentially perform the following cyclic operations for each charging voltage value in the voltage value-charging time sequence: calculating a first capacitance estimation value according to the equivalent internal resistance estimation value, the charging voltage value and the charging time corresponding to the charging voltage value, and the preset constant current value, calculating a second capacitance estimation value according to the discharging voltage value in the voltage value-discharging time sequence, which is equal to the charging voltage value, and the discharging time corresponding to the charging voltage value, the equivalent internal resistance estimation value, and the preset constant current value, and calculating a difference value between the first capacitance estimation value and the second capacitance estimation value;
a judging module 203, configured to judge whether the difference satisfies a preset condition, update the equivalent internal resistance estimated value based on a preset increment value if the difference does not satisfy the preset condition, and trigger the calculating module to perform the cycle operation for the charging voltage value in the voltage value-charging time sequence, and determine the current equivalent internal resistance estimated value as the equivalent internal resistance value of the supercapacitor if the difference satisfies the preset condition.
The invention also provides a storage medium, wherein a plurality of instructions are stored in the storage medium, and the instructions are suitable for being loaded by a processor to execute the supercapacitor internal resistance detection method.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (14)
1. A method for detecting the internal resistance of a super capacitor is characterized by comprising the following steps:
during the shutdown period of the super capacitor, charging and discharging the super capacitor at a preset constant current, periodically collecting the voltage value of the super capacitor in a charging state and the charging time corresponding to the voltage value according to a preset time interval in a preset interval of the charging and discharging process to obtain a voltage value-charging time sequence, and periodically collecting the voltage value of the super capacitor in a discharging state and the discharging time corresponding to the voltage value according to the preset time interval to obtain a voltage value-discharging time sequence;
acquiring a preset initial value of an equivalent internal resistance estimation value;
sequentially performing, for each charging voltage value in the voltage value-charging time sequence, the following cyclic operation: calculating a first capacitance estimation value according to the equivalent internal resistance estimation value, the charging voltage value and the charging time corresponding to the charging voltage value, and the preset constant current value, calculating a second capacitance estimation value according to the discharging voltage value in the voltage value-discharging time sequence, which is equal to the charging voltage value, the discharging time corresponding to the charging voltage value, the equivalent internal resistance estimation value, and the preset constant current value, calculating a difference value between the first capacitance estimation value and the second capacitance estimation value, and then judging whether the difference value meets a preset condition;
and if the difference value does not meet the preset condition, updating the equivalent internal resistance estimated value based on a preset increment value, executing the cyclic operation according to the charging voltage value in the voltage value-charging time sequence, and if the difference value meets the preset condition, determining the current equivalent internal resistance estimated value as the equivalent internal resistance value of the supercapacitor.
2. The method of claim 1, wherein said calculating, for each charging voltage value in the voltage value-charging time sequence, a first capacitance estimate from the equivalent internal resistance estimate, the charging voltage value and its corresponding charging time, and the value of the preset constant current comprises:
calculating a charging capacitor voltage estimated value according to the charging voltage value, the preset constant current value and the equivalent internal resistance estimated value;
and calculating the first capacitance estimated value according to the charging capacitance voltage estimated value, the preset constant current value, the charging time corresponding to the charging voltage value and the initial capacitance value of the super capacitor in the shutdown period.
3. The method of claim 2, wherein said calculating a charging capacitor voltage estimate based on the charging voltage value, the predetermined constant current value, and the equivalent internal resistance estimate comprises:
calculating the estimated value of the charge capacitor voltage according to the following formula:
UC_est_1＝Usc_1-Isc_1Req_est
wherein, Usc_1Representing said charging voltage value, Req_estRepresenting the estimated value of equivalent internal resistance, Isc_1Representing the value of said preset constant current during charging, UC_est_1Representing the charge capacitor voltage estimate.
4. The method of claim 3, wherein the calculating the first capacitance estimate based on the charging voltage value, the charging capacitance voltage estimate based on the charging capacitance voltage value, the predetermined constant current value, the charging time corresponding to the charging voltage value, and the initial capacitance value of the supercapacitor during the shutdown comprises:
calculating the first capacitance estimate as follows:
wherein, UC_est_1Representing the estimated value of the charge capacitor voltage, t1Represents the charging time corresponding to the charging voltage value, Isc_1Representing the value of said preset constant current during charging, Ceq_est_1Represents an initial capacitance value of the supercapacitor during the shutdown.
5. The method of claim 1, wherein said calculating, for each charging voltage value in the voltage value-charging time series, a second capacitance estimate from a discharging voltage value in the voltage value-discharging time series equal to the charging voltage value and its corresponding discharging time, the equivalent internal resistance estimate, and the value of the preset constant current comprises:
calculating a discharge capacitance voltage estimated value according to the discharge voltage value, the preset constant current value and the equivalent internal resistance estimated value;
and calculating the second capacitance estimated value according to the discharge capacitance voltage estimated value, the preset constant current value, the discharge time corresponding to the discharge voltage value and the initial capacitance value of the super capacitor in the shutdown period.
6. The method of claim 5, wherein said calculating a discharge capacitance voltage estimate based on the charging voltage value, the discharge voltage value, the predetermined constant current value, and the equivalent internal resistance estimate comprises:
calculating the discharge capacitance voltage estimate according to:
UC_est_2＝Usc_2-Isc_2Req_est
wherein, Usc_2Represents the discharge voltage value, Req_estRepresenting the estimated value of equivalent internal resistance, Isc_2Representing the value of said preset constant current during discharge, UC_est_2Representing the discharge capacitance voltage estimate.
7. The method of claim 6, wherein calculating the second capacitance estimate based on the discharge capacitance voltage estimate, the predetermined constant current value, the discharge time corresponding to the discharge voltage value, and the initial capacitance value of the ultracapacitor during the shutdown comprises:
calculating the first capacitance estimate as follows:
wherein, UC_est_2Representing the discharge capacitance voltage estimate, t2Indicating the discharge time corresponding to the discharge voltage value, Isc_2Representing the value of said preset constant current during discharge, Ceq_est_2Represents an initial capacitance value of the supercapacitor during the shutdown.
8. The method according to claim 1, wherein the preset interval of the charging and discharging process refers to a charging interval in which the voltage value of the supercapacitor is between 30% of the maximum voltage and a discharging interval in which the voltage value of the supercapacitor is between 30% of the maximum voltage and the maximum voltage.
9. The method of claim 1, wherein the predetermined time interval is 1 μ s, and the predetermined initial value of the estimated equivalent internal resistance is 0m Ω or 0.01m Ω.
10. The method of claim 1, wherein the predetermined condition is that a ratio of the difference to an average of the first capacitance estimate and the second capacitance estimate is less than 1%.
11. The method of claim 1, wherein the preset incremental value is 0.01m Ω.
12. The method of claim 1, wherein said updating the estimated equivalent internal resistance value based on a preset delta value comprises:
and adding the current equivalent internal resistance estimated value and the preset incremental value to serve as a new equivalent internal resistance estimated value.
13. A detection device for internal resistance of a super capacitor is characterized by comprising:
the data acquisition and preprocessing module is used for charging and discharging the super capacitor at preset constant current during the shutdown period of the super capacitor, periodically acquiring the voltage value of the super capacitor in a charging state and the charging time corresponding to the voltage value according to preset time intervals in a preset interval of the charging and discharging process to obtain a voltage value-charging time sequence, periodically acquiring the voltage value of the super capacitor in a discharging state and the discharging time corresponding to the voltage value according to the preset time intervals to obtain a voltage value-discharging time sequence, and acquiring a preset initial value of the equivalent internal resistance estimation value;
a calculating module, configured to sequentially perform the following cyclic operations for each charging voltage value in the voltage value-charging time sequence: calculating a first capacitance estimation value according to the equivalent internal resistance estimation value, the charging voltage value and the charging time corresponding to the charging voltage value, and the preset constant current value, calculating a second capacitance estimation value according to the discharging voltage value in the voltage value-discharging time sequence, which is equal to the charging voltage value, and the discharging time corresponding to the charging voltage value, the equivalent internal resistance estimation value, and the preset constant current value, and calculating a difference value between the first capacitance estimation value and the second capacitance estimation value;
and the judging module is used for judging whether the difference value meets a preset condition, updating the equivalent internal resistance estimated value based on a preset increment value if the difference value does not meet the preset condition, triggering the calculating module to execute the circulating operation aiming at the charging voltage value in the voltage value-charging time sequence, and determining the current equivalent internal resistance estimated value as the equivalent internal resistance value of the super capacitor if the difference value meets the preset condition.
14. A storage medium having stored therein a plurality of instructions adapted to be loaded by a processor to perform the method of any one of claims 1 to 12.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114865731A (en) * | 2022-04-13 | 2022-08-05 | 中国船舶重工集团公司第七一一研究所 | Compensation method and device for charging of super capacitor, electronic equipment and storage medium |
| CN115436824A (en) * | 2022-11-08 | 2022-12-06 | 苏州浪潮智能科技有限公司 | Super capacitor test method and device, electronic equipment and storage medium |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09211041A (en) * | 1996-01-30 | 1997-08-15 | Hioki Ee Corp | Method and device for measuring equivalent series resistance of capacitive element |
| CN101339230A (en) * | 2007-07-06 | 2009-01-07 | 鸿富锦精密工业（深圳）有限公司 | Method and apparatus for measuring battery internal resistance |
| JP2010185759A (en) * | 2009-02-12 | 2010-08-26 | Yaskawa Electric Corp | Method for estimating electrostatic capacitance and internal resistance of capacitor and measurement apparatus of same |
| US20120004875A1 (en) * | 2010-06-30 | 2012-01-05 | Reizo Maeda | Method of detecting battery internal resistance |
| CN104020353A (en) * | 2014-03-12 | 2014-09-03 | 宁波南车新能源科技有限公司 | Supercapacitor internal resistance measurement method |
| CN106058955A (en) * | 2016-05-18 | 2016-10-26 | 深圳天邦达科技有限公司 | Lithium battery pack management system of smart balance car |
| CN108693408A (en) * | 2018-08-22 | 2018-10-23 | 广东电网有限责任公司 | Ultracapacitor internal resistance detection method, device and computer readable storage medium |
| CN108918968A (en) * | 2018-03-30 | 2018-11-30 | 金卡智能集团股份有限公司 | Super capacitor DC internal resistance test method, switching time algorithm and readable medium |
| CN111781520A (en) * | 2020-06-28 | 2020-10-16 | 青岛美凯麟科技股份有限公司 | Power battery or super capacitor internal resistance test system and test method |
| CN111896875A (en) * | 2020-07-28 | 2020-11-06 | 江苏理工学院 | Power battery SOC estimation method considering hysteresis effect |
-
2022
- 2022-01-04 CN CN202210001758.1A patent/CN114325199B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09211041A (en) * | 1996-01-30 | 1997-08-15 | Hioki Ee Corp | Method and device for measuring equivalent series resistance of capacitive element |
| CN101339230A (en) * | 2007-07-06 | 2009-01-07 | 鸿富锦精密工业（深圳）有限公司 | Method and apparatus for measuring battery internal resistance |
| JP2010185759A (en) * | 2009-02-12 | 2010-08-26 | Yaskawa Electric Corp | Method for estimating electrostatic capacitance and internal resistance of capacitor and measurement apparatus of same |
| US20120004875A1 (en) * | 2010-06-30 | 2012-01-05 | Reizo Maeda | Method of detecting battery internal resistance |
| CN104020353A (en) * | 2014-03-12 | 2014-09-03 | 宁波南车新能源科技有限公司 | Supercapacitor internal resistance measurement method |
| CN106058955A (en) * | 2016-05-18 | 2016-10-26 | 深圳天邦达科技有限公司 | Lithium battery pack management system of smart balance car |
| CN108918968A (en) * | 2018-03-30 | 2018-11-30 | 金卡智能集团股份有限公司 | Super capacitor DC internal resistance test method, switching time algorithm and readable medium |
| CN108693408A (en) * | 2018-08-22 | 2018-10-23 | 广东电网有限责任公司 | Ultracapacitor internal resistance detection method, device and computer readable storage medium |
| CN111781520A (en) * | 2020-06-28 | 2020-10-16 | 青岛美凯麟科技股份有限公司 | Power battery or super capacitor internal resistance test system and test method |
| CN111896875A (en) * | 2020-07-28 | 2020-11-06 | 江苏理工学院 | Power battery SOC estimation method considering hysteresis effect |
Non-Patent Citations (2)
| Title |
|---|
| ALIN GRAMA: "Experimental determination of Equivalent Series Resistance of a supercapacitor", 2009 32ND INTERNATIONAL SPRING SEMINAR ON ELECTRONICS TECHNOLOGY, pages 1 - 4 * |
| 姚雨迎, 张东来, 秦海亮, 鲍志云: "超级电容器ESR的测试方法研究", 测控技术, no. 02, pages 15 - 17 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114865731A (en) * | 2022-04-13 | 2022-08-05 | 中国船舶重工集团公司第七一一研究所 | Compensation method and device for charging of super capacitor, electronic equipment and storage medium |
| CN114865731B (en) * | 2022-04-13 | 2023-11-07 | 中国船舶集团有限公司第七一一研究所 | Compensation method and device for charging super capacitor, electronic equipment and storage medium |
| CN115436824A (en) * | 2022-11-08 | 2022-12-06 | 苏州浪潮智能科技有限公司 | Super capacitor test method and device, electronic equipment and storage medium |
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