CN114302134A - CPHY signal voltage detection and voltage feedback multi-camera detection device - Google Patents

Abstract

The invention discloses a multi-camera detection device for CPHY signal voltage detection and voltage feedback, which comprises four paths of CPHY 2.5Gsps data receiving circuits, four paths of DPHY2.5Gbps data receiving circuits, a CPHY/DPHY LP level detection module, an I2C/I3C bus holding voltage detection module, an open short circuit module, an image cache module and a digital voltage supply module with feedback, wherein the CPHY module and the DPHY module are decoded by an FPGA (field programmable gate array) and received by an FPGA LVDS (low voltage differential signaling) interface, and the CPHY data is received by an FPGA GTX interface; writing the data into DDR4 at a high speed through FPGA DDR4IP, and caching the data; the FPGA GTX is connected with the PC through an optical fiber interface, and the FPGA high-speed read-write DDR4 transmits the multi-shot image data to the PC; the device provides 32 digital power supply modules and can support the camera to carry out simultaneous open-short circuit test; the invention aims to solve the problems of LP level monitoring in the transmission process of high-speed signals such as CPHY, DPHY and the like and level monitoring in the communication process of I2C/I3C, and simultaneously improve the digital voltage supply precision to be within 10mv besides increasing the number of digital power supplies.

Description

CPHY signal voltage detection and voltage feedback multi-camera detection device

Technical Field

The invention relates to a multi-camera detection device for CPHY signal voltage detection and voltage feedback, and belongs to the technical field of camera testing.

Background

In the mobile communication era, mobile phones become essential for people's life, and the requirements of people on the image frame rate and the image quality level are continuously improved; the flag-based ship-level camera module has higher requirements on power stability, precision, noise fluctuation, signal to noise ratio, bit error rate and the like; firstly, the power supply noise can directly affect the OB value of an image (zero value under the condition of full black of a photosensitive chip), and certainly can also reflect the image noise of a camera; the LP signal measurement of the CPHY and the DPHY is used for testing whether the camera product has the problem of weak signal output or not and for detecting the problem of bit error rate possibly caused by weak image output capability of a camera module caused by chips, design, processes and the like; for the performance of a camera for detecting the flagship, higher requirements are also provided for the stability, the power performance and the signal detection capability of a test system, in addition, CPHY1.5Gsps cannot meet the test requirements, and DPHY2.5G and CPHY 2.5Gsps also become necessary requirements. Based on the above, the invention adopts the ten-gigabit optical fiber as the data transmission protocol between the PC and the testing device, and adopts two transmission modes of 20G and 40G.

Disclosure of Invention

The invention aims to overcome the defects in the prior art, and firstly provides a scheme that 4 paths of CPHY reaches 2.5Gbps and DPHY reaches 2.5 Gbps; secondly, a scheme for detecting the LP level of the CPHY/DPHY signal and detecting the I2C signal level is provided; the secondary system also provides a large-current power supply scheme aiming at the far-end back-collapse precision of the digital power supply band reaching 10 mv; meanwhile, the system provides a DDR4 cache, self-brought open short circuit detection, with current detection, FPGA with embedded image scheme, and a scheme of sending images to a PC end at 20G/40G time.

The technical solution of the invention is realized as follows: a multi-camera detection device for CPHY signal voltage detection and voltage feedback comprises an image acquisition card, wherein the image acquisition card comprises a camera module, an FPGA chip, a CPHY circuit module, a DDR4 cache circuit, an I2C/I3C module and a level detection circuit; the camera module is used for collecting images, the CPHY circuit module is electrically connected with the camera module, and the CPHY circuit module adopts a CPHY 2.5Gsps data receiving circuit; the FPGA chip is internally provided with a CPHY IP core and is used for analyzing signals of the CPHY circuit module to obtain corresponding image data; the DDR4 cache circuit is used for caching image data, the FPGA chip reads and writes the image data to the DDR4 cache circuit, and the FPGA chip is communicated with the camera module through an I2C/I3C module; the CPHY circuit module and the I2C/I3C module are connected to a level detection circuit.

Preferably, the FPGA chip performs remote data transmission with a PC through an optical module and a gigabit optical network card; the optical module adopts a 20G/40G ten-gigabit optical fiber interface, and the optical fiber interface is connected with the GTX of the FPGA chip.

Preferably, the CPHY circuit module consists of a signal amplification circuit (DS25CP114) and a signal shaping circuit (DS100BR410 SQE); the DS25CP114 and the DS100BR410SQE both meet the requirement of high-speed processing of CPHY 2.5G frequency, wherein the rising edge and the falling edge of the data waveform amplified by the DS100BR410SQE from the DS25CP114 are steeper, and the waveform sampling of the FPGA is facilitated.

Preferably, the digital video camera further comprises a DPHY circuit module, a DPHY IP core is built in the FPGA chip and used for analyzing signals of the DPHY circuit module to obtain corresponding image data, and the DPHY circuit module is connected to the level detection circuit.

Preferably, the camera module is connected to the CPHY circuit module or the DPHY circuit module through the switch circuit module, and the switch circuit module is connected to the O/S circuit module.

Preferably, the camera module is connected to a digital power supply module with feedback, the digital power supply module with feedback adopts 4-8 power supply design, the precision of the power supply reaches 10mv, the camera module further comprises a far-end feedback circuit for the power supply voltage, and the feedback circuit performs voltage compensation on the power supply voltage according to the change of the voltage value of the large current in the transmission process.

Due to the application of the technical scheme, compared with the prior art, the invention has the following advantages:

1. the invention provides a solution for measuring CPHY/DPHY LP voltage and a solution for measuring I2C/I3C level, and meets the higher requirement of a flagship camera on signal monitoring.

2. The invention also provides a solution with 32-path high-precision digital power supply with feedback, and the precision can reach 10 mv.

3. The invention also provides a solution scheme which can realize simultaneous measurement of four cameras, wherein the four CPHY rates can reach 2.5Gbps, and the four DPHY rates can reach 2.5 Gbps.

4. The invention uses the image transmission scheme that four paths of cameras transmit images to the PC end through 20G or 40G optical fiber.

5. The invention also integrates the functions of 4 DDR4 storage reading, OS open short circuit detection, DPHY circuit and the like; wherein the main control chip is an FPGA XCKU11P-2FFVE1517E3991 of xilinx.

6. The invention has unique ID, and the test software algorithm can support external arbitrary configuration.

Drawings

The technical scheme of the invention is further explained by combining the accompanying drawings as follows:

FIG. 1 is a block diagram of the overall architecture of the multi-camera detection device for CPHY signal voltage detection and voltage feedback according to the present invention;

FIG. 2 is a circuit diagram of an ADC for CPHY/DPHY LP level detection, I2C/I3C level detection according to the present invention;

FIG. 3 is a circuit diagram of the CPHY/DPHY ADC pin switching circuit of the present invention;

FIG. 4 is an I2C/I3C module ADC pin switching circuit of the present invention;

FIG. 5 is a circuit diagram of the CPHY signal amplification circuit of the present invention;

FIG. 6 is a schematic diagram of the CPHY waveform shaping circuit of the present invention;

fig. 7 is a circuit diagram of a digital power supply module with feedback of the present invention.

Detailed Description

The invention is described below with reference to the accompanying drawings.

As shown in fig. 1, the multi-camera detection device for CPHY signal voltage detection and voltage feedback according to the present invention includes an image acquisition card, the image acquisition card is connected with a gigabit optical network card/accelerator card through two optical modules, and the long-distance transmission of data is realized through two or four optical fibers 20G, 40G, and the transmission distance is related to the power and wavelength of the selected optical module.

The image acquisition card comprises: the device comprises a camera module, an FPGA chip, a CPHY circuit module, a DPHY circuit module, a switch circuit module, a DDR4 cache circuit, an I2C/I3C module, a level detection circuit, a digital power supply module with feedback (including current) and an O/S circuit module; the FPGA chip adopts an FPGA XCKU11P, hereinafter referred to as FPGA.

As shown in FIG. 2, the ADC circuit of the multi-shot detection device for CPHY signal voltage detection and voltage feedback is used for CPHY/DPHY LP level detection and level detection of I2C/I3C.

As shown in FIG. 3, the CPHY/DPHY ADC pin switching circuit of the multi-shot detection device for CPHY signal voltage detection and voltage feedback switches the measurement of CPHY or DPHY LP level on different pins.

As shown in FIG. 4, the I2C and I3C ADC pin switching circuits of the multi-shot detection device for detecting the voltage of the CPHY signal and feeding the voltage switch the measurement of I2C/I3C levels of different pins.

As shown in fig. 5, the CPHY signal amplification module of the multi-camera detection device for CPHY signal voltage detection and voltage feedback uses a DS25CP114 chip to convert the three-wire differential of the CPHY into three pairs of two-wire differential which can be received by the FPGA, and amplifies the signal, thereby reducing the signal attenuation effect caused by the circuit impedance.

As shown in fig. 5 and 6, the CPHY waveform shaping circuit of the multi-shot detection device for CPHY signal voltage detection and voltage feedback uses a DS100BR410SQE chip to change the waveform caused by circuit impedance or switch impedance to be steeper, thereby facilitating multi-sampling recovery at the back end.

As shown in FIGS. 5 and 7, the high-precision digital power module with feedback for the multi-shot detection device for CPHY signal voltage detection and voltage feedback uses an ISL68300IRAZ-TK DCDC device to output voltage, and uses a chip TP1981-CR to perform feedback adjustment on the voltage value at the far end, and the output voltage precision can reach 10 mv.

Specifically, the computer PC transmits data to the FPGA through an optical fiber interface, and also receives camera image data which is sent by the FPGA through a UDP protocol and cached by the DDR4 through the optical fiber interface; the FPGA separates the transmission data to obtain I2C/I3C data, controls I2C/I3C buses of the four-path camera according to the selected control time sequence, and configures related chips such as camera products, device power supplies and the like.

The CPHY waveform needs to be accessed to an FPGA GTX interface through a CPHY circuit (through an amplifying circuit and a waveform shaping circuit), and a CPHY ip core is built in the FPGA and used for analyzing corresponding CPHY signals to obtain corresponding image data.

The DPHY waveform needs to be accessed into an FPGA LVDS interface through a DPHY circuit, and a DPHY ip core is built in the FPGA and used for analyzing corresponding DPHY signals to obtain corresponding image data.

The output waveform of the camera is selectively accessed into the DPHY circuit and the CPHY circuit through high-speed switch switching and is controlled by software.

The DPHY/CPHY LP level detection and the I2C/I3C level detection adopt ADC chips MAX11331ATJ +, different PIN PINs access signals into the ADC chips through a high-speed switch, the ADC chips are connected with the FPGA through SPI interfaces, and acquired level data are transmitted to the FPGA after AD conversion.

The high-precision digital power supply module with feedback is used for supplying power to the camera, internal resistance exists in a PCB or a connector, all PIN PINs between the power output end of the testing device and the camera need to be disconnected due to OS testing, and internal resistance also exists in a used switch chip; with the increase of the current demand of the high-pixel chip and the requirement of the voltage supply precision of the chip less than 10mv, the voltage of the power output end reaching the input end of the actual camera is reduced to some extent, so that a feedback circuit of the camera input end needs to be added, and the voltage of the input end needs to be adjusted more finely.

Furthermore, in the CPHY circuit module, three DS25cp114 chips of TI are used in the signal amplification circuit, and three pairs of differential signals are restored and amplified from the CPHY waveforms of 3 trios (CPHY is quintuple data). The TIDS100BR410SQE is used in a signal shaping circuit to shape the waveform, so that the rising edge and the falling edge are steeper (the waveform is flattened due to the influence of circuit and material internal resistance), the level value misjudgment of the FPGA GTX in the data acquisition process is avoided, and the error rate of CPHY data reduction is reduced.

Furthermore, the FPGA adopts an Xlinx FPGA XCKU11P-2FFVE1517E3991 which is a device main control chip and is used for collecting and restoring DPHY and CPHY image data, storing the image data into a DDR4, writing the data into a photosensitive chip through an I2C/I3C, controlling the power supply time sequence of a power supply required by the photosensitive chip, and transmitting the image data to a PC (personal computer) end through an optical fiber module at the rate of 20G/S or 40G through a GTX (GTX) port according to the requirement of an upper computer.

The above-mentioned embodiments are merely illustrative of the technical idea and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the scope of the present invention, and all equivalent changes or modifications made according to the spirit of the present invention should be covered in the scope of the present invention.

Claims (6)

1. A CPHY signal voltage detection and voltage feedback multi-camera detection device is characterized in that: the device comprises an image acquisition card, wherein the image acquisition card comprises a camera module, an FPGA chip, a CPHY circuit module, a DDR4 cache circuit, an I2C/I3C module and a level detection circuit; the camera module is used for collecting images, the CPHY circuit module is electrically connected with the camera module, and the CPHY circuit module adopts a CPHY 2.5Gsps data receiving circuit; the FPGA chip is internally provided with a CPHY IP core and is used for analyzing signals of the CPHY circuit module to obtain corresponding image data; the DDR4 cache circuit is used for caching image data, the FPGA chip reads and writes the image data to the DDR4 cache circuit, and the FPGA chip is communicated with the camera module through an I2C/I3C module; the CPHY circuit module and the I2C/I3C module are connected to a level detection circuit.

2. The apparatus of claim 1 for multi-shot detection of CPHY signal voltage detection and voltage feedback, wherein: the FPGA chip is in remote data transmission with a PC through an optical module and a gigabit optical network card; the optical module adopts a 20G/40G ten-gigabit optical fiber interface, and the optical fiber interface is connected with the GTX of the FPGA chip.

3. The apparatus of claim 1 for multi-shot detection of CPHY signal voltage detection and voltage feedback, wherein: the CPHY circuit module consists of a signal amplification circuit (DS25CP114) and a signal shaping circuit (DS100BR410 SQE); the DS25CP114 and the DS100BR410SQE both meet the requirement of high-speed processing of CPHY 2.5G frequency, wherein the rising edge and the falling edge of the data waveform amplified by the DS100BR410SQE from the DS25CP114 are steeper, and the waveform sampling of the FPGA is facilitated.

4. The apparatus of claim 1 for multi-shot detection of CPHY signal voltage detection and voltage feedback, wherein: the digital image processing device further comprises a DPHY circuit module, a DPHY IP core is built in the FPGA chip and used for analyzing signals of the DPHY circuit module to obtain corresponding image data, and the DPHY circuit module is connected to the level detection circuit.

5. The apparatus of claim 4 for multi-shot detection of CPHY signal voltage detection and voltage feedback, characterized in that: the camera module is connected with the CPHY circuit module or the DPHY circuit module through the switch circuit module, and the switch circuit module is connected with the O/S circuit module.

6. The apparatus of claim 1 for multi-shot detection of CPHY signal voltage detection and voltage feedback, wherein: the camera module is connected to a digital power supply module with feedback, the digital power supply module with feedback adopts 4 to 8 power supply designs, the precision of the power supply reaches 10mv, the camera module further comprises a far-end feedback circuit for the power supply voltage, and the feedback circuit performs voltage compensation on the power supply voltage according to the change of the voltage value of the large current in the transmission process.

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