CN114301441B - Linear equalizer and MIPI C-PHY circuit - Google Patents
Linear equalizer and MIPI C-PHY circuit Download PDFInfo
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Abstract
The invention discloses a linear equalizer and an MIPI C-PHY circuit. The linear equalizer includes a linear equalization circuit and a differential amplification circuit. The PMOS tube is adopted as a differential input pair tube in the linear equalization circuit, so that the low common mode signal level of 100-300 mv can be supported, the attenuation amplitude of the low-frequency gain and the position of the high-frequency pole can be respectively set by combining an adjustable resistor and an adjustable capacitor, the controllable low-frequency attenuation is obtained, the gain curve of high-frequency compensation can realize corresponding compensation according to different attenuation conditions of an actual channel, and further flat frequency response is obtained; the differential amplifying circuit is additionally arranged behind the linear equalizing circuit, so that the output of the linear equalizer has larger signal amplitude, for example, about 6db gain is provided for signals within 4Ghz, and the subsequent comparator is convenient to process, thereby providing powerful guarantee for accurate recovery of data.
Description
Technical Field
The invention belongs to the technical field of signal transmission, and particularly relates to a linear equalizer and an MIPI C-PHY circuit.
Background
In recent years, with the increase of information quantity, smart phones are developed to large-screen high-pixelation. The amount of data for transmitting video signals on the display screen is also increasing. For efficient transmission of signals, a differential transmission interface called MIPI D-PHY is generally used. But to pursue higher transmission speeds MIPI C-PHY is beginning to be used. MIPI C-PHY is a data transmission specification in a portable device formulated by MIPI Alliance, the maximum of the line of the D-PHY1 group is 2.5Gbps, and the signal speed of the C-PHY can reach 7.98 Gbps. Typically, the 1-group line of the differential transmission line D-PHY is composed of 2 leads, and the 1-group line of the C-PHY is a complex differential transmission line composed of 3 leads.
Just as high-speed three-wire voltage signals up to 3.5Gsps need to be transmitted in an electrical wired channel in MIPI C-PHY communications, high-speed signals propagating through the wired channel are prone to losses due to reflection, dielectric loss, and skin effect. These losses delay the rise and fall time of the signal and reduce the amplitude of the signal, deteriorating the quality of the signal, resulting in too much jitter (jitter) of the data recovered by the receiver, i.e. too much variation of the data time width from an ideal time unit (ui), and further result in too much jitter of the clock derived based on the recovered data. Both these corrupted data and clock will cause errors in the received data.
Disclosure of Invention
Aiming at the defects or improvement demands of the prior art, the invention provides a linear equalizer and an MIPI C-PHY circuit, which can support low common mode signal level of 100-300 mv and realize corresponding compensation according to different attenuation conditions of an actual channel, so as to obtain a flat frequency response system, and the accuracy of data recovery is high.
To achieve the above object, according to one aspect of the present invention, there is provided a linear equalizer including a linear equalization circuit; the linear equalization circuit comprises a current source, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first resistor and a second resistor; the first end of the first transistor is used for being connected with a power supply VDD, the second end of the first transistor is connected with the negative electrode of a current source, the control end of the first transistor is connected with the second end of the first transistor, the control end of the second transistor and the control end of the third transistor, and the positive electrode of the current source is used for being grounded; the first end of the second transistor is used for being connected with the power supply VDD, the second end of the second transistor is connected with the first end of the fourth transistor, the first end of the third transistor is used for being connected with the power supply VDD, and the second end of the third transistor is connected with the first end of the fifth transistor; the second end of the fourth transistor is connected with the first end of the first resistor, the second end of the first resistor is used for being grounded, the second end of the fifth transistor is connected with the first end of the second resistor, and the second end of the second resistor is used for being grounded; the control end of the fourth transistor is used as the first input end of the linear equalization circuit and the first input end of the linear equalizer, the control end of the fifth transistor is used as the second input end of the linear equalization circuit and the second input end of the linear equalizer, the second end of the fourth transistor is used as the first output end of the linear equalization circuit, and the second end of the fifth transistor is used as the second output end of the linear equalization circuit.
In some embodiments, the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are PMOS transistors.
In some embodiments, the linear equalization circuit further comprises a pole-zero adjustment module; and two ends of the pole-zero adjusting module are respectively connected with the second end of the second transistor and the second end of the third transistor, and the pole-zero adjusting module is used for adjusting the zero position of the frequency response curve of the linear equalization circuit and the position of the first pole.
In some embodiments, the linear equalization circuit further comprises a pole-zero adjustment module comprising a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitance, and a second capacitance; the first end of the sixth transistor is connected with the first end of the seventh transistor through the first capacitor, the second end of the sixth transistor is connected with the second end of the second transistor, the second end of the seventh transistor is connected with the second end of the third transistor, and the control end of the sixth transistor and the control end of the seventh transistor are connected to form a first control end for receiving a first control signal; the first end of the eighth transistor is connected with the first end of the ninth transistor through the second capacitor, the second end of the eighth transistor is connected with the second end of the second transistor, the second end of the ninth transistor is connected with the second end of the third transistor, and the control end of the eighth transistor and the control end of the ninth transistor are connected to form a second control end for receiving a second control signal.
In some embodiments, the linear equalization circuit further comprises a low frequency gain adjustment module; the two ends of the low-frequency gain adjusting module are respectively connected with the second end of the second transistor and the second end of the third transistor, and the low-frequency gain adjusting module is used for adjusting the low-frequency gain of the frequency response curve of the linear equalization circuit.
In some embodiments, the linear equalization circuit further includes a low frequency gain adjustment module including a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a tenth transistor, and an eleventh transistor; the first end of the tenth transistor is connected with the second end of the second transistor through a third resistor, the second end of the tenth transistor is connected with the second end of the third transistor through a fourth resistor, and the control end of the tenth transistor forms a third control end and is used for receiving a third control signal; the first end of the eleventh transistor is connected with the second end of the second transistor through the fifth resistor, the second end of the eleventh transistor is connected with the second end of the third transistor through the sixth resistor, and the control end of the eleventh transistor forms a fourth control end and is used for receiving a fourth control signal.
In some embodiments, the linear equalizer further comprises a differential amplifying circuit, and the differential amplifying circuit is configured to amplify an output signal of the linear equalizing circuit to obtain a larger signal amplitude.
In some embodiments, the linear equalizer further comprises a differential amplification circuit comprising a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a seventh resistor, and an eighth resistor; the first end of the twelfth transistor is used for being connected with the power supply VDD, the second end of the twelfth transistor is connected with the first end of the thirteenth transistor and the first end of the fourteenth transistor, the control end of the twelfth transistor is connected with the control end of the first transistor, the second end of the thirteenth transistor is connected with the first end of the seventh resistor, the second end of the seventh resistor is used for being grounded, the second end of the fourteenth transistor is connected with the first end of the eighth resistor, and the second end of the eighth resistor is used for being grounded; the control end of the thirteenth transistor is used as the first input end of the differential amplifying circuit, is connected with the first output end of the linear equalizing circuit, the control end of the fourteenth transistor is used as the second input end of the differential amplifying circuit, is connected with the second output end of the linear equalizing circuit, the second end of the thirteenth transistor is used as the first output end of the differential amplifying circuit and the first output end of the linear equalizer, and the second end of the fourteenth transistor is used as the second output end of the differential amplifying circuit and the second output end of the linear equalizer.
According to another aspect of the present invention, there is provided an MIPI C-PHY circuit including a data and clock recovery circuit; the data and clock recovery circuit is used for acquiring a first voltage of the first transmission line, a second voltage of the second transmission line and a third voltage of the third transmission line; the data and clock recovery circuit includes the linear equalizer described above for processing the first voltage, the second voltage, and the third voltage.
In some embodiments, the MIPI C-PHY circuit further comprises a decoder; the data and clock recovery circuit is used for synchronously sampling and converting data in series and parallel based on the difference value of the voltage signals processed by the linear equalizer, and then transmitting the data to the decoder for decoding.
In general, the above technical solutions conceived by the present invention have the following beneficial effects compared with the prior art: the PMOS tube is adopted as a differential input pair tube in the linear equalization circuit, so that the low common mode signal level of 100-300 mv can be supported, the attenuation amplitude of the low-frequency gain and the position of the high-frequency pole can be respectively set by combining an adjustable resistor and an adjustable capacitor, thereby obtaining a controllable low-frequency attenuation, and a gain curve of high-frequency compensation can realize corresponding compensation according to different attenuation conditions of an actual channel, namely, the low-frequency attenuation is controlled, the high frequency is compensated, and further, the flat frequency response is obtained; the differential amplifying circuit is additionally arranged behind the linear equalizing circuit, so that the output of the linear equalizer has larger signal amplitude, for example, about 6dB gain is provided for signals within 4GHz, and the subsequent comparator is convenient to process, thereby providing powerful guarantee for accurate recovery of data.
Drawings
FIG. 1 is a schematic diagram of the MIPI C-PHY circuit according to one embodiment of the invention;
FIG. 2 is a schematic diagram of a data and clock recovery circuit according to an embodiment of the invention;
fig. 3 is a schematic diagram of a linear equalizer according to an embodiment of the present invention;
fig. 4 is a graph showing a comparison of a frequency response curve (a curve) of a transmission link, a frequency curve (B curve) of a linear equalization circuit, and a frequency response curve (C curve) of the transmission link with the linear equalization circuit according to an embodiment of the present invention;
fig. 5 is a graph showing the comparison of the frequency response curve (C curve) of the transmission link with the linear equalizer circuit, the frequency response curve (D curve) of the differential amplifier, and the frequency response curve (E curve) of the transmission link with the linear equalizer circuit according to the embodiment of the present invention;
FIG. 6A is a signal eye diagram through a linear equalizer;
FIG. 6B is a signal eye diagram without a linear equalizer;
FIG. 7 is a simulated timing diagram of an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. As will be recognized by those of skill in the pertinent art, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present application. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.
In order to make the time width of the data obtained by the receiver as accurate as possible, it is considered to use a linear equalizer (CTLE) before the receiver to compensate the loss of the signal by the channel at high frequency. Since the MIPI C-PHY protocol specifies a voltage range of 100-300 mv for signals, the operating voltage range of the linear equalizer is 0.8v, and the common-use NMOS as an input to the linear equalizer of the pipeline can handle a signal common-mode voltage range of 500-700 mv, such linear equalizer cannot handle 100-300 mv of input signals. The processing method is to use a PMOS tube as an input pair tube, use a current source as a load to realize a source follower differential pair, and increase the common-mode voltage of an input signal to 500-700 mv which can be processed by a linear equalizer. However, this solution consumes current consumption and a certain area of the mA stage, and since the source follower is a source follower, gain cannot be obtained through the differential pair circuit except for the enhancement of the common mode voltage. Furthermore, such linear equalizers rely mainly on gain attenuation at low frequencies of the signal and on shaping the signal of the channel by movement of the first pole, and thus contribute little to the high frequency gain, so that although the shaped signal quality and integrity (jitter) can be improved, the signal amplitude becomes smaller, which can easily lead to errors in the data recovered by the following receiver.
In fact, for high-speed three-wire voltage signals of 100-300 mv up to 3.5Gsps, after passing through the channel loss, the high frequency component is attenuated by more than half, and the data and clock recovered by the receiver may deteriorate, resulting in sampling errors. Therefore, it is necessary to add a linear equalizer (CTLE) in front of the receiver and compensate for the attenuation of the signal by properly designing the structure of the linear equalizer to achieve accurate data and clock recovery.
According to the invention, on the one hand, a PMOS (P-channel metal oxide semiconductor) tube is adopted as a differential input pair tube in the linear equalization circuit, and the linear equalization circuit supporting a lower input common mode can be used for receiving signals in a voltage range of 100-300 mv specified by MIPI C-PHY (metal-oxide-semiconductor field-effect transistor) protocol, so that power consumption and area consumption caused by additionally designing a common mode voltage lifting circuit are avoided. In addition, by combining the adjustable resistor and the adjustable capacitor, the attenuation amplitude of the low-frequency gain and the position of the high-frequency pole can be respectively set, so that a controllable low-frequency attenuation and high-frequency compensation gain curve is obtained, and corresponding compensation can be realized according to different attenuation conditions of an actual channel, and a flat frequency response system is obtained.
On the other hand, the output end of the linear equalization circuit is connected in parallel with a differential amplification circuit, for example, the differential amplification circuit comprises two PMOS tubes as input pair tubes, two resistors are used as load resistors to be connected between the drain of the input pair tubes and the ground, and the drain of one current source and the source of the two input pair tubes are connected together to supply current to the input pair tubes. The differential amplifying circuit can provide about 6dB gain for the signal within 4GHz, so that the output of the linear equalizer has larger signal amplitude, and the subsequent comparator is convenient to process, thereby providing powerful guarantee for accurate recovery of data.
As shown in fig. 1, the MIPI C-PHY circuit of an embodiment of the invention includes a transmitter and a receiver that are connected by a transmission link. The connection system is commonly used in high-speed data communication of low-power-consumption intelligent equipment such as mobile phones, cameras, tablet computers and the like. For example, a typical application is that a camera may process a large amount of photographed image data by transmitting it to a CPU having a C-PHY receiver (slave) using a master chip (master) having a C-PHY transmitter, or that a CPU may display a large amount of displayed image data by transmitting it to a display having a C-PHY receiver (slave) using a master chip (master) having a C-PHY transmitter.
The transmitter includes an encoder, and first, second and third drivers connected to the encoder, respectively. As previously described, the C-PHY transmitter utilizes three transmission lines to transmit data. After the encoder encodes the original data and the clock, the original data and the clock are divided into three paths to be sent out through a first driver, a second driver and a third driver respectively, and the encoded data reach a receiver through a transmission link by a first transmission line A, a second transmission line B and a third transmission line C. The three transmission lines A, B and C are respectively configured as a first voltage signal, a second voltage signal, or a third voltage signal, wherein the first voltage signal is greater than the second voltage signal and the third voltage signal, and the second voltage signal is greater than the third voltage signal, that is, the first voltage signal corresponds to a high voltage signal, for example 300mv, the second voltage signal corresponds to a medium voltage signal, for example 200mv, and the third voltage signal corresponds to a low voltage signal, for example 100mv. Specifically, the first voltage signal, the second voltage signal, and the third voltage signal are distributed on the three transmission lines A, B and C in different arrangements and combinations, and there are 6 combinations in total, as shown in the following table.
The receiver includes a data and clock recovery circuit and a decoder coupled to the data and clock recovery circuit. The Data and clock recovery circuit obtains a first output data_ab, a second output data_bc, and a third output data_ca based on a difference between voltages of the transmission lines A, B and C, respectively, i.e., data_ab is obtained based on VA-VB, data_bc is obtained based on VB-VC, data_ca is obtained based on VC-VA, where VA is a voltage of the transmission line a, VB is a voltage of the transmission line B, and VC is a voltage of the transmission line C. Since there are 6 different combinations of VA, VB and VC, there are six possible values for data_ab, data_bc and data_ca. According to the coding rule of the C-PHY, each time Data of one ui is transmitted (even if Data 0 is always transmitted), voltage values of at least two transmission lines are exchanged between the three transmission lines A, B and C, and therefore, at least one of data_ab, data_bc and data_ca hops at each ui time. It is according to this feature that the clock recovery circuit obtains a positive pulse at each ui time, and the clock of this positive pulse can be used to sample and deserialize the data synchronously, and send it to the subsequent decoder (decoder) for decoding.
The transmission link (interface) shown in fig. 1 is a connection model of a channel, and after a signal passes through the connection model, a high frequency component is attenuated, and an attenuation characteristic is shown in an a curve of fig. 4. As the frequency increases, the attenuation of the high frequency components of the signal also increases, and therefore, it is necessary to compensate for the high frequency loss in the signal by a linear equalizer.
Fig. 2 shows a specific embodiment of a data and clock recovery circuit, specifically, the data and clock recovery circuit includes a first linear equalizer (Continuous Time Linear Equalizer, CTLE) C1, a second linear equalizer C2, and a third linear equalizer C3, a first comparator (comparator) C4, a second comparator C5, and a third comparator C6, a clock recovery and data delay circuit (clock recovery & data delay) C7, a frequency division circuit (divider) D1, and a first serial-to-parallel conversion module (sipo) S1, a second serial-to-parallel conversion module S2, and a third serial-to-parallel conversion module S3. The clock recovery and data delay circuit C7 further includes a first delay module (delay) 201, a second delay module 203, a third delay module 205, and a clock recovery module (not shown in fig. 2).
The first input end of the first linear equalizer C1 is used as the first input end of the data and clock recovery circuit and is connected with the first transmission line A, the second input end of the first linear equalizer C1 is used as the second input end of the data and clock recovery circuit and is connected with the second transmission line B, the first input end of the second linear equalizer C2 is connected with the second transmission line B, the second input end of the second linear equalizer C2 is used as the third input end of the data and clock recovery circuit and is connected with the third transmission line C, the first input end of the third linear equalizer C3 is connected with the third transmission line C, and the second input end of the third linear equalizer C3 is connected with the first transmission line A. The first output end of the first linear equalizer C1 is connected with the first input end of the first comparator C4, the second output end of the first linear equalizer C1 is connected with the second input end of the first comparator C4, the first output end of the second linear equalizer C2 is connected with the first input end of the second comparator C5, the second output end of the second linear equalizer C2 is connected with the second input end of the second comparator C5, the first output end of the third linear equalizer C3 is connected with the first input end of the third comparator C6, and the second output end of the third linear equalizer C3 is connected with the second input end of the third comparator C6.
The output of the first comparator C4 is connected to the input of the first delay module 201 and to the first input of the clock recovery module (not shown in fig. 2), the output of the second comparator C5 is connected to the input of the second delay module 203 and to the second input of the clock recovery module, and the output of the third comparator C6 is connected to the input of the third delay module 205 and to the third input of the clock recovery module. The output end of the clock recovery module is connected with the input end of the frequency dividing circuit D1, the output end of the first delay module 201 is connected with the first input end of the first serial-to-parallel conversion module S1, the output end of the second delay module 203 is connected with the first input end of the second serial-to-parallel conversion module S2, the output end of the third delay module 205 is connected with the first input end of the third serial-to-parallel conversion module S3, and the output end of the frequency dividing circuit D1 is respectively connected with the second input end of the first serial-to-parallel conversion module S1, the second input end of the second serial-to-parallel conversion module S2 and the second input end of the third serial-to-parallel conversion module S3. The output end of the first serial-parallel conversion module S1 is used as a first group of parallel output ends of the data and clock recovery circuit, the output end of the second serial-parallel conversion module S2 is used as a second group of parallel output ends of the data and clock recovery circuit, and the output end of the third serial-parallel conversion module S3 is used as a third group of parallel output ends of the data and clock recovery circuit.
The first linear equalizer C1, the second linear equalizer C2 and the third linear equalizer C3 process the voltage signals of the first transmission line a, the second transmission line B and the third transmission line C to obtain three pairs of differential signals. Specifically, the first linear equalizer C1 processes the voltage signals of the first transmission line a and the second transmission line B to obtain a first pair of differential signals ab_p and ab_n, the second linear equalizer C2 processes the voltage signals of the second transmission line B and the third transmission line C to obtain a second pair of differential signals bc_p and bc_n, and the third linear equalizer C3 processes the voltage signals of the third transmission line C and the first transmission line a to obtain a third pair of differential signals ca_p and ca_n. The first, second and third comparators C4, C5 and C6 convert the three pairs of differential signals into three digital signals, respectively. Specifically, the first comparator C4 converts the first pair of differential signals ab_p and ab_n into the first digital signal data_ab, the second comparator C5 converts the second pair of differential signals bc_p and bc_n into the second digital signal data_bc, and the third comparator C6 converts the third pair of differential signals ca_p and ca_n into the third digital signal data_ca. The three digital signals are characterized in that at least one signal is changing from 1 to 0 or from 0 to 1 at each minimum data ui instant.
It is this feature that is exploited by a Clock Recovery module in a Clock Recovery and data delay circuit (Clock Recovery & data delay) to obtain a rising edge pulse, i.e. a recovered Clock signal Clk, at each ui instant (note that this signal is not a normal 50% duty cycle Clock signal). The clock recovery and Data delay circuit also has the function of delaying the first digital signal data_ab, the second digital signal data_bc and the third digital signal data_ca by a certain time and sampling by the clock. Specifically, the first delay module 201 delays the first digital signal data_ab to obtain a first delayed signal data_ab_delay, the second delay module 203 delays the second digital signal data_bc to obtain a second delayed signal data_bc_delay, and the third delay module 205 delays the third digital signal data_ca to obtain a third delayed signal data_ca_delay.
The frequency dividing circuit D1 divides the recovered clock signal Clk by 2 to obtain divided clock signals clk_div2, respectively. The three delay signals are respectively input into a first serial-parallel conversion module S1, a second serial-parallel conversion module S2 and a third serial-parallel conversion module S3, and three groups of parallel output data are obtained under the control of the two-frequency division clock signal. Specifically, the first delay signal data_ab_delay and the divide-by-two clock signal clk_div2 are input to the first serial-to-parallel conversion module S1, and the first serial-to-parallel conversion module S1 converts the serial first delay signal data_ab_delay into 7-bit parallel Data data_ab_ [ 1-6:0 ] under the control of the divide-by-two clock signal clk_div2. The second delay signal data_bc_delay and the divide-by-two clock signal clk_div2 are input to the second serial-to-parallel conversion module S2, and the second serial-to-parallel conversion module S2 converts the serial second delay signal data_bc_delay into 7-bit parallel Data data_bc_ [ 1-6:0 ] under the control of the divide-by-two clock signal clk_div2. The third delay signal data_ca_delay and the divide-by-two clock signal Clk_div2 are input into a third serial-to-parallel conversion module S3, and the third serial-to-parallel conversion module S3 converts the serial third delay signal data_ca_delay into 7-bit parallel Data data_ca_ [ 1-6:0 ] under the control of the divide-by-two clock signal Clk_div2.
Three paths of 7-bit parallel data are obtained through the data and clock recovery circuit and sent to a following decoder for decoding.
The first to third linear equalizers C1, C2 and C3 are used to process the signals on transmission lines A, B and C, as shown in fig. 4, axlove is the frequency response of the signals on transmission lines A, B and C after channel loss, and it can be seen that the high frequency (3 GHz) gain is more than 5dB less than the low frequency if gain, and the signal integrity has been lost. The low frequency and the intermediate frequency of the signal are properly attenuated by the linear equalizer, and the high frequency is properly compensated (e.g., B cut) to obtain a flat frequency response curve (e.g., C cut). And after gain compensation (superposition of C cut and D cut) as in fig. 5, a flat frequency response curve (e.g., E cut) in the 3GHz range is obtained. The signal integrity of the differential signals ab_p, ab_n, bc_p, bc_n, ca_p, and ca_n processed by the first to third linear equalizers C1, C2, and C3 is restored (as shown in fig. 7). After analog-to-digital conversion by comparators C4, C5, C6, data_ab, data_bc, data_ca are obtained (as shown in fig. 7). According to the C-PHY protocol, at least one transition occurs at each ui time instant. It is according to this characteristic that the clock Recovery and data delay circuit C7 obtains a normal phase pulse signal Recovery clock at each ui time instant, and obtains clk_div2 through the frequency dividing circuit D1 (divider). The Data signals data_ab, data_bc, and data_ca are delay-adjusted within the clock recovery and Data delay circuit C7 for later sampling by the divided-by-two clock signal clk_div2. The first to third serial-parallel conversion modules (sipo) S1, S2 and S3 sample three paths of data by using a binary frequency clock signal clk_div2, obtain three paths of 7-bit parallel data through serial-parallel conversion, and send the three paths of 7-bit parallel data to a decoder for decoding.
Fig. 3 shows a specific embodiment of a linear equalizer. Specifically, the linear equalizer includes a linear equalization circuit 301 and a differential amplification circuit 303. The linear equalization circuit 301 includes a current source i_source, a first transistor p1, a second transistor p2, a third transistor p3, a fourth transistor p4, a fifth transistor p5, a first resistor R1, and a second resistor R2. The first end of the first transistor p1 is used for being connected with a power supply VDD, the second end of the first transistor p1 is connected with the negative electrode of the current source I_source, the control end of the first transistor p1 is connected with the second end of the first transistor p1, the control end of the second transistor p2 and the control end of the third transistor p3, and the positive electrode of the current source I_source is used for being grounded. The first end of the second transistor p2 is connected to the power supply VDD, the second end of the second transistor p2 is connected to the first end of the fourth transistor p4, the first end of the third transistor p3 is connected to the power supply VDD, and the second end of the third transistor p3 is connected to the first end of the fifth transistor p 5. The second end of the fourth transistor p4 is connected to the first end of the first resistor R1, the second end of the first resistor R1 is grounded, the second end of the fifth transistor p5 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is grounded. The control terminal inp of the fourth transistor p4 serves as a first input terminal of the linear equalization circuit 301 and a first input terminal of the linear equalizer, and the control terminal inn of the fifth transistor p5 serves as a second input terminal of the linear equalization circuit 301 and a second input terminal of the linear equalizer. The second terminal of the fourth transistor p4 is used as the first output terminal net1 of the linear equalization circuit 301, and the second terminal of the fifth transistor p5 is used as the second output terminal net2 of the linear equalization circuit 301. It will be appreciated that the capacitor C shown in FIG. 3 is connected in parallel with the first resistor R1 L And a capacitor C connected in parallel with the second resistor R2 L Are parasitic capacitances of the circuit, caused by physical characteristics of the device, inIn some embodiments, the smaller the parasitic capacitance should be, the better.
In some embodiments, the current source i_source is provided by an external analog circuit module. The first transistor p1, the second transistor p2 and the third transistor p3 are PMOS transistors, the first ends of the first transistor p1, the second transistor p2 and the third transistor p3 are sources, the second ends of the first transistor p1, the second transistor p2 and the third transistor p3 are drains, and the control ends of the first transistor p1, the second transistor p2 and the third transistor p3 are gates. Under the action of the current source i_source, the first transistor p1 will obtain a suitable bias voltage, and since the control terminal of the first transistor p1 (i.e. the gate of the first transistor p 1) is connected to the control terminal of the second transistor p2 (i.e. the gate of the second transistor p 2) and the control terminal of the third transistor p3 (i.e. the gate of the third transistor p 3), the second transistor p2 and the third transistor p3 can provide an operating current for the branches below each other.
The fourth transistor p4 and the fifth transistor p5 are PMOS transistors, and form a differential pair transistor, and have the same size, and the resistance values of the first resistor R1 and the second resistor R2 are equal. In some embodiments, the first terminals of the fourth transistor p4 and the fifth transistor p5 are both sources, the second terminals of the fourth transistor p4 and the fifth transistor p5 are both drains, and the control terminals of the fourth transistor p4 and the fifth transistor p5 are both gates. Compared with the case of adopting NMOS tubes as differential pair tubes, the low input common-mode voltage can be supported.
Specifically, the lower limit of the input common mode voltage that such a structure can support is analyzed first. Let the input common-mode voltage be vin_com, according to vin_com>v_net1-Vth, where v_net1 is the voltage at the second end (i.e., drain) of the fourth transistor p4, v_net1=i p2 R 1 ，I p2 Is the current of the second transistor p2, R 1 Since the resistance of the first resistor R1 is set, v_net1 can be set to about 300mv at maximum by appropriately setting the current of the second transistor p2 and the resistance of the first resistor R1; vth is the threshold voltage of the fourth transistor p4, and the minimum value of Vth is generally 200mv. Therefore, vin_com>300mv-200mv＝100mv。
The upper limit of the input common mode voltage that this structure can support is then analyzed. According to Vin_com<V DD - (v_ds_p2+v_gs_p4), wherein V DD For the voltage of the power supply VDD, v_ds_p2 is the overdrive voltage of the second transistor p2, and may be set at 100mv, v_gs_p4 is the voltage between the control terminal of the fourth transistor p4 (i.e., the gate of the fourth transistor p 4) and the first terminal of the fourth transistor p4 (i.e., the source of the fourth transistor p 4), and may be set at about 300mv, so vin_com<V DD -400mv. In severe cases, V DD Is 720mv, so vin_com<320mv。
Based on the analysis, the differential pair transistors of the linear equalization circuit are formed by adopting the PMOS tubes, and the range of the input common-mode voltage which can be supported is as follows: 100mv < vin_com <320mv, it is fully possible to handle low common mode signal levels of 100-300 mv for C-PHY. The power consumption and the area cost caused by adding the source follower are avoided.
The linear equalization circuit 301 also includes a pole-zero adjustment module 3011 and a low frequency gain adjustment module 3013. The pole-zero adjustment module 3011 includes a sixth transistor p6, a seventh transistor p7, an eighth transistor p8, a ninth transistor p9, a first capacitance c1, and a second capacitance c2. The first end of the sixth transistor p6 is connected to the first end of the seventh transistor p7 through the first capacitor c1, the second end of the sixth transistor p6 is connected to the second end of the second transistor p2, the second end of the seventh transistor p7 is connected to the second end of the third transistor p3, and the control end of the sixth transistor p6 and the control end of the seventh transistor p7 are connected to form a first control end for receiving the first control signal cs_ [1]. The first end of the eighth transistor p8 is connected to the first end of the ninth transistor p9 through the second capacitor c2, the second end of the eighth transistor p8 is connected to the second end of the second transistor p2, the second end of the ninth transistor p9 is connected to the second end of the third transistor p3, and the control end of the eighth transistor p8 and the control end of the ninth transistor p9 are connected to form a second control end for receiving the second control signal cs_ [2].
In some embodiments, the sixth transistor p6 and the seventh transistor p7 are PMOS transistors, the first ends of the sixth transistor p6 and the seventh transistor p7 are sources, the second ends of the sixth transistor p6 and the seventh transistor p7 are drains, the control ends of the sixth transistor p6 and the seventh transistor p7 are gates, the control ends of the sixth transistor p6 and the seventh transistor p7 (i.e., the gates of the sixth transistor p6 and the seventh transistor p 7) are controlled by the first control signal cs_1, and the first control signal cs_1 is an adjustable register control signal. When cs_ [1] is low, the sixth transistor p6 and the seventh transistor p7 are turned on, and the first capacitor C1 is enabled between the first terminal of the fourth transistor p4 (i.e., the source of the fourth transistor p 4) and the first terminal of the fifth transistor p5 (i.e., the source of the fifth transistor p 5). When cs_ [1] is high, the sixth transistor p6 and the seventh transistor p7 are turned off, and the first capacitor C1 is not enabled.
Similarly, the eighth transistor p8 and the ninth transistor p9 are PMOS transistors, the first ends of the eighth transistor p8 and the ninth transistor p9 are sources, the second ends of the eighth transistor p8 and the ninth transistor p9 are drains, the control ends of the eighth transistor p8 and the ninth transistor p9 are gates, and the control ends of the eighth transistor p8 and the ninth transistor p9 (i.e., the gates of the eighth transistor p8 and the ninth transistor p 9) are controlled by the second control signal cs_2, and the second control signal cs_2 is an adjustable register control signal. When cs_ [2] is low, the eighth transistor p8 and the ninth transistor p9 are turned on, and the second capacitor C2 is enabled between the first terminal of the fourth transistor p4 (i.e., the source of the fourth transistor p 4) and the first terminal of the fifth transistor p5 (i.e., the source of the fifth transistor p 5). When cs_ [2] is high, the eighth transistor p8 and the ninth transistor p9 are turned off, and the second capacitor C2 is not enabled.
Whether the first capacitor C1 and the second capacitor C2 are enabled or not is adjusted through two control signals Cs_ [1] and Cs_ [2], the size of the total enabled capacitor Cs is adjusted, the zero position of the frequency response curve of the linear equalization circuit and the position of the first pole are further adjusted, and a formula related to the zero and the first pole and the total enabled capacitor Cs is given below.
The low frequency gain adjustment module 3013 includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a tenth transistor p10, and an eleventh transistor p11. The first end of the tenth transistor p10 is connected to the second end of the second transistor p2 through the third resistor R3, the second end of the tenth transistor p10 is connected to the second end of the third transistor p3 through the fourth resistor R4, and the control end of the tenth transistor p10 forms a third control end for receiving the third control signal rs_ [1]. The first end of the eleventh transistor p11 is connected to the second end of the second transistor p2 through the fifth resistor R5, the second end of the eleventh transistor p11 is connected to the second end of the third transistor p3 through the sixth resistor R6, and the control end of the eleventh transistor p11 forms a fourth control end for receiving the fourth control signal rs_ [2].
In some embodiments, the tenth transistor p10 is a PMOS transistor, the first terminal of the tenth transistor p10 is a source, the second terminal of the tenth transistor p10 is a drain, and the control terminal of the tenth transistor p10 is a gate. The control terminal of the tenth transistor p10 (the gate of the tenth transistor p 10) is controlled by a third control signal rs_ [1], which is an adjustable register control signal. When Rs_ [1] is at a low level, the tenth transistor p10 is turned on, and the third resistor R3 and the fourth resistor R4 are connected in series and then connected between the first terminal of the fourth transistor p4 (i.e., the source of the fourth transistor p 4) and the first terminal of the fifth transistor p5 (i.e., the source of the fifth transistor p 5). When rs_ [1] is at a high level, the tenth transistor p10 is turned off, and the connection of the third resistor R3 and the fourth resistor R4 is turned off.
Similarly, the eleventh transistor p11 is a PMOS transistor, the first terminal of the eleventh transistor p11 is a source, the second terminal of the eleventh transistor p11 is a drain, and the control terminal of the eleventh transistor p11 is a gate. The control terminal of the eleventh transistor p11 (i.e., the gate of p 11) is controlled by a fourth control signal Rs_ [2], which is an adjustable register control signal. When Rs_ [2] is low, the eleventh transistor p11 is turned on, and the fifth resistor R5 and the sixth resistor R6 are connected in series and then connected between the first terminal of the fourth transistor p4 (i.e., the source of the fourth transistor p 4) and the first terminal of the fifth transistor p5 (i.e., the source of the fifth transistor p 5). When Rs_ [2] is high, the eleventh transistor p11 is turned off, and the connection of the fifth resistor R5 and the sixth resistor R6 is turned off.
The two control signals rs_1 and rs_2 are used to adjust whether the third resistor R3 and the fourth resistor R4 are enabled or not and whether the fifth resistor R5 and the sixth resistor R6 are enabled or not, so as to adjust the magnitude of the total parallel resistor Rs, and further adjust the low frequency gain (which is obtained by a low frequency gain formula below) of the frequency response curve of the linear equalization circuit.
The linear equalization circuit serves to attenuate the low frequency signal amplitude and to maintain or slightly amplify the high frequency signal amplitude. AC analysis of the first input inp and the first output net1 of the linear equalizer 301 may result in the frequency response curve B of the linear equalizer as described in fig. 4. The frequency response curve can also be obtained from a formula. The total enabled capacitance of the first capacitor C1 and the second capacitor C2 is expressed by Cs, the total parallel resistance of the third to sixth resistors R3 to R6 is expressed by Rs, and the resistance of the first resistor R1 and the second resistor R2 is expressed by R D The representation is C for capacitance at net1 L The transconductance g of the fourth transistor p4 and the fifth transistor p5 is shown m And (3) representing. The frequency response formula of the linear equalization circuit can be deduced as:
from the above equation it can be seen that the transfer function has one zero and two poles. Zero pointFirst pole->Second pole->Low frequency gain->High frequency gain Ideal peak gain=g m R D 。
It can be seen from this that the zero point size depends on R s *C s R can be adjusted by adjusting the first to fourth control signals s *C s And then the size of the zero point is adjusted. It will be appreciated that the zero is a gain boost that may bring about a frequency of 20db/10 th of the frequency, and may be used to compensate for the attenuation of the channel. For example, the a curve in fig. 4 is a frequency response curve of the channel of the transmission link, and it can be seen that a significant decay occurs from a frequency of 1GHz if the zero point w is to be zero z Setting around 1GHz compensates back for attenuation around this frequency. Curve C of fig. 4 is a frequency response plot of the transmission link plus compensation by the linear equalization circuit. It can be seen that after equalizer compensation, the C-curve yields a relatively flat frequency response curve around 1 GHz.
With further reference to fig. 4, curve a is the frequency response curve of the channel of the transmission link, the low frequency band being approximately equal to 0db representing the ideal signal amplitude before unattenuated, the gain being slowly attenuated with increasing frequency, curve B is the frequency response curve of the linear equalization circuit, and the gain being increased with increasing frequency over a range of frequencies. The C-curve (i.e., the frequency response of the signal at the output of the equalizer circuit relative to the ideal signal before channel attenuation) is the frequency response curve of the transmission link plus the linear equalizer circuit. The equalizer is designed to perform superposition cancellation by using the rising section of the B curve and the falling section of the A curve, and a C curve with flatter frequency response is obtained by superposition of the two curves. It can be seen that the C-curve gives a relatively flat frequency response curve within 3 GHz.
It can be seen that the signal amplitude of the C curve in the frequency band below 3GHz is about-3.7 dB, which indicates that after the processing by the linear equalization circuit, although the gain of the C curve does not drop significantly in the 3GHz range as in the a curve, the gain is still reduced to-3.7 dB, which is equivalent to a reduction in the signal amplitude to 65% of the ideal signal. For weak 1 and weak 0 in the signal level of the C-PHY, if the ideal signal amplitude is about 100mv, the signal amplitude after the equalization circuit processes is only 65 mv. Such small signals are also challenging to work properly with later comparators. In this way, the equalization circuit can attenuate the low frequency signal while compensating the high frequency signal to obtain a signal with approximately equal high frequency and low frequency, but the signal amplitude is attenuated to 65% of the ideal signal.
For this purpose, the output end of the linear equalizer 301 is connected to the differential amplifying circuit 303, so that the output of the linear equalizer has a larger signal amplitude, and is convenient for the subsequent comparator to process. As shown in fig. 3, the differential amplification circuit 303 includes a twelfth transistor p12, a thirteenth transistor p13, a fourteenth transistor p14, a seventh resistor R7, and an eighth resistor R8. The first terminal of the twelfth transistor p12 is connected to the power supply VDD, the second terminal of the twelfth transistor p12 is connected to the first terminal of the thirteenth transistor p13 and the first terminal of the fourteenth transistor p14, and the control terminal of the twelfth transistor p12 is connected to the control terminal of the first transistor p 1. The second end of the thirteenth transistor p13 is connected to the first end of the seventh resistor R7, the control end of the thirteenth transistor p13 is used as the first input end of the differential amplifying circuit 303, connected to the first output end net1 of the linear equalizing circuit 301, the second end of the fourteenth transistor p14 is connected to the first end of the eighth resistor R8, and the control end of the fourteenth transistor p14 is used as the second input end of the differential amplifying circuit 303, connected to the second output end net2 of the linear equalizing circuit 301. The second end of the seventh resistor R7 is connected to ground, and the second end of the eighth resistor R8 is connected to ground. The second terminal of the thirteenth transistor p13 serves as the first output terminal outp of the differential amplifying circuit 303 and the first output terminal of the linear equalizer, and the second terminal of the fourteenth transistor p14 serves as the second output terminal outn of the differential amplifying circuit 303 and the second output terminal of the linear equalizer.
In some embodiments, the thirteenth transistor p13 and the fourteenth transistor p14 are differential pair transistors, the first ends of the thirteenth transistor p13 and the fourteenth transistor p14 are sources, the second ends of the thirteenth transistor p13 and the fourteenth transistor p14 are drains, the control ends of the thirteenth transistor p13 and the fourteenth transistor p14 are gates, the thirteenth transistor p13 and the fourteenth transistor p14 are PMOS transistors, and the seventh resistor R7 and the eighth resistor R8 have the same size. Since the control terminal of the twelfth transistor p12 (i.e., the gate of the twelfth transistor p 12) is connected to the control terminal of the first transistor p1 (i.e., the gate of the first transistor p 1), the twelfth transistor p12 can supply the operating current to the branch below it.
The differential amplifying circuit plays a role of Gain compensation for providing a Gain boost for the linear equalizer, specifically, gain=g of the differential amplifying circuit m ′R 7 Wherein g m ' is the transconductance of the thirteenth and fourteenth transistors p13 and p14, R 7 The resistance values of the seventh resistor R7 and the eighth resistor R8. As shown in fig. 5, the differential amplifying circuit can provide a gain of about 6dB (2 times) for the signal in the 3GHz range, and can amplify the signal (65%) attenuated by the equalizing circuit by two times, that is, 130% of the ideal signal is achieved, which provides a greater guarantee for the correct operation of the following comparator.
Fig. 6A is a signal eye diagram through a linear equalizer, jitter being 31ps; fig. 6B is a signal eye diagram before linear equalizer processing, jitter being 61.8ps. Illustrating that the jitter of the data signal is significantly reduced after linear equalizer processing.
FIG. 7 is a simulated timing diagram of an embodiment of the present invention. It can be seen that the input signal to the receiver has a weak-1 state differential voltage of 74.5mv for a-B at 1.73ns instant, the high frequency component having been attenuated by the transmission link (channel model). After the linear equalizer, the differential voltage of ab_p and ab_n is 175mv, the waveform is more neat, and the high-frequency component is also complemented back, so that each intersection point is more converged at an ideal ui moment point (jitter is smaller). The transition edges of the Data data_ab, data_bc, and data_ca thus restored are more converged at the ideal ui time point (i.e., jitter is smaller, eye diagram is significantly improved), and thus the resultant restored clock Recovery clock and jitter of the divided-by-2 clock clk_div2 are also smaller (34.6 ps).
The low-input common-mode linear equalizer circuit can well compensate high-frequency signals attenuated by signals in a transmission channel, but low-frequency signals are attenuated by the linear equalizer, for example, under a common 12nm process, the simulation can obtain a flat signal gain of-3.9 dB in 3 GHz. After the differential amplifying circuit is added (the gain of about 8dB can be provided), the flat signal gain of +4.1dB can be obtained in 3 GHz. It can be seen through the transient eye diagram that jitter of the signal amplified by the equalizer shaping and the differential amplifier is significantly reduced, which is important for MIPI C-PHY, which is a high-speed circuit that recovers a clock through a data transition edge. In addition, after the differential amplification circuit amplifies, the signal amplitude is improved to a large signal mode which is easier to process by the comparator, and powerful guarantee is provided for accurate recovery of data.
The invention also provides an MIPI C-PHY circuit, which comprises a data and clock recovery circuit; the data and clock recovery circuit is used for acquiring a first voltage of the first transmission line, a second voltage of the second transmission line and a third voltage of the third transmission line; the data and clock recovery circuit includes the linear equalizer described above for processing the first voltage, the second voltage, and the third voltage.
The MIPI C-PHY circuit further includes a decoder; the data and clock recovery circuit is used for synchronously sampling and converting data in series and parallel based on the difference value of the voltage signals processed by the linear equalizer, and then transmitting the data to the decoder for decoding.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Any process or method description in a flowchart or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more (two or more) executable instructions for implementing specific logical functions or steps of the process. And the scope of the preferred embodiments of the present application includes additional implementations in which functions may be performed in a substantially simultaneous manner or in an opposite order from that shown or discussed, including in accordance with the functions that are involved.
Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions.
It is to be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. All or part of the steps of the methods of the embodiments described above may be performed by a program that, when executed, comprises one or a combination of the steps of the method embodiments, instructs the associated hardware to perform the method.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules described above, if implemented in the form of software functional modules and sold or used as a stand-alone product, may also be stored in a computer-readable storage medium. The storage medium may be a read-only memory, a magnetic or optical disk, or the like.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think of various changes or substitutions within the technical scope of the present application, and these should be covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (6)
1. A MIPI C-PHY circuit comprising a transmitter, a transmission link, and a receiver; the receiver includes a data and clock recovery circuit including a linear equalizer having first and second inputs for acquiring two of a first voltage, a second voltage, and a third voltage output by the transmission link;
the linear equalizer comprises a linear equalizing circuit and a differential amplifying circuit;
the linear equalization circuit comprises a current source, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first resistor and a second resistor;
the first end of the first transistor is used for being connected with a power supply VDD, the second end of the first transistor is connected with the negative electrode of the current source, the control end of the first transistor is connected with the second end of the first transistor, the control end of the second transistor and the control end of the third transistor, and the positive electrode of the current source is used for being grounded; the first end of the second transistor is used for being connected with a power supply VDD, the second end of the second transistor is connected with the first end of the fourth transistor, the first end of the third transistor is used for being connected with the power supply VDD, and the second end of the third transistor is connected with the first end of the fifth transistor; the second end of the fourth transistor is connected with the first end of the first resistor, the second end of the first resistor is used for being grounded, the second end of the fifth transistor is connected with the first end of the second resistor, and the second end of the second resistor is used for being grounded;
The control end of the fourth transistor is used as the first input end of the linear equalization circuit and the first input end of the linear equalizer, the control end of the fifth transistor is used as the second input end of the linear equalization circuit and the second input end of the linear equalizer, the second end of the fourth transistor is used as the first output end of the linear equalization circuit, and the second end of the fifth transistor is used as the second output end of the linear equalization circuit;
the linear equalization circuit also comprises a low-frequency gain adjusting module and a zero pole adjusting module; the two ends of the low-frequency gain adjustment module are respectively connected with the second end of the second transistor and the second end of the third transistor, and the low-frequency gain adjustment module is used for attenuating low-frequency signals; the two ends of the pole-zero adjusting module are respectively connected with the second end of the second transistor and the second end of the third transistor, and the pole-zero adjusting module is used for adjusting the zero position of the frequency response curve of the linear equalization circuit and the position of the first pole; the low-frequency gain adjusting module and the pole-zero adjusting module together enable the transmission link to be added with the linear equalization circuit so as to obtain a flat frequency response curve;
The differential amplifying circuit is used for amplifying the output signal of the linear equalizing circuit so as to obtain larger signal amplitude.
2. The MIPI C-PHY circuit of claim 1, further comprising a decoder; the data and clock recovery circuit is used for synchronously sampling and converting data in series-parallel mode based on the difference value of the voltage signals processed by the linear equalizer, and transmitting the data to the decoder for decoding.
3. The MIPI C-PHY circuit of claim 1, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are PMOS transistors.
4. The MIPI C-PHY circuit of claim 1, wherein the pole-zero adjustment module comprises a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitance, and a second capacitance;
the first end of the sixth transistor is connected with the first end of the seventh transistor through the first capacitor, the second end of the sixth transistor is connected with the second end of the second transistor, the second end of the seventh transistor is connected with the second end of the third transistor, and the control end of the sixth transistor and the control end of the seventh transistor are connected to form a first control end for receiving a first control signal;
The first end of the eighth transistor is connected with the first end of the ninth transistor through the second capacitor, the second end of the eighth transistor is connected with the second end of the second transistor, the second end of the ninth transistor is connected with the second end of the third transistor, and the control end of the eighth transistor and the control end of the ninth transistor are connected to form a second control end for receiving a second control signal.
5. The MIPI C-PHY circuit of claim 1, wherein the low-frequency gain adjustment module comprises a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a tenth transistor, and an eleventh transistor;
the first end of the tenth transistor is connected with the second end of the second transistor through the third resistor, the second end of the tenth transistor is connected with the second end of the third transistor through the fourth resistor, and the control end of the tenth transistor forms a third control end and is used for receiving a third control signal;
the first end of the eleventh transistor is connected with the second end of the second transistor through the fifth resistor, the second end of the eleventh transistor is connected with the second end of the third transistor through the sixth resistor, and the control end of the eleventh transistor forms a fourth control end and is used for receiving a fourth control signal.
6. The MIPI C-PHY circuit of claim 1, wherein the differential amplification circuit comprises a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a seventh resistor, and an eighth resistor;
the first end of the twelfth transistor is used for being connected with a power supply VDD, the second end of the twelfth transistor is connected with the first end of the thirteenth transistor and the first end of the fourteenth transistor, the control end of the twelfth transistor is connected with the control end of the first transistor, the second end of the thirteenth transistor is connected with the first end of the seventh resistor, the second end of the seventh resistor is used for being grounded, the second end of the fourteenth transistor is connected with the first end of the eighth resistor, and the second end of the eighth resistor is used for being grounded;
the control end of the thirteenth transistor is used as the first input end of the differential amplifying circuit and is connected with the first output end of the linear equalizing circuit, the control end of the fourteenth transistor is used as the second input end of the differential amplifying circuit and is connected with the second output end of the linear equalizing circuit, the second end of the thirteenth transistor is used as the first output end of the differential amplifying circuit and the first output end of the linear equalizer, and the second end of the fourteenth transistor is used as the second output end of the differential amplifying circuit and the second output end of the linear equalizer.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108280039A (en) * | 2018-02-13 | 2018-07-13 | 龙迅半导体（合肥）股份有限公司 | A kind of input signal decoding circuit at the ends MIPI C-Phy RX |
| CN108353044A (en) * | 2015-10-28 | 2018-07-31 | 华为技术有限公司 | Combine low frequency and high frequency continuous time linear equalizer |
| CN110061940A (en) * | 2018-06-21 | 2019-07-26 | 南方科技大学 | A kind of equalizer system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108353044A (en) * | 2015-10-28 | 2018-07-31 | 华为技术有限公司 | Combine low frequency and high frequency continuous time linear equalizer |
| CN108280039A (en) * | 2018-02-13 | 2018-07-13 | 龙迅半导体（合肥）股份有限公司 | A kind of input signal decoding circuit at the ends MIPI C-Phy RX |
| CN110061940A (en) * | 2018-06-21 | 2019-07-26 | 南方科技大学 | A kind of equalizer system |
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